Mass trailing space removal for compiler.

compiler/README.txt

@@ -6,22 +6,22 @@ programmers manual.
 To recompile the compiler, you can use the batch files :
  + mppc386.bat    if you want to build a cross compiler from i386 to m68k
  + mppcsparc      if you want to build a cross compiler from i386 to SPARC
- 
+
  or
 Use the make utility as following
-  
+
       make OS_TARGET="compiler OS target" \
       CPU_TARGET="compiler CPU target" \
       FPCCPUOPT="Optimization level" \
       PP="compiler used to compile FPC" \
       COMPILER_OPTIONS="Options passed to compiler" \
-      
-      
+
+
 If an option is omitted, then target CPU/OS will be same as current CPU/OS
- 
+
 Possibles targets are : linux go32v2 win32 os2 freebsd beos netbsd amiga haiku
 atari sunos qnx netware openbsd wdosx palmos macos macosx emx
-   
+
 Possible compiler switches (* marks a currently required switch):
   -----------------------------------------------------------------
   GDB*                support of the GNU Debugger

compiler/aarch64/ncpuset.pas

@@ -61,7 +61,7 @@ implementation
       begin
         max_linear_list:=10;
       end;
-    
+
 
     function taarch64casenode.has_jumptable: boolean;
       begin
@@ -281,7 +281,7 @@ implementation
         if target_info.system=system_aarch64_win64 then
           begin
             { For windows, it has to be in a data section otherwise an access violation
-              will occur, but also full 64-bit references to avoid problems with 
+              will occur, but also full 64-bit references to avoid problems with
               relative references }
             sectype:=sec_rodata;
             new_section(current_procinfo.aktlocaldata,sectype,lower(current_procinfo.procdef.mangledname),sizeof(aint));

compiler/aasmdata.pas

@@ -111,7 +111,7 @@ interface
          sp_guids,
          sp_paraloc
       );
-      
+
     const
       AsmListTypeStr : array[TAsmListType] of string[24] =(
         'al_begin',

compiler/arm/aasmcpu.pas

@@ -1658,7 +1658,7 @@ implementation
 
 {$push}
 { Disable range and overflow checking here }
-{$R-}{$Q-}        
+{$R-}{$Q-}
     procedure fix_invalid_imms(list: TAsmList);
       var
         curtai: tai;

compiler/arm/agarmgas.pas

@@ -58,7 +58,7 @@ unit agarmgas;
       gas_shiftmode2str : array[tshiftmode] of string[3] = (
         '','lsl','lsr','asr','ror','rrx');
 
-    const 
+    const
       cputype_to_gas_march : array[tcputype] of string = (
         '', // cpu_none
         'armv2',

compiler/arm/cpubase.pas

@@ -607,7 +607,7 @@ unit cpubase;
 
 {$push}
 { Disable range and overflow checking here }
-{$R-}{$Q-}        
+{$R-}{$Q-}
     function is_thumb32_imm(d: aint): boolean;
       var
         t : aint;
@@ -641,14 +641,14 @@ unit cpubase;
               end;
           end;
       end;
-    
+
     function is_continuous_mask(d : aword;var lsb, width: byte) : boolean;
       var
         msb : byte;
       begin
         lsb:=BsfDword(d);
         msb:=BsrDword(d);
-        
+
         width:=msb-lsb+1;
         result:=(lsb<>255) and (msb<>255) and (aword(((1 shl (msb-lsb+1))-1) shl lsb) = d);
       end;

compiler/arm/cpuinfo.pas

@@ -288,7 +288,7 @@ Type
       ct_stm32f107rc,
       ct_stm32f107vb,
       ct_stm32f107vc,
-      
+
       ct_stm32f401cb,
       ct_stm32f401rb,
       ct_stm32f401vb,
@@ -431,10 +431,10 @@ Type
 
       { TI Stellaris }
       ct_lm4f120h5,
-      
+
       { SAMSUNG }
       ct_sc32442b,
-      
+
       { Infineon }
       ct_xmc4500x1024,
       ct_xmc4500x768,
@@ -505,7 +505,7 @@ Type
       ct_arduino_due,
       ct_flip_n_click,
       ct_wio_terminal,
-      
+
       { Nordic Semiconductor }
       ct_nrf51422_xxaa,
       ct_nrf51422_xxab,
@@ -739,7 +739,7 @@ Const
       (controllertypestr:'LPC2114';	controllerunitstr:'LPC21x4';	cputype:cpu_armv4t; fputype:fpu_soft; flashbase:$00000000;	flashsize:$00040000;	srambase:$40000000;	sramsize:$00004000),
       (controllertypestr:'LPC2124';	controllerunitstr:'LPC21x4';	cputype:cpu_armv4t; fputype:fpu_soft; flashbase:$00000000;	flashsize:$00040000;	srambase:$40000000;	sramsize:$00004000),
       (controllertypestr:'LPC2194';	controllerunitstr:'LPC21x4';	cputype:cpu_armv4t; fputype:fpu_soft; flashbase:$00000000;	flashsize:$00040000;	srambase:$40000000;	sramsize:$00004000),
-      
+
       (controllertypestr:'LPC1754';	controllerunitstr:'LPC1754';	cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00000000;	flashsize:$00020000;	srambase:$10000000;	sramsize:$00004000),
       (controllertypestr:'LPC1756';	controllerunitstr:'LPC1756';	cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00000000;	flashsize:$00040000;	srambase:$10000000;	sramsize:$00004000),
       (controllertypestr:'LPC1758';	controllerunitstr:'LPC1758';	cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00000000;	flashsize:$00080000;	srambase:$10000000;	sramsize:$00008000),
@@ -827,7 +827,7 @@ Const
       (controllertypestr:'STM32F107RC';     controllerunitstr:'STM32F10X_CL';     cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
       (controllertypestr:'STM32F107VB';     controllerunitstr:'STM32F10X_CL';     cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
       (controllertypestr:'STM32F107VC';     controllerunitstr:'STM32F10X_CL';     cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
-    
+
       (controllertypestr:'STM32F401CB';     controllerunitstr:'STM32F401XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
       (controllertypestr:'STM32F401RB';     controllerunitstr:'STM32F401XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
       (controllertypestr:'STM32F401VB';     controllerunitstr:'STM32F401XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
@@ -882,7 +882,7 @@ Const
       (controllertypestr:'NUCLEOF446RE';    controllerunitstr:'STM32F446XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00020000),
       (controllertypestr:'STM32F446VE';     controllerunitstr:'STM32F446XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00020000),
       (controllertypestr:'STM32F446ZE';     controllerunitstr:'STM32F446XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00020000),
- 
+
       (controllertypestr:'STM32F745XE';     controllerunitstr:'STM32F745';        cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20010000; sramsize:$00040000),
       (controllertypestr:'STM32F745XG';     controllerunitstr:'STM32F745';        cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00100000; srambase:$20010000; sramsize:$00040000),
       (controllertypestr:'STM32F746XE';     controllerunitstr:'STM32F746';        cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20010000; sramsize:$00040000),
@@ -971,7 +971,7 @@ Const
 
       { Samsung }
       (controllertypestr:'SC32442B';	controllerunitstr:'SC32442b';	cputype:cpu_armv4t; fputype:fpu_soft; flashbase:$00000000;	flashsize:$00000000;	srambase:$00000000;	sramsize:$08000000),
-      
+
       { Infinion }
       (controllertypestr:'XMC4500X1024';  controllerunitstr:'XMC4500'; cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000;	flashsize:$00100000;	srambase:$20000000;	sramsize:$00010000),
       (controllertypestr:'XMC4500X768';   controllerunitstr:'XMC4500'; cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000;	flashsize:$000C0000;	srambase:$20000000;	sramsize:$00010000),
@@ -1040,11 +1040,11 @@ Const
       (controllertypestr:'ATSAM3X8E';     controllerunitstr:'SAM3X8E'; cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00080000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
 
       (controllertypestr:'SAMD51P19A';    controllerunitstr:'SAMD51P19A'; cputype:cpu_armv7em; fputype:fpu_fpv4_sp_d16; flashbase:$00000000; flashsize:$00080000; srambase:$20000000; sramsize:$00030000),
-      
+
       (controllertypestr:'ARDUINO_DUE';   controllerunitstr:'SAM3X8E'; cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00080000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
       (controllertypestr:'FLIP_N_CLICK';  controllerunitstr:'SAM3X8E'; cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00080000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
       (controllertypestr:'WIO_TERMINAL'; controllerunitstr:'SAMD51P19A'   ; cputype:cpu_armv7em; fputype:fpu_fpv4_sp_d16; flashbase:$00004000; flashsize:$0007C000; srambase:$20000000; sramsize:$00030000),
-      
+
       { Nordic Semiconductor }
       (controllertypestr:'NRF51422_XXAA'; controllerunitstr:'NRF51'; cputype:cpu_armv6m; fputype:fpu_soft; flashbase:$00000000; flashsize:$00040000;      srambase:$20000000; sramsize:$00004000),
       (controllertypestr:'NRF51422_XXAB'; controllerunitstr:'NRF51'; cputype:cpu_armv6m; fputype:fpu_soft; flashbase:$00000000; flashsize:$00020000;      srambase:$20000000; sramsize:$00004000),
@@ -1054,7 +1054,7 @@ Const
       (controllertypestr:'NRF51822_XXAC'; controllerunitstr:'NRF51'; cputype:cpu_armv6m; fputype:fpu_soft; flashbase:$00000000; flashsize:$00040000;      srambase:$20000000; sramsize:$00008000),
       (controllertypestr:'NRF52832_XXAA'; controllerunitstr:'NRF52'; cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$00000000; flashsize:$00080000; srambase:$20000000; sramsize:$00010000),
       (controllertypestr:'NRF52840_XXAA'; controllerunitstr:'NRF52'; cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$00000000; flashsize:$00080000; srambase:$20000000; sramsize:$00010000),
-      
+
       { Raspberry Pi 2 }
       (controllertypestr:'RASPI2'; controllerunitstr:'RASPI2'; cputype:cpu_armv7a; fputype:fpu_vfpv4; flashbase:$00000000; flashsize:$00000000; srambase:$00008000; sramsize:$10000000),
 

compiler/arm/narmcal.pas

@@ -79,7 +79,7 @@ implementation
 
   procedure tarmcallnode.set_result_location(realresdef: tstoreddef);
     begin
-      if (realresdef.typ=floatdef) and 
+      if (realresdef.typ=floatdef) and
          (target_info.abi<>abi_eabihf) and
          (procdefinition.proccalloption<>pocall_hardfloat) and
          ((cs_fp_emulation in current_settings.moduleswitches) or

compiler/armgen/aoptarm.pas

@@ -1412,7 +1412,7 @@ Implementation
                     NewOp:=A_NONE;
                     if taicpu(hp1).oppostfix=PF_None then
                       NewOp:=A_MOV
-                    else 
+                    else
 {$ifdef ARM}
                       if (current_settings.cputype < cpu_armv6) then
                         begin
@@ -1676,7 +1676,7 @@ Implementation
             remove either the and or the lsl/xsr sequence if possible
           }
 
-          else if (taicpu(p).oper[2]^.val < high(int64)) and 
+          else if (taicpu(p).oper[2]^.val < high(int64)) and
 	    cutils.ispowerof2(taicpu(p).oper[2]^.val+1,i) and
             GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
             MatchInstruction(hp1, A_MOV, [taicpu(p).condition], [PF_None]) and

compiler/avr/cpuinfo.pas

@@ -487,7 +487,7 @@ Const
         (
         controllertypestr:'AVRSIM';
         controllerunitstr:'AVRSIM';
-        
+
         cputype: cpu_avr5;
         fputype: fpu_soft;
         flashbase:0;

compiler/cg64f32.pas

@@ -327,7 +327,7 @@ unit cg64f32;
           end;
         tmpref := ref;
 {$if defined(cpu8bitalu) or defined(cpu16bitalu)}
-        { Preload base and index to a separate temp register for 8 & 16 bit CPUs 
+        { Preload base and index to a separate temp register for 8 & 16 bit CPUs
           to reduce spilling and produce a better code. }
         if (tmpref.base<>NR_NO) and (getsupreg(tmpref.base)>=first_int_imreg) then
           begin
@@ -373,7 +373,7 @@ unit cg64f32;
           end;
         tmpref := ref;
 {$if defined(cpu8bitalu) or defined(cpu16bitalu)}
-        { Preload base and index to a separate temp register for 8 & 16 bit CPUs 
+        { Preload base and index to a separate temp register for 8 & 16 bit CPUs
           to reduce spilling and produce a better code. }
         if (tmpref.base<>NR_NO) and (getsupreg(tmpref.base)>=first_int_imreg) then
           begin

compiler/cgutils.pas

@@ -74,7 +74,7 @@ unit cgutils;
          base,
          index       : tregister;
          refaddr     : trefaddr;
-         scalefactor : byte;     
+         scalefactor : byte;
 {$if defined(riscv32) or defined(riscv64)}
          symboldata  : tlinkedlistitem;
 {$endif riscv32/64}

compiler/comprsrc.pas

@@ -45,7 +45,7 @@ type
       procedure Collect(const fn : ansistring);virtual;
       procedure EndCollect; virtual;
    end;
-   
+
    TWinLikeResourceFile = class(tresourcefile)
    private
       fResScript : TScript;
@@ -380,14 +380,14 @@ begin
   BlockRead(f, buf, SizeOf(buf), i);
   close(f);
   Filemode:=oldfmode;
-  
+
   if i<>SizeOf(buf) then
     exit;
 
   for i:=1 to 32 do
     if buf[i]<>ResSignature[i] then
       exit;
-      
+
   Result:=True;
 end;
 
@@ -456,7 +456,7 @@ begin
   src := nil;
   Result:=true;
 end;
- 
+
 procedure CompileResourceFiles;
 var
   resourcefile : tresourcefile;
@@ -524,7 +524,7 @@ end;
 procedure CollectResourceFiles;
 var
   resourcefile : tresourcefile;
-  
+
   procedure ProcessModule(u : tmodule);
   var
     res : TCmdStrListItem;
@@ -545,7 +545,7 @@ var
         res:=TCmdStrListItem(res.Next);
       end;
   end;
-  
+
 var
   hp : tused_unit;
   s : TCmdStr;

compiler/defcmp.pas

@@ -639,12 +639,12 @@ implementation
                         is_shortstring(def_to) then
                         eq:=te_equal
                      else if (tstringdef(def_to).stringtype=st_ansistring) and
-                             (tstringdef(def_from).stringtype=st_ansistring) then 
+                             (tstringdef(def_from).stringtype=st_ansistring) then
                       begin
                         { don't convert ansistrings if any condition is true:
                           1) same encoding
                           2) from explicit codepage ansistring to ansistring and vice versa
-                          3) from any ansistring to rawbytestring 
+                          3) from any ansistring to rawbytestring
                           4) from rawbytestring to any ansistring }
                         if (tstringdef(def_from).encoding=tstringdef(def_to).encoding) or
                            ((tstringdef(def_to).encoding=0) and (tstringdef(def_from).encoding=getansistringcodepage)) or
@@ -655,7 +655,7 @@ implementation
                            eq:=te_equal;
                          end
                         else
-                         begin        
+                         begin
                            doconv := tc_string_2_string;
 
                            { prefere conversion to utf8 codepage }
@@ -668,7 +668,7 @@ implementation
                            else
                              eq:=te_convert_l3;
                          end
-                      end          
+                      end
                      else
                      { same string type ? }
                       if (tstringdef(def_from).stringtype=tstringdef(def_to).stringtype) and

compiler/entfile.pas

@@ -1267,8 +1267,8 @@ end;
 
 {$ifndef FPC_HAS_TYPE_EXTENDED}
 {$ifdef FPC_SOFT_FPUX80}
-{ i8086,i386 and x86_64 normally have 80bit float type for 
-  entryreal, but this is not supported 
+{ i8086,i386 and x86_64 normally have 80bit float type for
+  entryreal, but this is not supported
   on CPUs without 80bit floats.
   Special code is required to handle this. }
 const

compiler/export.pas

@@ -71,7 +71,7 @@ type
       procedure generatelib;virtual;
       procedure setinitname(list: TAsmList; const s: string); virtual;
       procedure setfininame(list: TAsmList; const s: string); virtual;
-      
+
       property initname: string read finitname;
       property fininame: string read ffininame;
       property ignoreduplicates : boolean read fignoreduplicates write fignoreduplicates;
@@ -155,7 +155,7 @@ procedure exportname(const s : string; options: texportoptions);
           item:=TCmdStrListItem(item.next);
         end;
     end;
-    
+
 
   procedure exportallprocsymnames(ps: tprocsym; options: texportoptions);
     var

compiler/fppu.pas

@@ -1666,17 +1666,17 @@ var
                begin
                  dispose(ppufile.interface_crc_array);
                  ppufile.interface_crc_array:=interface_crc_array;
-               end; 
+               end;
              if assigned(ppufile.implementation_crc_array) then
                begin
                  dispose(ppufile.implementation_crc_array);
                  ppufile.implementation_crc_array:=implementation_crc_array;
-               end; 
+               end;
              if assigned(ppufile.indirect_crc_array) then
                begin
                  dispose(ppufile.indirect_crc_array);
                  ppufile.indirect_crc_array:=indirect_crc_array;
-               end; 
+               end;
            end;
          if FileExists(ppufilename+'.IMP',false) then
            RenameFile(ppufilename+'.IMP',ppufilename+'.IMP-old');

compiler/globals.pas

@@ -205,9 +205,9 @@ Const
          lineendingtype : tlineendingtype;
 
          whitespacetrimcount : word;
-         
+
          whitespacetrimauto : boolean;
-         
+
 {$if defined(generic_cpu)}
          case byte of
 {$endif}

compiler/globtype.pas

@@ -671,7 +671,7 @@ interface
          pocall_vectorcall
        );
        tproccalloptions = set of tproccalloption;
-       
+
        tlineendingtype = ({Carriage return, aka #13}
                           le_cr,
                           {Carriage return + line feed, aka #13#10}
@@ -682,7 +682,7 @@ interface
                           le_platform,
                           {Use whatever is in the file}
                           le_source);
-                          
+
      const
        proccalloptionStr : array[tproccalloption] of string[16]=('',
            'CDecl',

compiler/hlcgobj.pas

@@ -5202,7 +5202,7 @@ implementation
 {$else}
                { clear the whole register }
                mmreg:=newreg(R_MMREGISTER,getsupreg(tstaticvarsym(p).initialloc.register),R_SUBMMWHOLE);
-{$endif}             
+{$endif}
                a_opmm_reg_reg(TAsmList(arg),OP_XOR,tstaticvarsym(p).vardef, mmreg, mmreg,
                  { as we pass shuffle=nil, we have to pass a full register }
                  nil);

compiler/htypechk.pas

@@ -2485,7 +2485,7 @@ implementation
                 if assigned(srsym) and
                    (srsym.typ=procsym) and
                    (
-                     (tprocsym(srsym).procdeflist.count>0) or 
+                     (tprocsym(srsym).procdeflist.count>0) or
                      (sp_generic_dummy in srsym.symoptions)
                    ) then
                   begin

compiler/i8086/cgcpu.pas

@@ -2394,7 +2394,7 @@ unit cgcpu;
         var
           ref : treference;
         begin
-          if sp_moved then 
+          if sp_moved then
             exit;
           if not(pi_has_open_array_parameter in current_procinfo.flags) then
             exit;
@@ -2514,7 +2514,7 @@ unit cgcpu;
         a_load_loc_reg(list,OS_INT,lenloc,NR_DI);
         list.concat(Taicpu.op_reg(A_INC,S_W,NR_DI));
         { Now DI contains (high+1). }
-	
+
         include(current_procinfo.flags, pi_has_open_array_parameter);
 
         { special case handling for elesize=2:

compiler/jvm/cgcpu.pas

@@ -125,5 +125,5 @@ implementation
       begin
         cg:=tcgjvm.Create;
       end;
-      
+
 end.

compiler/llvm/llvmtype.pas

@@ -618,7 +618,7 @@ implementation
     procedure TLLVMTypeInfo.appendprocdef(list:TAsmList;def:tprocdef);
       begin
         { the procdef itself is already written by appendprocdef_implicit }
-      
+
         { last write the types from this procdef }
         if assigned(def.parast) then
           write_symtable_defs(current_asmdata.asmlists[al_start],def.parast);

compiler/m68k/ag68kgas.pas

@@ -266,7 +266,7 @@ interface
               end;
           top_const:
             getopstr_jmp:=tostr(o.val);
-          else 
+          else
             internalerror(200405022);
         end;
       end;

compiler/m68k/ag68kvasm.pas

@@ -108,7 +108,7 @@ unit ag68kvasm;
           internalerror(2016052601);
         end;
 
-        if (target_info.system = system_m68k_amiga) then 
+        if (target_info.system = system_m68k_amiga) then
           begin
             Replace(result,'$ASM',maybequoted(ScriptFixFileName(Unix2AmigaPath(AsmFileName))));
             Replace(result,'$OBJ',maybequoted(ScriptFixFileName(Unix2AmigaPath(ObjFileName))));

compiler/m68k/aoptcpu.pas

@@ -292,7 +292,7 @@ unit aoptcpu;
               opstr:=opname(p);
               case taicpu(p).oper[0]^.typ of
                 top_reg:
-                  { do not optimize away FPU to INT to FPU reg moves. These are used for 
+                  { do not optimize away FPU to INT to FPU reg moves. These are used for
                     to-single-rounding on FPUs which have no FSMOVE/FDMOVE. (KB) }
                   if not ((taicpu(p).opcode = A_FMOVE) and
                     (getregtype(taicpu(p).oper[0]^.reg) <> getregtype(taicpu(p).oper[1]^.reg))) then
@@ -417,7 +417,7 @@ unit aoptcpu;
         (taicpu(next).oper[1]^.ref^.base=NR_A7) and
         (taicpu(next).oper[1]^.ref^.index=NR_NO) and
         (taicpu(next).oper[1]^.ref^.symbol=nil) and
-        (taicpu(next).oper[1]^.ref^.direction=dir_none) and 
+        (taicpu(next).oper[1]^.ref^.direction=dir_none) and
         not (current_settings.cputype in cpu_coldfire) then
         begin
           DebugMsg('Optimizer: LEA, MOVE(M) to MOVE(M) predecremented',p);
@@ -592,7 +592,7 @@ unit aoptcpu;
                 if (taicpu(p).oper[0]^.typ = top_realconst) then
                   begin
                     if (taicpu(p).oper[0]^.val_real = 0.0) then
-                      begin 
+                      begin
                         DebugMsg('Optimizer: FCMP #0.0 to FTST',p);
                         taicpu(p).opcode:=A_FTST;
                         taicpu(p).opsize:=S_FX;

compiler/m68k/cgcpu.pas

@@ -672,11 +672,11 @@ unit cgcpu;
               list.concat(taicpu.op_reg_reg(A_SUB,S_L,register,register))
             else}
               { ISA B/C Coldfire has MOV3Q which can move -1 or 1..7 to any reg }
-              if (current_settings.cputype in [cpu_isa_b,cpu_isa_c,cpu_cfv4e]) and 
+              if (current_settings.cputype in [cpu_isa_b,cpu_isa_c,cpu_cfv4e]) and
                  ((longint(a) = -1) or ((longint(a) > 0) and (longint(a) < 8))) then
                 list.concat(taicpu.op_const_reg(A_MOV3Q,S_L,longint(a),register))
               else
-                { MOVEA.W will sign extend the value in the dest. reg to full 32 bits 
+                { MOVEA.W will sign extend the value in the dest. reg to full 32 bits
                   (specific to Ax regs only) }
                 if isvalue16bit(a) then
                   list.concat(taicpu.op_const_reg(A_MOVEA,S_W,longint(a),register))
@@ -697,8 +697,8 @@ unit cgcpu;
            else
              begin
                { ISA B/C Coldfire has sign extend/zero extend moves }
-               if (current_settings.cputype in [cpu_isa_b,cpu_isa_c,cpu_cfv4e]) and 
-                  (size in [OS_16, OS_8, OS_S16, OS_S8]) and 
+               if (current_settings.cputype in [cpu_isa_b,cpu_isa_c,cpu_cfv4e]) and
+                  (size in [OS_16, OS_8, OS_S16, OS_S8]) and
                   ((longint(a) >= low(smallint)) and (longint(a) <= high(smallint))) then
                  begin
                    if size in [OS_16, OS_8] then
@@ -877,7 +877,7 @@ unit cgcpu;
               a_load_reg_ref_unaligned(list,tosize,tosize,hreg,dref)
             else
               begin
-                { if we use a temp register, we don't need to fully resolve 
+                { if we use a temp register, we don't need to fully resolve
                   the dest ref, not even on coldfire }
                 fixref(list,bref,false);
                 list.concat(taicpu.op_reg_ref(A_MOVE,TCGSize2OpSize[tosize],hreg,bref));
@@ -1282,7 +1282,7 @@ unit cgcpu;
                 scratch_reg := force_to_dataregister(list, size, reg);
                 sign_extend(list, size, scratch_reg);
 
-                { some special cases which can generate smarter code 
+                { some special cases which can generate smarter code
                   using the SWAP instruction }
                 if (a = 16) then
                   begin
@@ -1539,7 +1539,7 @@ unit cgcpu;
         opcode := topcg2tasmop[op];
         opsize := TCGSize2OpSize[size];
 
-        { on ColdFire all arithmetic operations are only possible on 32bit 
+        { on ColdFire all arithmetic operations are only possible on 32bit
           and addressing modes are limited }
         if needs_unaligned(ref.alignment,size) or
            (not (CPUM68K_HAS_BYTEWORDMATH in cpu_capabilities[current_settings.cputype]) and (opsize <> S_L)) then
@@ -1582,7 +1582,7 @@ unit cgcpu;
         opcode := topcg2tasmop[op];
         opsize := TCGSize2OpSize[size];
 
-        { on ColdFire all arithmetic operations are only possible on 32bit 
+        { on ColdFire all arithmetic operations are only possible on 32bit
           and addressing modes are limited }
         if needs_unaligned(ref.alignment,size) or
            (not (CPUM68K_HAS_BYTEWORDMATH in cpu_capabilities[current_settings.cputype]) and (opsize <> S_L)) then
@@ -1603,7 +1603,7 @@ unit cgcpu;
               //list.concat(tai_comment.create(strpnew('a_op_ref_reg: normal op')));
               href:=ref;
               { Coldfire doesn't support d(Ax,Dx) for long MULx... }
-              fixref(list,href,(op in [OP_MUL,OP_IMUL]) and 
+              fixref(list,href,(op in [OP_MUL,OP_IMUL]) and
                                (current_settings.cputype in cpu_coldfire));
               list.concat(taicpu.op_ref_reg(opcode, opsize, href, reg));
             end;
@@ -1654,7 +1654,7 @@ unit cgcpu;
 
         if a = 0 then
           list.concat(taicpu.op_reg(A_TST,TCGSize2OpSize[size],reg))
-        else 
+        else
           begin
             { ColdFire ISA A also needs S_L for CMPI }
             { Note: older QEMU pukes from CMPI sizes <> .L even on ISA B/C, but
@@ -1677,7 +1677,7 @@ unit cgcpu;
       var
         tmpref: treference;
       begin
-        { optimize for usage of TST here, so ref compares against zero, which is the 
+        { optimize for usage of TST here, so ref compares against zero, which is the
           most common case by far in the RTL code at least (KB) }
         if not needs_unaligned(ref.alignment,size) and (a = 0) then
           begin
@@ -2064,8 +2064,8 @@ unit cgcpu;
         regs_to_save_fpu: tcpuregisterarray;
       begin
         { The code generated by the section below, particularly the movem.l
-          instruction is known to cause an issue when compiled by some GNU 
-          assembler versions (I had it with 2.17, while 2.24 seems OK.) 
+          instruction is known to cause an issue when compiled by some GNU
+          assembler versions (I had it with 2.17, while 2.24 seems OK.)
           when you run into this problem, just call inherited here instead
           to skip the movem.l generation. But better just use working GNU
           AS version instead. (KB) }
@@ -2319,7 +2319,7 @@ unit cgcpu;
           else
             ;
         end; { otherwise the size is already correct }
-      end; 
+      end;
 
     procedure tcg68k.sign_extend(list: TAsmList;_oldsize : tcgsize; reg: tregister);
       begin
@@ -2526,7 +2526,7 @@ unit cgcpu;
             end;
           { this is handled in 1st pass for 32-bit cpu's (helper call) }
           OP_IDIV,OP_DIV,
-          OP_IMUL,OP_MUL: 
+          OP_IMUL,OP_MUL:
             internalerror(2002081701);
           { this is also handled in 1st pass for 32-bit cpu's (helper call) }
           OP_SAR,OP_SHL,OP_SHR:

compiler/m68k/n68kinl.pas

@@ -56,7 +56,7 @@ interface
         procedure second_trunc_real; override;
         {procedure second_prefetch; override;
         procedure second_abs_long; override;}
-      protected 
+      protected
         function second_incdec_tempregdef: tdef; override;
       private
         procedure second_do_operation(op: TAsmOp);

compiler/m68k/n68kutil.pas

@@ -52,7 +52,7 @@ implementation
         def: tdef;
       begin
         inherited InsertObjectInfo;
-        if (not current_module.is_unit) and (target_info.system in [system_m68k_sinclairql]) then 
+        if (not current_module.is_unit) and (target_info.system in [system_m68k_sinclairql]) then
           begin
             { insert the main program name into the object. this will be set as default job name by the system unit }
             tcb:=ctai_typedconstbuilder.create([tcalo_new_section]);

compiler/macho.pas

@@ -54,10 +54,10 @@ type
 
 // mach/thread_status.h
 
-{$ifdef i386}  
+{$ifdef i386}
 
 {$endif i386}
-  
+
 // mach/machine.h
 
 type
@@ -74,8 +74,8 @@ const
   CPU_STATE_NICE		= 3;
 
   {* Capability bits used in the definition of cpu_type. }
-  CPU_ARCH_MASK	  = $ff000000;	{ mask for architecture bits } 
-  CPU_ARCH_ABI64	= $01000000;	{ 64 bit ABI } 
+  CPU_ARCH_MASK	  = $ff000000;	{ mask for architecture bits }
+  CPU_ARCH_ABI64	= $01000000;	{ 64 bit ABI }
 
   {	Machine types known by all. }
 
@@ -97,7 +97,7 @@ const
 
   CPU_TYPE_POWERPC	  = 18;
   CPU_TYPE_POWERPC64	= CPU_TYPE_POWERPC or CPU_ARCH_ABI64;
-  
+
 {*
  *	Machine subtypes (these are defined here, instead of in a machine
  *	dependent directory, so that any program can get all definitions
@@ -137,7 +137,7 @@ const
  *	ID assigned by DEC available via the SID register).
  *}
 
- 	CPU_SUBTYPE_VAX_ALL	= 0; 
+ 	CPU_SUBTYPE_VAX_ALL	= 0;
   CPU_SUBTYPE_VAX780	= 1;
   CPU_SUBTYPE_VAX785	= 2;
   CPU_SUBTYPE_VAX750	= 3;
@@ -157,7 +157,7 @@ const
  * The subtype definitions here are unusual for historical reasons.
  * NeXT used to consider 68030 code as generic 68000 code.  For
  * backwards compatability:
- * 
+ *
  *	CPU_SUBTYPE_MC68030 symbol has been preserved for source code
  *	compatability.
  *
@@ -196,12 +196,12 @@ const
   CPU_SUBTYPE_ITANIUM_2		   = 11 + (1 shl 4);
   CPU_SUBTYPE_XEON				   = 12 + (0 shl 4);
   CPU_SUBTYPE_XEON_MP			   = 12 + (1 shl 4);
-                                  
+
   CPU_SUBTYPE_INTEL_FAMILY_MAX	=  15;
   CPU_SUBTYPE_INTEL_MODEL_ALL	= 0;
 
   {* X86 subtypes. *}
- 
+
   CPU_SUBTYPE_X86_ALL		 = 3;
   CPU_SUBTYPE_X86_64_ALL = 3;
   CPU_SUBTYPE_X86_ARCH1	 = 4;
@@ -226,7 +226,7 @@ const
 
 {*
  *	HPPA subtypes for Hewlett-Packard HP-PA family of
- *	risc processors. Port by NeXT to 700 series. 
+ *	risc processors. Port by NeXT to 700 series.
  *}
 
  	CPU_SUBTYPE_HPPA_ALL		= 0;
@@ -234,7 +234,7 @@ const
   CPU_SUBTYPE_HPPA_7100LC	= 1;
 
   {* MC88000 subtypes. *}
-  
+
  	CPU_SUBTYPE_MC88000_ALL	= 0;
   CPU_SUBTYPE_MC88100	    = 1;
   CPU_SUBTYPE_MC88110	    = 2;
@@ -247,7 +247,7 @@ const
   CPU_SUBTYPE_I860_860	=  1;
 
   {* PowerPC subtypes *}
-  
+
   CPU_SUBTYPE_POWERPC_ALL		= 0;
   CPU_SUBTYPE_POWERPC_601		= 1;
   CPU_SUBTYPE_POWERPC_602		= 2;
@@ -292,15 +292,15 @@ const
   CPUFAMILY_ARM_9      = $e73283ae;
   CPUFAMILY_ARM_11     = $8ff620d8;
   CPUFAMILY_ARM_XSCALE = $53b005f5;
-  
+
   CPUFAMILY_INTEL_YONAH	  = CPUFAMILY_INTEL_6_14;
   CPUFAMILY_INTEL_MEROM	  = CPUFAMILY_INTEL_6_15;
   CPUFAMILY_INTEL_PENRYN	= CPUFAMILY_INTEL_6_23;
   CPUFAMILY_INTEL_NEHALEM	= CPUFAMILY_INTEL_6_26;
-  
+
   CPUFAMILY_INTEL_CORE	 = CPUFAMILY_INTEL_6_14;
   CPUFAMILY_INTEL_CORE2	 = CPUFAMILY_INTEL_6_15;
-  
+
 // mach/vm_prot.h
 type
   vm_prot_t = Integer;
@@ -357,7 +357,7 @@ const
 
   VM_PROT_WANTS_COPY = $10;
 
-  
+
 { Constant for the magic field of the mach_header (32-bit architectures)  the mach magic number  }
 
 const
@@ -436,7 +436,7 @@ const
 
 const
   { Constants for the flags field of the mach_header  }
-  
+
   MH_NOUNDEFS     = $1;   { the object file has no undefined references  }
   MH_INCRLINK     = $2;   { the object file is the output of an  incremental link against a base file and can't be link edited again  }
   MH_DYLDLINK     = $4;   { the object file is input for the dynamic linker and can't be staticly link edited again  }
@@ -566,21 +566,21 @@ type
    * section structures directly follow the segment command and their size is
    * reflected in cmdsize.
     }
-  
-  { for 32-bit architectures  }            
-  
-  segment_command = record           
-    cmd      : uint32_t;             { LC_SEGMENT  }                          
-    cmdsize  : uint32_t;             { includes sizeof section structs  }     
-    segname  : array[0..15] of char; { segment name  }                        
-    vmaddr   : uint32_t;             { memory address of this segment  }      
-    vmsize   : uint32_t;             { memory size of this segment  }         
-    fileoff  : uint32_t;             { file offset of this segment  }         
-    filesize : uint32_t;             { amount to map from the file  }         
-    maxprot  : vm_prot_t;            { maximum VM protection  }               
-    initprot : vm_prot_t;            { initial VM protection  }               
-    nsects   : uint32_t;             { number of sections in segment  }       
-    flags    : uint32_t;             { flags  }                               
+
+  { for 32-bit architectures  }
+
+  segment_command = record
+    cmd      : uint32_t;             { LC_SEGMENT  }
+    cmdsize  : uint32_t;             { includes sizeof section structs  }
+    segname  : array[0..15] of char; { segment name  }
+    vmaddr   : uint32_t;             { memory address of this segment  }
+    vmsize   : uint32_t;             { memory size of this segment  }
+    fileoff  : uint32_t;             { file offset of this segment  }
+    filesize : uint32_t;             { amount to map from the file  }
+    maxprot  : vm_prot_t;            { maximum VM protection  }
+    initprot : vm_prot_t;            { initial VM protection  }
+    nsects   : uint32_t;             { number of sections in segment  }
+    flags    : uint32_t;             { flags  }
   end;
   psegment_command = ^segment_command;
 
@@ -591,19 +591,19 @@ type
    * command and their size is reflected in cmdsize.
     }
   { for 64-bit architectures  }
-  
+
   segment_command_64 = record
-    cmd      : uint32_t;              { LC_SEGMENT_64  }                      
+    cmd      : uint32_t;              { LC_SEGMENT_64  }
     cmdsize  : uint32_t;              { includes sizeof section_64 structs  }
-    segname  : array[0..15] of char;  { segment name  }                      
-    vmaddr   : uint64_t;              { memory address of this segment  }    
-    vmsize   : uint64_t;              { memory size of this segment  }       
-    fileoff  : uint64_t;              { file offset of this segment  }       
-    filesize : uint64_t;              { amount to map from the file  }       
-    maxprot  : vm_prot_t;             { maximum VM protection  }             
-    initprot : vm_prot_t;             { initial VM protection  }             
-    nsects   : uint32_t;              { number of sections in segment  }     
-    flags    : uint32_t;              { flags  }                             
+    segname  : array[0..15] of char;  { segment name  }
+    vmaddr   : uint64_t;              { memory address of this segment  }
+    vmsize   : uint64_t;              { memory size of this segment  }
+    fileoff  : uint64_t;              { file offset of this segment  }
+    filesize : uint64_t;              { amount to map from the file  }
+    maxprot  : vm_prot_t;             { maximum VM protection  }
+    initprot : vm_prot_t;             { initial VM protection  }
+    nsects   : uint32_t;              { number of sections in segment  }
+    flags    : uint32_t;              { flags  }
   end;
   psegment_command_64 = ^segment_command_64;
 
@@ -616,18 +616,18 @@ const
 
   SG_FVMLIB = $2;  { this segment is the VM that is allocated by }
                    {	a fixed VM library, for overlap checking in }
-                   { the link editor  }                           
-   
+                   { the link editor  }
+
   SG_NORELOC = $4; { this segment has nothing that was relocated }
                    { in it and nothing relocated to it, that is  }
                    { it maybe safely replaced without relocation }
-     
+
   SG_PROTECTED_VERSION_1 = $8;  { This segment is protected.  If the    }
                                 {	segment starts at file offset 0, the  }
                                 {	first page of the segment is not      }
                                 {	protected.  All other pages of the    }
                                 {	segment are protected.                }
-     
+
   {* A segment is made up of zero or more sections.  Non-MH_OBJECT files have
    * all of their segments with the proper sections in each, and padded to the
    * specified segment alignment when produced by the link editor.  The first
@@ -730,9 +730,9 @@ const
   S_LAZY_DYLIB_SYMBOL_POINTERS = $10; { section with only lazy symbol pointers to lazy loaded dylibs  }
 
   {* Constants for the section attributes part of the flags field of a section structure.  }
-  
+
   SECTION_ATTRIBUTES_USR     = $ff000000; { User setable attributes  }
-  
+
   S_ATTR_PURE_INSTRUCTIONS   = $80000000; { section contains only true machine instructions  }
   S_ATTR_NO_TOC              = $40000000; { section contains coalesced symbols }
                                           { that are not to be in a ranlib table of contents  }
@@ -741,7 +741,7 @@ const
   S_ATTR_NO_DEAD_STRIP       = $10000000; { no dead stripping  }
   S_ATTR_LIVE_SUPPORT        = $08000000; { blocks are live if they reference live blocks  }
   S_ATTR_SELF_MODIFYING_CODE = $04000000; { Used with i386 code stubs written on by dyld  }
-  
+
   {
    * If a segment contains any sections marked with S_ATTR_DEBUG then all
    * sections in that segment must have this attribute.  No section other than
@@ -909,10 +909,10 @@ type
    * Zero or more sub_umbrella frameworks may be use by an umbrella framework.
    * The name of a sub_umbrella framework is recorded in the following structure.
     }
-  
+
   sub_umbrella_command = record
-    cmd           : uint32_t; { LC_SUB_UMBRELLA  }                
-    cmdsize       : uint32_t; { includes sub_umbrella string  }   
+    cmd           : uint32_t; { LC_SUB_UMBRELLA  }
+    cmdsize       : uint32_t; { includes sub_umbrella string  }
     sub_umbrella  : lc_str;   { the sub_umbrella framework name  }
   end;
 
@@ -929,11 +929,11 @@ type
    * shared libraries may be use by an umbrella framework or (or dynamic library).
    * The name of a sub_library framework is recorded in the following structure.
    * For example /usr/lib/libobjc_profile.A.dylib would be recorded as "libobjc".}
-   
+
   sub_library_command = record
-    cmd         : uint32_t; { LC_SUB_LIBRARY  }             
+    cmd         : uint32_t; { LC_SUB_LIBRARY  }
     cmdsize     : uint32_t; { includes sub_library string  }
-    sub_library : lc_str;   { the sub_library name  }       
+    sub_library : lc_str;   { the sub_library name  }
   end;
   psub_library_command = ^sub_library_command;
 
@@ -944,29 +944,29 @@ type
    * which are not (0) from the library.  The bit for module 0 is the low bit
    * of the first byte.  So the bit for the Nth module is:
    * (linked_modules[N/8] >> N%8) & 1 }
-  
+
   prebound_dylib_command = record
-    cmd      : uint32_t;     { LC_PREBOUND_DYLIB  }           
-    cmdsize  : uint32_t;     { includes strings  }            
-    name     : lc_str;       { library's path name  }         
+    cmd      : uint32_t;     { LC_PREBOUND_DYLIB  }
+    cmdsize  : uint32_t;     { includes strings  }
+    name     : lc_str;       { library's path name  }
     nmodules : uint32_t;     { number of modules in library  }
     linked_modules : lc_str; { bit vector of linked modules  }
   end;
   pprebound_dylib_command = ^prebound_dylib_command;
-       
-       
+
+
   {* A program that uses a dynamic linker contains a dylinker_command to identify
    * the name of the dynamic linker (LC_LOAD_DYLINKER).  And a dynamic linker
    * contains a dylinker_command to identify the dynamic linker (LC_ID_DYLINKER).
    * A file can have at most one of these.}
-  
+
   dylinker_command = record
     cmd     : uint32_t; { LC_ID_DYLINKER or LC_LOAD_DYLINKER  }
-    cmdsize : uint32_t; { includes pathname string  }          
-    name    : lc_str;   { dynamic linker's path name  }        
+    cmdsize : uint32_t; { includes pathname string  }
+    name    : lc_str;   { dynamic linker's path name  }
   end;
   pdylinker_command = ^dylinker_command;
-  
+
   {
    * Thread commands contain machine-specific data structures suitable for
    * use in the thread state primitives.  The machine specific data structures
@@ -988,14 +988,14 @@ type
    * created (based on the shell's limit for the stack size).  Command arguments
    * and environment variables are copied onto that stack.
     }
-  
+
   thread_command = record
-    cmd     : uint32_t; { LC_THREAD or  LC_UNIXTHREAD  }                                        
-    cmdsize : uint32_t; { total size of this command  }                                  
-    flavor  : uint32_t; { uint32_t flavor		   flavor of thread state  }                 
-    count   : uint32_t; { uint32_t count		   count of longs in thread state  }         
+    cmd     : uint32_t; { LC_THREAD or  LC_UNIXTHREAD  }
+    cmdsize : uint32_t; { total size of this command  }
+    flavor  : uint32_t; { uint32_t flavor		   flavor of thread state  }
+    count   : uint32_t; { uint32_t count		   count of longs in thread state  }
                         { struct XXX_thread_state state   thread state for this flavor  }
-                        { ...  }                                                         
+                        { ...  }
   end;
   pthread_command = ^thread_command;
 
@@ -1006,10 +1006,10 @@ type
    * and then calls it.  This gets called before any module initialization
    * routines (used for C++ static constructors) in the library.  }
   { for 32-bit architectures  }
-  
+
   routines_command = record
-    cmd     : uint32_t;       { LC_ROUTINES  }                      
-    cmdsize : uint32_t;       { total size of this command  }       
+    cmd     : uint32_t;       { LC_ROUTINES  }
+    cmdsize : uint32_t;       { total size of this command  }
     init_address : uint32_t;  { address of initialization routine  }
     init_module  : uint32_t;  { index into the module table that the init routine is defined in }
     reserved1 : uint32_t;
@@ -1023,13 +1023,13 @@ type
 
   { * The 64-bit routines command.  Same use as above. }
   { for 64-bit architectures  }
-  
+
   routines_command_64 = record
-    cmd     : uint32_t;         { LC_ROUTINES_64  }                   
-    cmdsize : uint32_t;         { total size of this command  }       
+    cmd     : uint32_t;         { LC_ROUTINES_64  }
+    cmdsize : uint32_t;         { total size of this command  }
     init_address : uint64_t;    { address of initialization routine  }
-    init_module  : uint64_t;    { index into the module table that  } 
-                                {  the init routine is defined in  }  
+    init_module  : uint64_t;    { index into the module table that  }
+                                {  the init routine is defined in  }
     reserved1 : uint64_t;
     reserved2 : uint64_t;
     reserved3 : uint64_t;
@@ -1045,12 +1045,12 @@ type
     }
 
   symtab_command = record
-    cmd     : uint32_t;  { LC_SYMTAB  }                       
-    cmdsize : uint32_t;  { sizeof(struct symtab_command)  }   
-    symoff  : uint32_t;  { symbol table offset  }             
-    nsyms   : uint32_t;  { number of symbol table entries  }  
-    stroff  : uint32_t;  { string table offset  }             
-    strsize : uint32_t;  { string table size in bytes  }      
+    cmd     : uint32_t;  { LC_SYMTAB  }
+    cmdsize : uint32_t;  { sizeof(struct symtab_command)  }
+    symoff  : uint32_t;  { symbol table offset  }
+    nsyms   : uint32_t;  { number of symbol table entries  }
+    stroff  : uint32_t;  { string table offset  }
+    strsize : uint32_t;  { string table size in bytes  }
   end;
   psymtab_command = ^symtab_command;
 
@@ -1284,13 +1284,13 @@ type
 
   {* The twolevel_hints_command contains the offset and number of hints in the
    * two-level namespace lookup hints table.}
- 
+
 type
   twolevel_hints_command = record
-    cmd     : uint32_t; { LC_TWOLEVEL_HINTS  }                    
+    cmd     : uint32_t; { LC_TWOLEVEL_HINTS  }
     cmdsize : uint32_t; { sizeof(struct twolevel_hints_command)  }
-    offset  : uint32_t; { offset to the hint table  }             
-    nhints  : uint32_t; { number of hints in the hint table  }    
+    offset  : uint32_t; { offset to the hint table  }
+    nhints  : uint32_t; { number of hints in the hint table  }
   end;
 
   {
@@ -1337,62 +1337,62 @@ type
    * cksum field of this load command in the output file.  If when the prebinding
    * is re-done and the cksum field is non-zero it is left unchanged from the
    * input file. }
-   
+
   prebind_cksum_command = record
-    cmd     : uint32_t; { LC_PREBIND_CKSUM  }                    
+    cmd     : uint32_t; { LC_PREBIND_CKSUM  }
     cmdsize : uint32_t; { sizeof(struct prebind_cksum_command)  }
-    cksum   : uint32_t; { the check sum or zero  }               
+    cksum   : uint32_t; { the check sum or zero  }
   end;
   pprebind_cksum_command = ^prebind_cksum_command;
-  
-       
+
+
   {* The uuid load command contains a single 128-bit unique random number that
    * identifies an object produced by the static link editor. }
 
-  uuid_command = record                
-    cmd     : uint32_t;                { LC_UUID  }                    
+  uuid_command = record
+    cmd     : uint32_t;                { LC_UUID  }
     cmdsize : uint32_t;                { sizeof(struct uuid_command)  }
-    uuid    : array[0..15] of uint8_t; { the 128-bit uuid  }           
+    uuid    : array[0..15] of uint8_t; { the 128-bit uuid  }
   end;
   puuid_command = ^uuid_command;
-  
-  
+
+
   {* The rpath_command contains a path which at runtime should be added to
    * the current run path used to find @rpath prefixed dylibs.}
-    
+
   rpath_command = record
-    cmd     : uint32_t; { LC_RPATH  }               
-    cmdsize : uint32_t; { includes string  }        
+    cmd     : uint32_t; { LC_RPATH  }
+    cmdsize : uint32_t; { includes string  }
     path    : lc_str;   { path to add to run path  }
   end;
   prpath_command = ^rpath_command;
 
-  
+
   {* The linkedit_data_command contains the offsets and sizes of a blob
    * of data in the __LINKEDIT segment.}
-  
+
   linkedit_data_command = record
     cmd      : uint32_t; { LC_CODE_SIGNATURE or LC_SEGMENT_SPLIT_INFO  }
-    cmdsize  : uint32_t; { sizeof(struct linkedit_data_command)  }      
-    dataoff  : uint32_t; { file offset of data in __LINKEDIT segment  } 
-    datasize : uint32_t; { file size of data in __LINKEDIT segment   }  
+    cmdsize  : uint32_t; { sizeof(struct linkedit_data_command)  }
+    dataoff  : uint32_t; { file offset of data in __LINKEDIT segment  }
+    datasize : uint32_t; { file size of data in __LINKEDIT segment   }
   end;
   plinkedit_data_command = ^linkedit_data_command;
-  
-  
+
+
   {* The encryption_info_command contains the file offset and size of an
    * of an encrypted segment.}
-  
+
   encryption_info_command = record
-    cmd       : uint32_t; { LC_ENCRYPTION_INFO  }                               
-    cmdsize   : uint32_t; { sizeof(struct encryption_info_command)  }           
-    cryptoff  : uint32_t; { file offset of encrypted range  }                   
-    cryptsize : uint32_t; { file size of encrypted range  }                     
+    cmd       : uint32_t; { LC_ENCRYPTION_INFO  }
+    cmdsize   : uint32_t; { sizeof(struct encryption_info_command)  }
+    cryptoff  : uint32_t; { file offset of encrypted range  }
+    cryptsize : uint32_t; { file size of encrypted range  }
     cryptid   : uint32_t; { which enryption system, 0 means not-encrypted yet  }
   end;
   pencryption_info_command = ^encryption_info_command;
-  
-  
+
+
   {* The symseg_command contains the offset and size of the GNU style
    * symbol table information as described in the header file <symseg.h>.
    * The symbol roots of the symbol segments must also be aligned properly
@@ -1400,12 +1400,12 @@ type
    * multiple of a 4 bytes translates to the length field of the symbol
    * roots also being a multiple of a long.  Also the padding must again be
    * zeroed. (THIS IS OBSOLETE and no longer supported). }
-  
+
   symseg_command = record
-    cmd     : uint32_t; { LC_SYMSEG  }                    
+    cmd     : uint32_t; { LC_SYMSEG  }
     cmdsize : uint32_t; { sizeof(struct symseg_command)  }
-    offset  : uint32_t; { symbol segment offset  }        
-    size    : uint32_t; { symbol segment size in bytes  } 
+    offset  : uint32_t; { symbol segment offset  }
+    size    : uint32_t; { symbol segment size in bytes  }
   end;
   psymseg_command = ^symseg_command;
 
@@ -1414,28 +1414,28 @@ type
    * ident_command structure.  The strings are null terminated and the size of
    * the command is padded out with zero bytes to a multiple of 4 bytes/
    * (THIS IS OBSOLETE and no longer supported).}
-  
+
   ident_command = record
-    cmd     : uint32_t; { LC_IDENT  }                        
+    cmd     : uint32_t; { LC_IDENT  }
     cmdsize : uint32_t; { strings that follow this command  }
   end;
   pident_command = ^ident_command;
-  
-  
+
+
   {* The fvmfile_command contains a reference to a file to be loaded at the
    * specified virtual address.  (Presently, this command is reserved for
    * internal use.  The kernel ignores this command when loading a program into
    * memory).  }
-  
+
   fvmfile_command = record
-    cmd         : uint32_t;  { LC_FVMFILE  }              
+    cmd         : uint32_t;  { LC_FVMFILE  }
     cmdsize     : uint32_t;  { includes pathname string  }
-    name        : lc_str;    { files pathname  }          
-    header_addr : uint32_t;  { files virtual address  }   
+    name        : lc_str;    { files pathname  }
+    header_addr : uint32_t;  { files virtual address  }
   end;
   pfvmfile_command = ^fvmfile_command;
 
-  
+
   {* This header file describes the structures of the file format for "fat"
    * architecture specific file (wrapper design).  At the begining of the file
    * there is one fat_header structure followed by a number of fat_arch

compiler/mips/aasmcpu.pas

@@ -553,7 +553,7 @@ procedure fixup_jmps(list: TAsmList);
           ait_instruction:
             { probleim here: pseudo-instructions can translate into
               several CPU instructions, possibly depending on assembler options,
-              to obe on safe side, let's assume a mean of two. } 
+              to obe on safe side, let's assume a mean of two. }
             inc(instrpos,2);
           ait_const:
             begin
@@ -680,16 +680,16 @@ procedure fixup_jmps(list: TAsmList);
 
 procedure resolveReadAfterWrite(list: TAsmList);
 label skip;
-var 
+var
     p, pp : tai;
     l, x : TLinkedListItem;
-    firstReg : tregister;    
+    firstReg : tregister;
 
 begin
 
   l:= list.first;
   while assigned(l) do begin
-      
+
     p:= tai(l);
     if p.typ = ait_instruction then begin
 
@@ -699,11 +699,11 @@ begin
 
           x:= l.next;
           if not assigned(x) then goto skip;
-          
+
           pp:= tai(x);
-    
+
           while pp.typ <> ait_instruction do begin
-            
+
             x:= x.next;
             if not assigned(x) then goto skip;
 
@@ -721,22 +721,22 @@ begin
 
                 0 : {nothing to do};
 
-                1 : 
+                1 :
                     if (taicpu(pp).oper[0]^.typ = top_reg) and (firstReg = taicpu(pp).oper[0]^.reg) then
                           list.insertAfter(taicpu.op_none(A_NOP), l);
 
                 2 :
-                    if ((taicpu(pp).oper[0]^.typ = top_reg) and (firstReg = taicpu(pp).oper[0]^.reg)) or 
-                       ((taicpu(pp).oper[1]^.typ = top_reg) and (firstReg = taicpu(pp).oper[1]^.reg)) or 
+                    if ((taicpu(pp).oper[0]^.typ = top_reg) and (firstReg = taicpu(pp).oper[0]^.reg)) or
+                       ((taicpu(pp).oper[1]^.typ = top_reg) and (firstReg = taicpu(pp).oper[1]^.reg)) or
                        ((taicpu(pp).oper[1]^.typ = top_ref) and (firstReg = taicpu(pp).oper[1]^.ref^.base)) then
                           list.insertAfter(taicpu.op_none(A_NOP), l);
 
                 3 :
-                    if ((taicpu(pp).oper[0]^.typ = top_reg) and (firstReg = taicpu(pp).oper[0]^.reg)) or 
+                    if ((taicpu(pp).oper[0]^.typ = top_reg) and (firstReg = taicpu(pp).oper[0]^.reg)) or
                        ((taicpu(pp).oper[1]^.typ = top_reg) and (firstReg = taicpu(pp).oper[1]^.reg)) or
                        ((taicpu(pp).oper[2]^.typ = top_reg) and (firstReg = taicpu(pp).oper[2]^.reg)) then
                           list.insertAfter(taicpu.op_none(A_NOP), l);
-                
+
                 else
 
                     internalerror(2024092501);
@@ -750,7 +750,7 @@ begin
       end;
 
     end;
-    
+
 skip:
     l:= l.next;
 

compiler/mips/aoptcpu.pas

@@ -320,7 +320,7 @@ unit aoptcpu;
                 move $t9,$reg
                 jalr $t9
 
-                if $reg is nonvolatile, its value may be used after call 
+                if $reg is nonvolatile, its value may be used after call
                 and we cannot safely replace it with $t9 }
               if (opcode=A_MOVE) and
                  (taicpu(next).oper[0]^.reg=NR_R25) and

compiler/mips/cgcpu.pas

@@ -1347,7 +1347,7 @@ begin
           { IEEE Double values are stored in floating point
             register pairs f2X/f2X+1,
             as the f2X+1 register is not correctly marked as used for now,
-            we simply assume it is also used if f2X is used 
+            we simply assume it is also used if f2X is used
             Should be fixed by a proper inclusion of f2X+1 into used_in_proc }
           if (ord(reg)-ord(RS_F0)) mod 2 = 0 then
             include(rg[R_FPUREGISTER].used_in_proc,succ(reg));

compiler/mips/cpubase.pas

@@ -351,10 +351,10 @@ unit cpubase;
         );
       begin
         result := inverse[c];
-      end;      
+      end;
       function findreg_by_number(r:Tregister):tregisterindex;
       begin
-        { the register table for MIPS cpu only contains 
+        { the register table for MIPS cpu only contains
           R_SUBFS and R_SUBD register types.
           This function is called by dbgstabs unit,
           here were are only interested in register,

compiler/mips/cpugas.pas

@@ -127,7 +127,7 @@ unit cpugas;
          Replace(result,'$FLOATABI',gas_float_option(current_settings.fputype));
          { ARCH selection }
          Replace(result,'$ARCH','-march='+lower(cputypestr[current_settings.cputype]));
-//          Replace(result,'$ARCH','-march=pic32mx -mtune=pic32mx');      
+//          Replace(result,'$ARCH','-march=pic32mx -mtune=pic32mx');
       end;
 
     procedure TMIPSGNUAssembler.WriteExtraHeader;

compiler/mips/cpuinfo.pas

@@ -62,8 +62,8 @@ Const
      pocall_cppdecl
    ];
 
-   { cpu strings as accepted by 
-     GNU assembler in -arch=XXX option 
+   { cpu strings as accepted by
+     GNU assembler in -arch=XXX option
      this ilist needs to be uppercased }
    cputypestr : array[tcputype] of string[8] = ('',
      { cpu_mips1        } 'MIPS1',

compiler/mips/cpupi.pas

@@ -154,7 +154,7 @@ implementation
 
     procedure tcpuprocinfo.postprocess_code;
       begin
-        
+
         fixup_jmps(aktproccode);
 
         if init_settings.cputype = cpu_mips1 then resolveReadAfterWrite(aktproccode);

compiler/ncgbas.pas

@@ -198,7 +198,7 @@ interface
                     MessagePos(filepos,asmr_e_invalid_reference_syntax);
                   { Subscribed access }
                   if forceref or
-{$ifdef avr}                     
+{$ifdef avr}
                      (sofs>=tcgsize2size[sym.localloc.size])
 {$else avr}
                      (sofs<>0)

compiler/ncgrtti.pas

@@ -1760,7 +1760,7 @@ implementation
              defaultpacking,reqalign,
              targetinfos[target_info.system]^.alignment.recordalignmin);
            { store special terminator for init table for more optimal rtl operations
-             strictly related to RecordRTTI procedure in rtti.inc (directly 
+             strictly related to RecordRTTI procedure in rtti.inc (directly
              related to RTTIRecordRttiInfoToInitInfo function) }
            if rt=initrtti then
              tcb.emit_tai(Tai_const.Create_nil_dataptr,voidpointertype)
@@ -2571,7 +2571,7 @@ implementation
             end;
           recorddef :
             begin
-              { guarantee initrtti for any record for RTTI purposes 
+              { guarantee initrtti for any record for RTTI purposes
                 also for fpc_initialize, fpc_finalize }
               if (rt=fullrtti) then
                 begin
@@ -2591,7 +2591,7 @@ implementation
 
               if (rt=fullrtti) then
                 begin
-                  { guarantee initrtti for any object for RTTI purposes 
+                  { guarantee initrtti for any object for RTTI purposes
                     also for fpc_initialize, fpc_finalize }
                   if (tobjectdef(def).objecttype=odt_object) then
                     begin

compiler/ncgset.pas

@@ -1329,7 +1329,7 @@ implementation
                               genjumptable(labels,min_label.svalue,max_label.svalue)
                             { value has been determined on an i7-4770 using a random case with random values
                               if more values are known, this can be handled depending on the target CPU
-                              
+
                               Testing on a Core 2 Duo E6850 as well as on a Raspi3 showed also, that 64 is
                               a good value }
                             else if labelcnt>=64 then

compiler/ncgutil.pas

@@ -630,7 +630,7 @@ implementation
               { The size of the stack parameter must be not less than
                 the size of the register because the spilling code for
                 most CPU targets spills whole registers.
-                
+
                 Spilling of sub registers is supported for x86.
               }
               if (paraloc<>nil) and (regsize>tcgsize2size[paraloc^.Size]) then

compiler/ogcoff.pas

@@ -585,7 +585,7 @@ implementation
          AddrNames,
          AddrOrds   : cardinal;
        end;
-       { MaybeSwap procedures 
+       { MaybeSwap procedures
        tcoffpedatadir = packed record
          vaddr : longword;
          size  : longword;
@@ -928,7 +928,7 @@ implementation
             v.AddrOrds:=SwapEndian(v.AddrOrds);
           end;
      end;
-  
+
      const
        SymbolMaxGrow = 200*sizeof(coffsymbol);
        StrsMaxGrow   = 8192;

compiler/ogelf.pas

@@ -624,7 +624,7 @@ implementation
 
 
     procedure TElfObjData.writereloc(data:aint;len:aword;p:TObjSymbol;reltype:TObjRelocationType);
-      type 
+      type
         multi = record
           case integer of
           0 : (ba : array[0..sizeof(aint)-1] of byte);

compiler/ogomf.pas

@@ -3372,7 +3372,7 @@ implementation
       begin
         debugsections:=nil;
         elfsechdrs:=nil;
-        
+
         { mark the offset of the start of the ELF image }
         elf_start_pos:=Writer.Size;
 

compiler/options.pas

@@ -219,7 +219,7 @@ begin
 end;
 
 procedure set_endianess_macros;
-  begin 
+  begin
     { endian define }
     case target_info.endian of
       endian_little :
@@ -5675,23 +5675,23 @@ begin
           init_settings.optimizerswitches:=[
                                           cs_opt_stackframe,
                                           cs_opt_size,              // makes smaller
-                                          cs_opt_uncertain, 
-                                          cs_opt_peephole, 
+                                          cs_opt_uncertain,
+                                          cs_opt_peephole,
                                           cs_opt_tailrecursion,
                                           cs_opt_nodecse,           // makes smaller - don't sets vars to 0
-                                          cs_opt_nodedfa, 
+                                          cs_opt_nodedfa,
                                           cs_opt_loopstrength,
-                                          cs_opt_reorder_fields, 
+                                          cs_opt_reorder_fields,
                                           cs_opt_dead_values,       // makes smaller
                                           cs_opt_remove_empty_proc, // makes smaller
-                                          cs_opt_dead_store_eliminate, 
-                                          cs_opt_forcenostackframe,                                          
+                                          cs_opt_dead_store_eliminate,
+                                          cs_opt_forcenostackframe,
                                           cs_opt_unused_para,       // makes smaller
                                           cs_opt_consts];
 
           // dont work: cs_opt_regvar, cs_opt_constant_propagate
           // dont compile: cs_opt_scheduler
-          // makes larger: cs_opt_autoinline 
+          // makes larger: cs_opt_autoinline
 }
         init_settings.optimizerswitches:=[];
         init_settings.debugswitches:= [];

compiler/optvirt.pas

@@ -177,7 +177,7 @@ unit optvirt;
       DEVIRT_SECTION_NAME = 'contextinsensitive_devirtualization';
 
    { *************************** tinheritancetreenode ************************* }
-    
+
     constructor tinheritancetreenode.create(_parent: tinheritancetreenode; _def: tobjectdef; _instantiated: boolean);
       begin
         fparent:=_parent;
@@ -223,7 +223,7 @@ unit optvirt;
     function tinheritancetreenode.maybeaddchild(_def: tobjectdef; _instantiated: boolean): tinheritancetreenode;
       begin
         { sanity check }
-        if assigned(_def.childof) then 
+        if assigned(_def.childof) then
           begin
             if (_def.childof<>def) then
               internalerror(2008092201);
@@ -277,7 +277,7 @@ unit optvirt;
         classrefdefs:=nil;
         inherited destroy;
       end;
-      
+
 
     function tinheritancetree.registerinstantiatedobjectdefrecursive(def: tobjectdef; instantiated: boolean): tinheritancetreenode;
       begin
@@ -376,7 +376,7 @@ unit optvirt;
 
 
     procedure tinheritancetree.foreachnodefromroot(root: tinheritancetreenode; proctocall: tinheritancetreecallback; arg: pointer);
-        
+
       procedure process(const node: tinheritancetreenode);
         var
          i: longint;
@@ -390,7 +390,7 @@ unit optvirt;
             else
               proctocall(node.childs[i],arg);
         end;
-        
+
       begin
         process(root);
       end;
@@ -414,7 +414,7 @@ unit optvirt;
             else
               proctocall(node.childs[i],arg);
         end;
-        
+
       begin
         process(froots);
       end;
@@ -461,7 +461,7 @@ unit optvirt;
               if { stop when this method does not exist in a parent }
                  (currnode.def.vmtentries.count<=i) then
                 break;
-              
+
               if not assigned(currnode.def.vmcallstaticinfo) then
                 currnode.def.vmcallstaticinfo:=allocmem(currnode.def.vmtentries.count*sizeof(tvmcallstatic));
               { if this method cannot be called, we can just mark it as

compiler/parser.pas

@@ -289,7 +289,7 @@ implementation
              unloaded_units:=nil;
            end;
          { Set default types to nil. At this point they are not valid class pointers. }
-         reset_all_default_types; 
+         reset_all_default_types;
 
          { if there was an error in the scanner, the scanner is
            still assinged }

compiler/pdecobj.pas

@@ -1715,7 +1715,7 @@ implementation
               end
             else
               olddef:=nil;
-              
+
             { if set explicitly, apply $RTTI directive to current object }
             if current_module.rtti_directive.clause<>rtc_none then
               current_structdef.apply_rtti_directive(current_module.rtti_directive)

compiler/pmodules.pas

@@ -2966,7 +2966,7 @@ type
 
          { global switches are read, so further changes aren't allowed }
          curr.in_global:=false;
-  
+
          { system unit is loaded, now insert feature defines }
          for feature:=low(tfeature) to high(tfeature) do
            if feature in features then

compiler/powerpc/agppcvasm.pas

@@ -89,7 +89,7 @@ unit agppcvasm;
         result:=asminfo^.asmcmd;
 
         objtype:='-Felf';
-        if (target_info.system in [system_powerpc_amiga, system_powerpc_morphos]) then 
+        if (target_info.system in [system_powerpc_amiga, system_powerpc_morphos]) then
           begin
             Replace(result,'$ASM',maybequoted(ScriptFixFileName(Unix2AmigaPath(AsmFileName))));
             Replace(result,'$OBJ',maybequoted(ScriptFixFileName(Unix2AmigaPath(ObjFileName))));

compiler/powerpc/cgcpu.pas

@@ -602,7 +602,7 @@ const
                tmpreg := getintregister(list, OS_INT);
                list.concat(taicpu.op_reg_reg(A_NEG, tmpreg, src1));
                list.concat(taicpu.op_reg_reg_reg_const_const(A_RLWNM, dst, src2, tmpreg, 0, 31));
-             end;       
+             end;
            else
              list.concat(taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1));
          end;

compiler/powerpc/nppcmat.pas

@@ -89,7 +89,7 @@ implementation
          size       : Tcgsize;
          hl : tasmlabel;
          done: boolean;
-         
+
          procedure genOrdConstNodeDiv;
          const
              negops : array[boolean] of tasmop = (A_NEG, A_NEGO);
@@ -128,7 +128,7 @@ implementation
                 cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, 0, resultreg);
              end else if (ispowerof2(tordconstnode(right).value, power)) then begin
                  if (is_signed(right.resultdef)) then begin
-                     
+
                      tempreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
                      maskreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
                      modreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
@@ -152,7 +152,7 @@ implementation
              end;
          end;
 
-         
+
       begin
          secondpass(left);
          secondpass(right);
@@ -529,7 +529,7 @@ implementation
                     end;
                   LOC_REGISTER, LOC_CREGISTER,
                   LOC_REFERENCE, LOC_CREFERENCE,
-                  LOC_SUBSETREG, LOC_CSUBSETREG, 
+                  LOC_SUBSETREG, LOC_CSUBSETREG,
                   LOC_SUBSETREF, LOC_CSUBSETREF:
                     begin
                       hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);

compiler/powerpc64/cgcpu.pas

@@ -255,7 +255,7 @@ begin
        RS_R9, RS_R10, RS_R11, RS_R12, RS_R31, RS_R30, RS_R29,
        RS_R28, RS_R27, RS_R26, RS_R25, RS_R24, RS_R23, RS_R22,
        RS_R21, RS_R20, RS_R19, RS_R18, RS_R17, RS_R16, RS_R15,
-       RS_R14], first_int_imreg, []);	
+       RS_R14], first_int_imreg, []);
   rg[R_FPUREGISTER] := trgcpu.create(R_FPUREGISTER, R_SUBNONE,
     [RS_F0, RS_F1, RS_F2, RS_F3, RS_F4, RS_F5, RS_F6, RS_F7, RS_F8, RS_F9,
      RS_F10, RS_F11, RS_F12, RS_F13, RS_F31, RS_F30, RS_F29, RS_F28, RS_F27,

compiler/powerpc64/cpubase.pas

@@ -366,7 +366,7 @@ const
   { the size of the "red zone" which must not be changed by asynchronous calls
    in the stack frame and can be used for storing temps }
   RED_ZONE_SIZE = 288;
-  
+
   { minimum size of the stack frame if one exists }
   MINIMUM_STACKFRAME_SIZE = 112;
   MINIMUM_STACKFRAME_SIZE_ELFV2 = 112 - 16;

compiler/powerpc64/cpuinfo.pas

@@ -110,7 +110,7 @@ Const
                                   cs_opt_tailrecursion,cs_opt_reorder_fields,cs_opt_fastmath];
 
    level1optimizerswitches = genericlevel1optimizerswitches;
-   level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches + 
+   level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
      [{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_stackframe,cs_opt_nodecse,cs_opt_tailrecursion];
    level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches;
    level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];

compiler/powerpc64/nppccal.pas

@@ -85,7 +85,7 @@ function tppccallnode.pass_1: tnode;
 
 procedure tppccallnode.do_syscall;
 begin
-  { no MorphOS style syscalls supported. Only implemented to avoid abstract 
+  { no MorphOS style syscalls supported. Only implemented to avoid abstract
    method not implemented compiler warning. }
   internalerror(2005120401);
 end;

compiler/powerpc64/rappcgas.pas

@@ -111,11 +111,11 @@ begin
       else if upper(actasmpattern) = 'HIGHERA' then
         oper.opr.ref.refaddr := addr_highera
       else if upper(actasmpattern) = 'HIGHESTA' then
-        oper.opr.ref.refaddr := addr_highesta        
+        oper.opr.ref.refaddr := addr_highesta
       else if upper(actasmpattern) = 'HIGHER' then
         oper.opr.ref.refaddr := addr_higher
       else if upper(actasmpattern) = 'HIGHEST' then
-        oper.opr.ref.refaddr := addr_highest                
+        oper.opr.ref.refaddr := addr_highest
       else
         Message(asmr_e_invalid_reference_syntax);
 

compiler/pp.pas

@@ -75,7 +75,7 @@ program pp;
                       MMX which allows the compiler to generate
                       MMX instructions
   -----------------------------------------------------------------
-  Switches automatically inside fpcdefs.inc  
+  Switches automatically inside fpcdefs.inc
   -----------------------------------------------------------------
   cpuflags            The target processor has status flags (on by default)
   cpufpemu            The target compiler will also support emitting software

compiler/ppcgen/aasmcpu.pas

@@ -435,7 +435,7 @@ uses cutils, cclasses;
       begin
         result := operand_read;
         case opcode of
-          A_STBU, A_STBUX, A_STHU, A_STHUX, A_STWU, A_STWUX, 
+          A_STBU, A_STBUX, A_STHU, A_STHUX, A_STWU, A_STWUX,
 {$ifdef cpu64bitalu}
           A_STDU, A_STDUX,
 {$endif cpu64bitalu}
@@ -523,7 +523,7 @@ uses cutils, cclasses;
               ait_const:
                 begin
                   if (tai_const(p).consttype<>aitconst_32bit) then
-                    internalerror(2008052101); 
+                    internalerror(2008052101);
                   inc(instrpos);
                 end;
               else

compiler/ppcgen/agppcgas.pas

@@ -72,7 +72,7 @@ unit agppcgas;
     topstr = string[4];
 
     function branchmode(o: tasmop): topstr;
-    function cond2str(op: tasmop; c: tasmcond): string;  
+    function cond2str(op: tasmop; c: tasmcond): string;
 
   implementation
 
@@ -515,11 +515,11 @@ unit agppcgas;
                 hp:=tai(current_asmdata.asmlists[hal].First);
                 while assigned(hp) do
                   begin
-                    case hp.typ of 
+                    case hp.typ of
                      ait_align :
                        begin
                          if tai_align_abstract(hp).aligntype > max_alignment[cur_sectype] then
-                           begin 
+                           begin
                              max_alignment[cur_sectype]:=tai_align_abstract(hp).aligntype;
                              current_asmdata.asmlists[hal].InsertAfter(tai_comment.Create(strpnew('Alignment put to '+tostr(tai_align_abstract(hp).aligntype))),hp);
                            end;
@@ -573,7 +573,7 @@ unit agppcgas;
         { make sure we always have a code and toc section,
           the linker expects that }
         writer.AsmWriteln(#9'.csect .text[PR],'+sectionalignment_aix(sec_code,max_alignment[sec_code]));
-        { set _text_s, to be used by footer below } 
+        { set _text_s, to be used by footer below }
         writer.AsmWriteln(#9'_text_s:');
         writer.AsmWriteln(#9'.toc');
       end;

compiler/ppcgen/ngppccnv.pas

@@ -150,7 +150,7 @@ implementation
                        cg.a_load_reg_reg(current_asmdata.CurrAsmList,opsize,opsize,left.location.register,hreg1);
                   end;
                 hreg2 := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
-                
+
                 if not(is_cbool(resultdef)) then
                   begin
                     { hreg2:=hreg1-1; carry:=hreg1=0 }

compiler/ppcgen/ngppcset.pas

@@ -61,7 +61,7 @@ implementation
     begin
       max_linear_list := 10;
     end;
-    
+
 
     function tgppccasenode.has_jumptable : boolean;
       begin

compiler/ppcgen/rgcpu.pas

@@ -86,13 +86,13 @@ unit rgcpu;
             tmpref:=spilltemp;
             tmpref.refaddr := addr_low;
             tmpref.base:=hreg;
-	    
+
             ins:=spilling_create_load(tmpref,tempreg);
             add_cpu_interferences(ins);
-	    
-	    
+
+
             helplist.concat(ins);
-	    
+
             if getregtype(tempreg)=R_INTREGISTER then
               ungetregisterinline(helplist,hreg);
 

compiler/ppu.pas

@@ -431,7 +431,7 @@ end;
 
 procedure tppufile.putdata(const b;len:integer);
 {$ifdef Test_Double_checksum}
-  var 
+  var
     pb : pbyte;
     ind : integer;
 {$endif Test_Double_checksum}

compiler/ptype.pas

@@ -1427,7 +1427,7 @@ implementation
                          def:=csetdef.create(cansichartype,torddef(cansichartype).low.svalue,torddef(cansichartype).high.svalue,true);
                        end
                      else
-                       Message(sym_e_ill_type_decl_set);  
+                       Message(sym_e_ill_type_decl_set);
                      end
                    else if (torddef(tt2).ordtype<>uvoid) and
                       (torddef(tt2).low>=0) then

compiler/rgobj.pas

@@ -648,7 +648,7 @@ unit rgobj;
           i8086 where indexed memory access instructions allow only
           few registers as arguments and additionally the calling convention
           provides no general purpose volatile registers.
-          
+
           Also spill registers which have the initial memory location
           and are used only once. This allows to access the memory location
           directly, without preloading it to a register.
@@ -1635,9 +1635,9 @@ unit rgobj;
         to get too much conflicts with the result that the spilling code
         will never converge (PFV)
 
-        We need a special processing for nodes with the ri_spill_helper flag set. 
+        We need a special processing for nodes with the ri_spill_helper flag set.
         These nodes contain a value of a previously spilled node.
-        We need to avoid another spilling of ri_spill_helper nodes, since it will 
+        We need to avoid another spilling of ri_spill_helper nodes, since it will
         likely lead to an endless loop and the register allocation will fail.
       }
       maxlength:=0;
@@ -2569,7 +2569,7 @@ unit rgobj;
                   begin
                     if (getregtype(reg)=regtype) then
                       begin
-                        {A register allocation of the spilled register (and all coalesced registers) 
+                        {A register allocation of the spilled register (and all coalesced registers)
                          must be removed.}
                         supreg:=get_alias(getsupreg(reg));
                         if supregset_in(regs_to_spill_set,supreg) then

compiler/riscv/agrvgas.pas

@@ -29,7 +29,7 @@ unit agrvgas;
 {$i fpcdefs.inc}
 
   interface
-  
+
     uses
        systems,aasmbase,
        aasmtai,aasmdata,

compiler/riscv/cgrv.pas

@@ -43,7 +43,7 @@ unit cgrv;
         procedure a_load_const_ref(list: TAsmList; size: tcgsize; a: tcgint; const ref: treference); override;
         procedure a_load_reg_ref(list: TAsmList; fromsize, tosize: TCGSize; reg: tregister; const ref: treference); override;
         procedure a_load_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
-        procedure a_load_const_reg(list: TAsmList; size: tcgsize; a: tcgint; register: tregister); override;            
+        procedure a_load_const_reg(list: TAsmList; size: tcgsize; a: tcgint; register: tregister); override;
 
         procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
         procedure a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
@@ -204,7 +204,7 @@ unit cgrv;
     procedure tcgrv.a_bit_scan_reg_reg(list: TAsmList; reverse,not_zero: boolean; srcsize, dstsize: tcgsize; src, dst: TRegister);
       begin
         internalerror(2016060401);
-      end;       
+      end;
 
 
     procedure tcgrv.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
@@ -546,12 +546,12 @@ unit cgrv;
             list.concat(taicpu.op_reg_reg_const(A_ADDI,r,href.base,href.offset));
           end
         else if (href.refaddr=addr_pcrel) then
-          begin                     
+          begin
             tmpreg:=getintregister(list,OS_ADDR);
 
             b:=href.base;
             href.base:=NR_NO;
-                                        
+
             current_asmdata.getjumplabel(l);
             a_label(list,l);
 
@@ -567,7 +567,7 @@ unit cgrv;
           end
         else
           internalerror(2016060504);
-      end;                
+      end;
 
 
     procedure tcgrv.a_cmp_const_reg_label(list: TAsmList; size: tcgsize; cmp_op: topcmp; a: tcgint; reg: tregister; l: tasmlabel);
@@ -634,7 +634,7 @@ unit cgrv;
       begin
         {reference_reset_symbol(href,l,0,0);
 
-        tmpreg:=getintregister(list,OS_ADDR);    
+        tmpreg:=getintregister(list,OS_ADDR);
 
         current_asmdata.getjumplabel(l);
         a_label(list,l);
@@ -701,7 +701,7 @@ unit cgrv;
                     inc(localsize,sizeof(pint));
                   end;
               end;
-               
+
             reference_reset_base(href,NR_STACK_POINTER_REG,stackcount,ctempposinvalid,0,[]);
 
             stackAdjust:=0;
@@ -802,11 +802,11 @@ unit cgrv;
                 postcompensation:=localsize-precompensation;
               end
             else
-              begin            
+              begin
                 precompensation:=0;
                 postcompensation:=localsize;
               end;
-            
+
             reference_reset_base(href,NR_STACK_POINTER_REG,postcompensation-stacksize,ctempposinvalid,0,[]);
 
             if precompensation>0 then
@@ -1071,7 +1071,7 @@ unit cgrv;
         tmpreg: TRegister;
       begin
         href:=ref;
-        fixref(list,href);    
+        fixref(list,href);
 
         if href.refaddr=addr_pcrel then
           begin
@@ -1177,7 +1177,7 @@ unit cgrv;
           end
         else if (ref.index=NR_NO) and
                 (ref.base=NR_NO) then
-          begin              
+          begin
             tmpreg:=getintregister(list,OS_INT);
 
             a_load_const_reg(list, OS_ADDR,ref.offset,tmpreg);

compiler/riscv/cpubase.pas

@@ -464,7 +464,7 @@ uses
          The value of this constant is equal to the constant
          PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
       }
-{$ifdef RISCV64}	  
+{$ifdef RISCV64}
       std_param_align = 8;
 {$endif RISCV64}
 {$ifdef RISCV32}

compiler/riscv/hlcgrv.pas

@@ -191,7 +191,7 @@ implementation
           op_onr12methodaddr;
         end
       else
-        begin                      
+        begin
           reference_reset_symbol(href,current_asmdata.RefAsmSymbol(procdef.mangledname,AT_FUNCTION),0,0,[]);
 
           tmpreg:=NR_X5;
@@ -219,7 +219,7 @@ implementation
 
   procedure thlcgriscv.g_external_wrapper(list: TAsmList; procdef: tprocdef; const wrappername, externalname: string; global: boolean);
     var
-      sym: tasmsymbol;   
+      sym: tasmsymbol;
       ai: taicpu;
       href: treference;
       tmpreg: TRegister;

compiler/riscv/nrvadd.pas

@@ -33,7 +33,7 @@ unit nrvadd;
     type
       trvaddnode = class(tcgaddnode)
         function pass_1: tnode; override;
-      protected                            
+      protected
         procedure Cmp(signed,is_smallset: boolean);
 
         function use_mul_helper: boolean; override;
@@ -44,7 +44,7 @@ unit nrvadd;
 
         procedure second_addordinal; override;
 
-        procedure pass_left_and_right;  
+        procedure pass_left_and_right;
 
         function use_fma: boolean; override;
 
@@ -99,7 +99,7 @@ implementation
                 hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
 
               if (right.location.loc=LOC_CONSTANT) and
-                 { right.location.value might be $8000000000000000, 
+                 { right.location.value might be $8000000000000000,
                    and its minus value generates an overflow here }
                  {$ifdef AVOID_OVERFLOW} ((right.location.value = low_value) or {$endif}
                  (not is_imm12(-right.location.value)) {$ifdef AVOID_OVERFLOW}){$endif} then
@@ -117,7 +117,7 @@ implementation
                 hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
 
               if (right.location.loc=LOC_CONSTANT) and
-                 { right.location.value might be $8000000000000000, 
+                 { right.location.value might be $8000000000000000,
                    and its minus value generates an overflow here }
                  {$ifdef AVOID_OVERFLOW} ((right.location.value = low_value) or {$endif}
                  (not is_imm12(-right.location.value)) {$ifdef AVOID_OVERFLOW}){$endif} then
@@ -244,7 +244,7 @@ implementation
                   not(is_signed(right.resultdef));
 
         Cmp(not unsigned,false);
-      end;                  
+      end;
 
 
     procedure trvaddnode.second_addordinal;

compiler/riscv/nrvset.pas

@@ -61,7 +61,7 @@ implementation
       begin
         max_linear_list:=3;
       end;
-    
+
 
     function trvcasenode.has_jumptable : boolean;
       begin

compiler/riscv32/cpuinfo.pas

@@ -189,7 +189,7 @@ Const
    level1optimizerswitches = genericlevel1optimizerswitches;
    level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches + [{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_nodecse,cs_opt_tailrecursion,cs_opt_consts];
    level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches;
-   level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_opt_stackframe]; 
+   level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_opt_stackframe];
 
  const
    cpu_capabilities : array[tcputype] of set of tcpuflags =

compiler/riscv32/cpupi.pas

@@ -44,7 +44,7 @@ unit cpupi;
 
           needs_frame_pointer: boolean;
           // procedure handle_body_start;override;
-          // procedure after_pass1;override;            
+          // procedure after_pass1;override;
           constructor create(aparent: tprocinfo); override;
           procedure set_first_temp_offset;override;
           function calc_stackframe_size:longint;override;
@@ -61,7 +61,7 @@ unit cpupi;
        cgutils,
        cgobj,
        defutil,
-       aasmcpu;     
+       aasmcpu;
 
 
     constructor trv32procinfo.create(aparent: tprocinfo);

compiler/riscv32/nrv32cnv.pas

@@ -73,9 +73,9 @@ implementation
     function trv32typeconvnode.first_int_to_real: tnode;
       var
         fname: string[19];
-      begin                                                        
+      begin
         if (cs_fp_emulation in current_settings.moduleswitches) then
-          result:=inherited first_int_to_real                      
+          result:=inherited first_int_to_real
         { converting a 64bit integer to a float requires a helper }
         else
           begin

compiler/riscv64/cgcpu.pas

@@ -38,7 +38,7 @@ unit cgcpu;
         procedure done_register_allocators; override;
 
         { move instructions }
-        procedure a_load_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;     
+        procedure a_load_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
         procedure a_load_const_reg(list: TAsmList; size: tcgsize; a: tcgint; register: tregister); override;
 
         procedure g_concatcopy(list: TAsmList; const source, dest: treference; len: aint); override;

compiler/riscv64/cpuinfo.pas

@@ -96,7 +96,7 @@ Const
                                   cs_opt_stackframe];
 
    level1optimizerswitches = genericlevel1optimizerswitches;
-   level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches + 
+   level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
      [{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_stackframe,cs_opt_nodecse,cs_opt_tailrecursion,cs_opt_consts];
    level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches;
    level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_opt_stackframe];

compiler/riscv64/cpunode.pas

@@ -32,7 +32,7 @@ uses
   ncgbas, ncgld, ncgflw, ncgcnv, ncgmem, ncgcon, ncgcal, ncgset, ncginl, ncgopt,
   ncgobjc,
   { symtable }
-  symcpu,           
+  symcpu,
   aasmdef,
   { to be able to only parts of the generic code,
     the processor specific nodes must be included

compiler/riscv64/nrv64cnv.pas

@@ -70,7 +70,7 @@ unit nrv64cnv;
     *****************************************************************************}
 
     function trv64typeconvnode.first_int_to_real: tnode;
-      begin                  
+      begin
         if (cs_fp_emulation in current_settings.moduleswitches) then
           result:=inherited first_int_to_real
         { converting a 64bit integer to a float requires a helper }

compiler/scandir.pas

@@ -1138,7 +1138,7 @@ unit scandir;
                 current_namespacelist.Insert(s)
               else // copied when correct module is activated
                 premodule_namespacelist.Insert(s);
-              s:='';  
+              s:='';
               if c=',' then
                 begin
                   current_scanner.readchar;

compiler/sparc/cpuinfo.pas

@@ -106,7 +106,7 @@ Const
                                   cs_opt_reorder_fields,cs_opt_fastmath];
 
    level1optimizerswitches = genericlevel1optimizerswitches;
-   level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches + 
+   level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
      [cs_opt_regvar,cs_opt_tailrecursion,cs_opt_nodecse,cs_opt_consts];
    level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches;
    level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];

compiler/sparc64/cpuinfo.pas

@@ -102,7 +102,7 @@ Const
                                   cs_opt_reorder_fields,cs_opt_fastmath];
 
    level1optimizerswitches = genericlevel1optimizerswitches;
-   level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches + 
+   level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
      [{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_tailrecursion,cs_opt_nodecse,cs_opt_consts];
    level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches;
    level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];

compiler/symdef.pas

@@ -2955,7 +2955,7 @@ implementation
         case stringtype of
           st_shortstring:
             result:=cshortstringtype;
-          { st_longstring is currently not supported but 
+          { st_longstring is currently not supported but
             when it is this case will need to be supplied }
           st_longstring:
             internalerror(2021040801);
@@ -5214,7 +5214,7 @@ implementation
     procedure tabstractrecorddef.apply_rtti_directive(dir: trtti_directive);
       begin
         { records don't support the inherit clause but shouldn't
-          give an error either if used (for Delphi compatibility), 
+          give an error either if used (for Delphi compatibility),
           so we silently enforce the clause as explicit. }
         rtti.clause:=rtc_explicit;
         rtti.options:=dir.options;
@@ -9714,7 +9714,7 @@ implementation
        bool8type:=nil;
        bool16type:=nil;
        bool32type:=nil;
-       bool64type:=nil;                
+       bool64type:=nil;
 {$ifdef llvm}
        llvmbool1type:=nil;             { LLVM i1 type }
 {$endif llvm}

compiler/symsym.pas

@@ -1561,9 +1561,9 @@ implementation
 
     function tprocsym.could_be_implicitly_specialized:boolean;
       begin
-        result:=(m_implicit_function_specialization in current_settings.modeswitches) and 
+        result:=(m_implicit_function_specialization in current_settings.modeswitches) and
                 (sp_generic_dummy in symoptions) and
-                assigned(genprocsymovlds);          
+                assigned(genprocsymovlds);
       end;
 
 {****************************************************************************

compiler/systems.pas

@@ -356,7 +356,7 @@ interface
          some newer instructions (like CMOVcc or PREFECTXXX) lead to troubles,
          related to OS or emulator lack of support. }
        systems_i386_default_486 = [system_i386_go32v2, system_i386_watcom,
-                                   system_i386_emx, system_i386_wdosx, 
+                                   system_i386_emx, system_i386_wdosx,
                                    system_i386_beos, system_i386_netware,
                                    system_i386_netwlibc, system_i386_symbian];
 

compiler/systems/i_beos.pas

@@ -90,15 +90,15 @@ unit i_beos;
                 maxCrecordalign : 4
               );
             first_parm_offset : 8;
-            { Stack size used to be 256 K under BeOS. So, it was the value 
-              used in previous version of FPC for BeOS (but lost in the road 
+            { Stack size used to be 256 K under BeOS. So, it was the value
+              used in previous version of FPC for BeOS (but lost in the road
               to 2.* ;-).
-              According to buildtools/gcc/gcc/config/i386/beos-elf.h in the 
+              According to buildtools/gcc/gcc/config/i386/beos-elf.h in the
               Haiku's repository, this value was increased to 1Mb since r4.1b3.
-              Under R5, this value is even greater. listarea report a default 
+              Under R5, this value is even greater. listarea report a default
               size of 16 Mb for the user stack of the main thread.
-              People who still use BeOS nowadays should use R5 (or Haiku), 
-              so i use this new value.  
+              People who still use BeOS nowadays should use R5 (or Haiku),
+              so i use this new value.
             }
             stacksize    : 16 * 1024 * 1024;
             stackalign   : 4;

compiler/systems/i_haiku.pas

@@ -92,14 +92,14 @@ unit i_haiku;
                 maxCrecordalign : 4
               );
             first_parm_offset : 8;
-            { Stack size used to be 256 K under BeOS. So, it was the value 
-              used in previous version of FPC for BeOS (but lost in the road 
+            { Stack size used to be 256 K under BeOS. So, it was the value
+              used in previous version of FPC for BeOS (but lost in the road
               to 2.* ;-).
-              According to buildtools/gcc/gcc/config/i386/beos-elf.h in the 
+              According to buildtools/gcc/gcc/config/i386/beos-elf.h in the
               Haiku's repository, this value was increased to 1Mb since r4.1b3.
-              Under R5, this value is even greater. listarea report a default 
+              Under R5, this value is even greater. listarea report a default
               size of 16 Mb for the user stack of the main thread.
-              People who still use BeOS nowadays should use R5 (or Haiku), 
+              People who still use BeOS nowadays should use R5 (or Haiku),
               so i use this new value.
             }
             stacksize    : 16 * 1024 * 1024;

compiler/systems/i_wii.pas

@@ -91,7 +91,7 @@ unit i_wii;
                 maxCrecordalign : 8
               );
             first_parm_offset : 8;
-            stacksize    : 131072;  // 128 kb 
+            stacksize    : 131072;  // 128 kb
             stackalign   : 16;
             abi : abi_powerpc_sysv;
             llvmdatalayout : 'E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32';

compiler/systems/mac_crea.txt

@@ -43,7 +43,7 @@ REQUEST ------------------------------------------------------------------------
 
 WEB CREATOR/FILE TYPE Registration Request
 ==========================================
-%UNIQUE REGISTRATION%: 
+%UNIQUE REGISTRATION%:
 %NAME%: Olle Raab
 %COMPANY%: Free Pascal Team
 %ADDRESS%: VikingavŠgen 28 A
@@ -52,7 +52,7 @@ Sweden
 %TELEPHONE%: +46-46-120053
 %E-MAIL%: [email protected]
 %PRODUCT NAME%: Free Pascal Compiler
-%DEVICE DRIVER%: 
+%DEVICE DRIVER%:
 %SIGNATURE (HEX)%: 46506173
 %END
 

compiler/systems/t_amiga.pas

@@ -89,7 +89,7 @@ end;
 
 procedure TLinkerAmiga.SetAmigaPPCInfo;
 begin
-  with Info do 
+  with Info do
    begin
     if not UseVLink then
      begin

compiler/systems/t_aros.pas

@@ -131,7 +131,7 @@ begin
   while assigned(HPath) do
    begin
     s:=HPath.Str;
-    s1 := Unix2AmigaPath(maybequoted(s)); 
+    s1 := Unix2AmigaPath(maybequoted(s));
     if trim(s1)<>'' then
      LinkRes.Add('SEARCH_DIR('+s1+')');
     HPath:=TCmdStrListItem(HPath.Next);

compiler/systems/t_freertos.pas

@@ -1642,7 +1642,7 @@ begin
           Info.ExeCmd[1]:=Info.ExeCmd[1]+' -T '+cntrlr+'.rom.rvfp.ld -T '+cntrlr+'.rom.newlib.ld -T '+cntrlr+'.rom.version.ld -T '+cntrlr+'.rom.newlib-nano.ld -T '+cntrlr+'.rom.heap.ld'
         else if idf_version>=50000 then
           Info.ExeCmd[1]:=Info.ExeCmd[1]+' -T '+cntrlr+'.rom.rvfp.ld -T '+cntrlr+'.rom.newlib.ld -T '+cntrlr+'.rom.version.ld -T '+cntrlr+'.rom.newlib-time.ld -T '+cntrlr+'.rom.newlib-nano.ld -T '+cntrlr+'.rom.heap.ld'
-        else 
+        else
           Comment(V_Error,'Unsupported esp-idf version specified');
 
       if current_settings.controllertype=ct_esp32c3 then

compiler/systems/t_gba.pas

@@ -74,12 +74,12 @@ Var
   i        : longint;
   HPath    : TCmdStrListItem;
   s,s1,s2  : TCmdStr;
-  prtobj, 
+  prtobj,
   cprtobj  : string[80];
   linklibc,
   linklibgcc : boolean;
   found1,
-  found2   : boolean;  
+  found2   : boolean;
 begin
   s:='';
   WriteResponseFile:=False;
@@ -129,8 +129,8 @@ begin
      if librarysearchpath.FindFile('crtbegin.o',false,s) then
       LinkRes.AddFileName(s);
    end;
-   
-  
+
+
   while not ObjectFiles.Empty do
    begin
     s:=ObjectFiles.GetFirst;
@@ -193,7 +193,7 @@ begin
      begin
       LinkRes.Add('-lc');
      end;
-    
+
    end
   else
    begin
@@ -216,7 +216,7 @@ begin
          LinkRes.AddFileName(s1);
         LinkRes.Add(')');
       end;
-   end;   
+   end;
   if linklibc then
    begin
      found2:=librarysearchpath.FindFile('crtn.o',false,s2);
@@ -227,8 +227,8 @@ begin
          LinkRes.AddFileName(s2);
         LinkRes.Add(')');
       end;
-   end;   
-   
+   end;
+
   with linkres do
     begin
       add('/* Linker Script Original v1.3 by Jeff Frohwein     */');
@@ -603,7 +603,7 @@ begin
         current_module.exefilename,true,false);
     end;
 
-  if success then 
+  if success then
     begin
       success:=DoExec(FindUtil('gbafix'), current_module.exefilename,true,false);
     end;

compiler/systems/t_linux.pas

@@ -384,7 +384,7 @@ begin
     The former contains library names qualified with prefix and suffix (coming from
     "external 'c' name 'foo' declarations), the latter contains raw names (from "$linklib c"
     directives). }
-  hp:=tmodule(loaded_units.first);  
+  hp:=tmodule(loaded_units.first);
   while assigned(hp) do
     begin
       result:=Assigned(hp.ImportLibraryList.find(target_info.sharedClibprefix+'c'+target_info.sharedClibext));

compiler/systems/t_nds.pas

@@ -77,7 +77,7 @@ Var
   i        : longint;
   HPath    : TCmdStrListItem;
   s,s1,s2  : TCmdStr;
-  prtobj, 
+  prtobj,
   cprtobj  : string[80];
   linklibc,
   linklibgcc : boolean;
@@ -105,7 +105,7 @@ begin
     else
       internalerror(2019050935);
   end;
-  
+
   if (linklibc or linklibgcc) then
     prtobj:=cprtobj;
 
@@ -231,7 +231,7 @@ begin
          LinkRes.AddFileName(s1);
         LinkRes.Add(')');
       end;
-   end;   
+   end;
   if linklibc then
    begin
      found2:=librarysearchpath.FindFile('crtn.o',false,s2);
@@ -242,8 +242,8 @@ begin
          LinkRes.AddFileName(s2);
         LinkRes.Add(')');
       end;
-   end;   
-   
+   end;
+
   with linkres do
     begin
       if apptype=app_arm9 then //ARM9
@@ -402,7 +402,7 @@ begin
         add('	.jcr            : { KEEP (*(.jcr)) } >ewram :main = 0');
         add('	.got            : { *(.got.plt) *(.got) *(.rel.got) } >ewram :main = 0');
         add('');
-        add('	.ewram ALIGN(4) :'); 
+        add('	.ewram ALIGN(4) :');
         add('	{');
         add('		__ewram_start = ABSOLUTE(.) ;');
         add('		*(.ewram)');
@@ -453,7 +453,7 @@ begin
         add('		__vectors_end = ABSOLUTE(.);');
         add('	} >vectors AT>ewram :vectors = 0xff');
         add('	');
-        add('	.sbss __dtcm_end (NOLOAD):'); 
+        add('	.sbss __dtcm_end (NOLOAD):');
         add('	{');
         add('		__sbss_start = ABSOLUTE(.);');
         add('		__sbss_start__ = ABSOLUTE(.);');
@@ -462,7 +462,7 @@ begin
         add('		__sbss_end = ABSOLUTE(.);');
         add('	} >dtcm :NONE');
         add('');
-        add('	.bss __bss_vma (NOLOAD):'); 
+        add('	.bss __bss_vma (NOLOAD):');
         add('	{');
         add('		__bss_start = ABSOLUTE(.);');
         add('		__bss_start__ = ABSOLUTE(.);');
@@ -836,7 +836,7 @@ begin
   Replace(cmdstr,'$GCSECTIONS',GCSectionsStr);
   Replace(cmdstr,'$MAP',MapStr);
   Replace(cmdstr,'$DYNLINK',DynLinkStr);
-  
+
   success:=DoExec(FindUtil(utilsprefix+BinStr),cmdstr,true,false);
 
 { Remove ReponseFile }
@@ -846,16 +846,16 @@ begin
 { Post process }
   if success then
     begin
-      success:=DoExec(FindUtil(utilsprefix + 'objcopy'), '-O binary '+ 
-        ChangeFileExt(current_module.exefilename, preName) + ' ' + 
+      success:=DoExec(FindUtil(utilsprefix + 'objcopy'), '-O binary '+
+        ChangeFileExt(current_module.exefilename, preName) + ' ' +
         ChangeFileExt(current_module.exefilename, preName+target_info.exeext),
         true,false);
     end;
 
-  if success and (apptype=app_arm9) then 
+  if success and (apptype=app_arm9) then
     begin
-      success:=DoExec(FindUtil('ndstool'), '-c ' + 
-        ChangeFileExt(current_module.exefilename, '.nds') + ' -9 ' + 
+      success:=DoExec(FindUtil('ndstool'), '-c ' +
+        ChangeFileExt(current_module.exefilename, '.nds') + ' -9 ' +
         ChangeFileExt(current_module.exefilename, preName+target_info.exeext),
         true,false);
     end;

compiler/systems/t_ps1.pas

@@ -93,9 +93,9 @@ begin
     HPath:= TCmdStrListItem(LibrarySearchPath.First);
     while assigned(HPath) do begin
       s:= HPath.Str;
-      
+
       if s <> '' then LinkRes.Add('SEARCH_DIR("' + s + '")');
-      
+
       HPath:= TCmdStrListItem(HPath.Next);
     end;
 
@@ -103,7 +103,7 @@ begin
     while not ObjectFiles.Empty do begin
         LinkRes.Add('INPUT(' + ExtractFileName(ObjectFiles.GetFirst) + ')');
     end;
-    
+
 
     LinkRes.Add('INPUT(libcard.a libpress.a libgpu.a libgs.a libgte.a)');
     LinkRes.Add('INPUT(libcd.a libetc.a libsn.a libsnd.a libspu.a)');
@@ -235,11 +235,11 @@ end;
 
 
 procedure write0till(var f: file; k: dWord);
-var 
+var
     b : byte;
 
 begin
-  
+
   b:= 0;
   repeat
     BlockWrite(f, b, 1);
@@ -260,7 +260,7 @@ var
 begin
 
   result:= false;
-  
+
   AssignFile(f, name + '.bin');
   {$I-} reset(f, 1); {$I+}
   if ioResult <> 0 then exit;
@@ -269,7 +269,7 @@ begin
     Message3(link_f_executable_too_big_exceeds_X_by_Y_bytes,'PS1','2097152',tostr(filesize(f)-$200000));
     exit;
   end;
-  
+
   close(f);
 
   AssignFile(f, name + '.psx-exe');
@@ -354,7 +354,7 @@ begin
 
     DeleteFile(outputexedir + Info.ResName);
 
-    
+
     if not FileCopy(current_module.exefilename + '.elf', current_module.exefilename + '.bin', 0) then begin
       writeln('Cant Write ' + current_module.exefilename + '.bin File!');
       result:= false;
@@ -371,7 +371,7 @@ begin
       exit;
     end;
 
-   
+
     success:= CreatePSXEXE(current_module.exefilename);
     if not success then begin
       writeln('Create PSX-EXE failed!');

compiler/systems/t_sinclairql.pas

@@ -305,7 +305,7 @@ begin
   MakeSinclairQLExe:=DoExec(BinStr,CmdStr,true,false);
 
   { Kludge:
-      With the above linker script, vlink will produce two files. The main binary 
+      With the above linker script, vlink will produce two files. The main binary
       and the relocation info. Here we copy the two together. (KB) }
   if MakeSinclairQLExe and not sinclairql_vlink_experimental then
     begin
@@ -317,7 +317,7 @@ begin
       bufsize:=16384;
 {$push}
 {$i-}
-      { Rename vlink's output file into the header file it is, then parse the 
+      { Rename vlink's output file into the header file it is, then parse the
         expected length from it. Later we use either this size or the final binary
         size in the BASIC loader, depending on which one is bigger. (KB) }
       RenameFile(ExeName,HdrName);

compiler/systems/t_wii.pas

@@ -77,7 +77,7 @@ Var
   linklibc,
   linklibgcc  : boolean;
   found1,
-  found2   : boolean;    
+  found2   : boolean;
 begin
   WriteResponseFile:=False;
   linklibc:=(SharedLibFiles.Find('c')<>nil);
@@ -123,8 +123,8 @@ begin
      if librarysearchpath.FindFile('crtmain.o',false,s) then
       LinkRes.AddFileName(s);
    end;
-   
-   
+
+
   while not ObjectFiles.Empty do
    begin
     s:=ObjectFiles.GetFirst;
@@ -187,7 +187,7 @@ begin
      begin
       LinkRes.Add('-lc');
      end;
-     
+
    end
   else
    begin
@@ -210,7 +210,7 @@ begin
          LinkRes.AddFileName(s1);
         LinkRes.Add(')');
       end;
-   end;   
+   end;
   if linklibc then
    begin
      found2:=librarysearchpath.FindFile('ecrtn.o',false,s2);
@@ -221,7 +221,7 @@ begin
          LinkRes.AddFileName(s2);
         LinkRes.Add(')');
       end;
-   end;   
+   end;
   with linkres do
    begin
     add('/*');
@@ -529,8 +529,8 @@ begin
     add('PROVIDE(__ipcbufferHi = __ipcbufferHi);');
     add('PROVIDE(__gxregs = __gxregs);');
    end;
-   
-   
+
+
 { Write and Close response }
   linkres.writetodisk;
   linkres.free;
@@ -584,12 +584,12 @@ begin
 { Remove ReponseFile }
   if (success) and not(cs_link_nolink in current_settings.globalswitches) then
    DeleteFile(outputexedir+Info.ResName);
-   
+
 { Post process }
 
-  if success then 
+  if success then
    begin
-    success:=DoExec(FindUtil('elf2dol'),ChangeFileExt(current_module.exefilename,'.elf')+' '+ 
+    success:=DoExec(FindUtil('elf2dol'),ChangeFileExt(current_module.exefilename,'.elf')+' '+
      current_module.exefilename,true,false);
    end;
   MakeExecutable:=success;   { otherwise a recursive call to link method }

compiler/utils/README.txt

@@ -4,7 +4,7 @@ development of the Free Pascal Compiler.
 msg2inc  : Convert a compiler message file (errorX.msg) to .inc files to
            include it as the default language in the compiler. It can
            also convert the .msg to .tex for inclusion the documentation
-	  
+
 nasmconv : Convert a Nasm insns.dat to i386tab.inc so it can be used with
            the compiler