+ fpc_riscv_pause

compiler/compinnr.pas

@@ -226,6 +226,10 @@ type
 {$if defined(AARCH64)}
      ,
      {$i ccpuinnr.inc}
+{$endif}
+{$if defined(RISCV)}
+     ,
+     {$i ccpuinnr.inc}
 {$endif}
    );
 

compiler/riscv/cpubase.pas

@@ -179,6 +179,9 @@ uses
 //        A_FCVT_D_S,A_FCVT_S_D,
 //        A_FCVT_W_D,A_FCVT_WU_D,A_FCVT_D_W,A_FCVT_D_WU,
 
+        { Zihintpause }
+        A_PAUSE,
+
         { Machine mode }
         A_MRET,A_HRET,A_SRET,A_URET,
         A_WFI,

compiler/riscv/itcpugas.pas

@@ -163,6 +163,9 @@ unit itcpugas;
         'flq','fsq',
         'fmax.q','fmax.q',
 
+        { Zihintpause }
+        'pause',
+
         { Machine mode }
         'mret','hret','sret','uret',
         'wfi',

compiler/riscv/nrvinl.pas

@@ -51,6 +51,10 @@ interface
 
         procedure second_fma; override;
         procedure second_minmax; override;
+
+        function pass_typecheck_cpu: tnode; override;
+        function first_cpu: tnode; override;
+        procedure pass_generate_code_cpu; override;
       protected
         procedure load_fpu_location;
       end;
@@ -74,6 +78,44 @@ implementation
                               trvinlinenode
 *****************************************************************************}
 
+     function trvinlinenode.pass_typecheck_cpu: tnode;
+       begin
+         Result:=nil;
+         case inlinenumber of
+           in_riscv_pause:
+             resultdef:=voidtype;
+           else
+             result:=inherited;
+         end;
+       end;
+
+
+    function trvinlinenode.first_cpu : tnode;
+      begin
+        Result:=nil;
+        case inlinenumber of
+          in_riscv_pause:
+            begin
+              expectloc:=LOC_VOID;
+              resultdef:=voidtype;
+            end;
+          else
+            Result:=inherited first_cpu;
+        end;
+      end;
+
+
+     procedure trvinlinenode.pass_generate_code_cpu;
+       begin
+         case inlinenumber of
+           in_riscv_pause:
+             current_asmdata.CurrAsmList.concat(taicpu.op_none(A_PAUSE));
+           else
+             inherited pass_generate_code_cpu;
+         end;
+       end;
+
+
      function trvinlinenode.first_sqrt_real : tnode;
        begin
          if (current_settings.fputype >= fpu_fd) then

rtl/linux/Makefile

@@ -971,10 +971,12 @@ endif
 ifeq ($(ARCH),riscv32)
 override LOADERS=
 SYSINIT_UNITS=si_prc si_dll si_c
+CPU_UNITS=$(INTRINSICSUNIT)
 endif
 ifeq ($(ARCH),riscv64)
 override LOADERS=
 SYSINIT_UNITS=si_prc si_dll si_c si_g
+CPU_UNITS=$(INTRINSICSUNIT)
 endif
 ifeq ($(ARCH),mips64)
 override LOADERS=

rtl/linux/Makefile.fpc

@@ -78,7 +78,7 @@ endif
 endif
 # syscall unit compiled with -dFPC_USE_LIBC
 # required mode objfpc which adds a dependency to
-# objpas unit 
+# objpas unit
 ifneq ($(filter -dFPC_USE_LIBC,$(OPT) $(CROSSOPT)),)
   SYSCALL_DEPS_OS+=$(OBJPASUNIT)$(PPUEXT)
 endif
@@ -120,11 +120,13 @@ endif
 ifeq ($(ARCH),riscv32)
 override LOADERS=
 SYSINIT_UNITS=si_prc si_dll si_c
+CPU_UNITS=$(INTRINSICSUNIT)
 endif
 
 ifeq ($(ARCH),riscv64)
 override LOADERS=
 SYSINIT_UNITS=si_prc si_dll si_c si_g
+CPU_UNITS=$(INTRINSICSUNIT)
 endif
 
 ifeq ($(ARCH),mips64)

rtl/riscv/cpuinnr.inc

@@ -0,0 +1,16 @@
+  {
+    Defines CPU intrinsic indicies for RiscV
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2021 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+fpc_in_riscv_pause = fpc_in_cpu_first+0;

rtl/riscv/cpuprocs.inc

@@ -0,0 +1,16 @@
+{
+    Defines CPU intrinsics for RiscV
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2025 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+procedure fpc_riscv_pause;[internproc:fpc_in_riscv_pause];

rtl/riscv/intrinsics.inc

@@ -0,0 +1,28 @@
+{
+    Provides CPU intrinsics for RiscV
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2021 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+{$IFNDEF FPC_DOTTEDUNITS}
+unit intrinsics;
+{$ENDIF FPC_DOTTEDUNITS}
+
+  interface
+
+    const
+    {$i cpuinnr.inc}
+
+    {$i cpuprocs.inc}
+
+  implementation
+
+end.

rtl/riscv32/intrinsics.pp

@@ -0,0 +1,16 @@
+{
+    Provides CPU intrinsics for RiscV 32
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2025 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+{$I ../ricsv/intrinsics.inc}

rtl/riscv64/intrinsics.pp

@@ -0,0 +1,16 @@
+{
+    Provides CPU intrinsics for RiscV 64
+
+    This file is part of the Free Pascal run time library.
+    Copyright (c) 2025 by the Free Pascal development team.
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+{$I ../riscv/intrinsics.inc}