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@@ -140,6 +140,7 @@ unit aoptx86;
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function OptPass1VPXor(var p: tai): boolean;
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function OptPass1Imul(var p : tai) : boolean;
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+ function OptPass2Movx(var p : tai): Boolean;
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function OptPass2MOV(var p : tai) : boolean;
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function OptPass2Imul(var p : tai) : boolean;
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function OptPass2Jmp(var p : tai) : boolean;
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@@ -149,8 +150,8 @@ unit aoptx86;
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function OptPass2ADD(var p : tai): Boolean;
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function PostPeepholeOptMov(var p : tai) : Boolean;
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-{$ifdef x86_64} { These post-peephole optimisations only affect 64-bit registers. [Kit] }
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function PostPeepholeOptMovzx(var p : tai) : Boolean;
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+{$ifdef x86_64} { These post-peephole optimisations only affect 64-bit registers. [Kit] }
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function PostPeepholeOptXor(var p : tai) : Boolean;
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{$endif}
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function PostPeepholeOptAnd(var p : tai) : boolean;
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@@ -160,6 +161,7 @@ unit aoptx86;
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function PostPeepholeOptCall(var p : tai) : Boolean;
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function PostPeepholeOptLea(var p : tai) : Boolean;
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function PostPeepholeOptPush(var p: tai): Boolean;
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+ function PostPeepholeOptShr(var p : tai) : boolean;
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procedure ConvertJumpToRET(const p: tai; const ret_p: tai);
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@@ -4935,6 +4937,529 @@ unit aoptx86;
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end;
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+ function TX86AsmOptimizer.OptPass2Movx(var p : tai) : boolean;
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+ const
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+ LIST_STEP_SIZE = 4;
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+ var
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+ ThisReg: TRegister;
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+ MinSize, MaxSize, TrySmaller, TargetSize: TOpSize;
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+ TargetSubReg: TSubRegister;
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+ hp1, hp2: tai;
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+ RegInUse, p_removed: Boolean;
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+
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+ { Store list of found instructions so we don't have to call
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+ GetNextInstructionUsingReg multiple times }
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+ InstrList: array of taicpu;
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+ InstrMax, Index: Integer;
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+ UpperLimit, TrySmallerLimit: TCgInt;
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+
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+ { Data flow analysis }
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+ TestValMin, TestValMax: TCgInt;
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+ SmallerOverflow: Boolean;
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+
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+ begin
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+ Result := False;
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+ p_removed := False;
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+
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+ { This is anything but quick! }
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+ if not(cs_opt_level2 in current_settings.optimizerswitches) then
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+ Exit;
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+
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+ SetLength(InstrList, 0);
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+ InstrMax := -1;
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+ ThisReg := taicpu(p).oper[1]^.reg;
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+ hp1 := p;
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+
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+ case taicpu(p).opsize of
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+ S_BW, S_BL:
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+ begin
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+ UpperLimit := $FF;
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+ MinSize := S_B;
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+ if taicpu(p).opsize = S_BW then
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+ MaxSize := S_W
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+ else
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+ MaxSize := S_L;
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+ end;
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+ S_WL:
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+ begin
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+ UpperLimit := $FFFF;
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+ MinSize := S_W;
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+ MaxSize := S_L;
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+ end
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+ else
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+ InternalError(2020112301);
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+ end;
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+
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+ TestValMin := 0;
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+ TestValMax := UpperLimit;
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+ TrySmallerLimit := UpperLimit;
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+ TrySmaller := S_NO;
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+ SmallerOverflow := False;
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+
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+ while GetNextInstructionUsingReg(hp1, hp1, ThisReg) and
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+ (hp1.typ = ait_instruction) and
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+ (
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+ { Under -O1 and -O2, GetNextInstructionUsingReg may return an
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+ instruction that doesn't actually contain ThisReg }
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+ (cs_opt_level3 in current_settings.optimizerswitches) or
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+ RegInInstruction(ThisReg, hp1)
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+ ) do
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+ begin
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+ case taicpu(hp1).opcode of
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+ A_INC,A_DEC:
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+ begin
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+ { Has to be an exact match on the register }
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+ if not MatchOperand(taicpu(hp1).oper[0]^, ThisReg) then
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+ Break;
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+
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+ if taicpu(hp1).opcode = A_INC then
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+ begin
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+ Inc(TestValMin);
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+ Inc(TestValMax);
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+ end
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+ else
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+ begin
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+ Dec(TestValMin);
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+ Dec(TestValMax);
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+ end;
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+ end;
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+
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+ { OR and XOR are not included because they can too easily fool
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+ the data flow analysis (they can cause non-linear behaviour) }
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+ A_ADD,A_SUB,A_AND,A_SHL,A_SHR:
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+ begin
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+ if
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+ (taicpu(hp1).oper[1]^.typ <> top_reg) or
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+ { Has to be an exact match on the register }
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+ (taicpu(hp1).oper[1]^.reg <> ThisReg) or not
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+ (
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+ (
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+ (taicpu(hp1).oper[0]^.typ = top_const) and
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+ (
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+ (
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+ (taicpu(hp1).opcode = A_SHL) and
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+ (
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+ ((MinSize = S_B) and (taicpu(hp1).oper[0]^.val < 8)) or
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+ ((MinSize = S_W) and (taicpu(hp1).oper[0]^.val < 16)) or
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+ ((MinSize = S_L) and (taicpu(hp1).oper[0]^.val < 32))
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+ )
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+ ) or (
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+ (taicpu(hp1).opcode <> A_SHL) and
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+ (
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+ ((taicpu(hp1).oper[0]^.val and UpperLimit) = taicpu(hp1).oper[0]^.val) or
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+ { Is it in the negative range? }
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+ (((not taicpu(hp1).oper[0]^.val) and (UpperLimit shr 1)) = (not taicpu(hp1).oper[0]^.val))
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+ )
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+ )
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+ )
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+ ) or (
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+ MatchOperand(taicpu(hp1).oper[0]^, taicpu(hp1).oper[1]^.reg) and
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+ ((taicpu(hp1).opcode = A_ADD) or (taicpu(hp1).opcode = A_AND) or (taicpu(hp1).opcode = A_SUB))
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+ )
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+ ) then
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+ Break;
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+
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+ case taicpu(hp1).opcode of
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+ A_ADD:
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+ if (taicpu(hp1).oper[0]^.typ = top_reg) then
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+ begin
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+ TestValMin := TestValMin * 2;
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+ TestValMax := TestValMax * 2;
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+ end
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+ else
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+ begin
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+ TestValMin := TestValMin + taicpu(hp1).oper[0]^.val;
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+ TestValMax := TestValMax + taicpu(hp1).oper[0]^.val;
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+ end;
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+ A_SUB:
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+ if (taicpu(hp1).oper[0]^.typ = top_reg) then
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+ begin
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+ TestValMin := 0;
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+ TestValMax := 0;
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+ end
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+ else
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+ begin
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+ TestValMin := TestValMin - taicpu(hp1).oper[0]^.val;
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+ TestValMax := TestValMax - taicpu(hp1).oper[0]^.val;
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+ end;
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+ A_AND:
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+ if (taicpu(hp1).oper[0]^.typ = top_const) then
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+ begin
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+ { we might be able to go smaller if AND appears first }
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+ if InstrMax = -1 then
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+ case MinSize of
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+ S_B:
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+ ;
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+ S_W:
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+ if ((taicpu(hp1).oper[0]^.val and $FF) = taicpu(hp1).oper[0]^.val) or
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+ ((not(taicpu(hp1).oper[0]^.val) and $7F) = (not taicpu(hp1).oper[0]^.val)) then
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+ begin
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+ TrySmaller := S_B;
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+ TrySmallerLimit := $FF;
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+ end;
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+ S_L:
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+ if ((taicpu(hp1).oper[0]^.val and $FF) = taicpu(hp1).oper[0]^.val) or
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+ ((not(taicpu(hp1).oper[0]^.val) and $7F) = (not taicpu(hp1).oper[0]^.val)) then
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+ begin
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+ TrySmaller := S_B;
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+ TrySmallerLimit := $FF;
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+ end
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+ else if ((taicpu(hp1).oper[0]^.val and $FFFF) = taicpu(hp1).oper[0]^.val) or
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+ ((not(taicpu(hp1).oper[0]^.val) and $7FFF) = (not taicpu(hp1).oper[0]^.val)) then
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+ begin
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+ TrySmaller := S_W;
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+ TrySmallerLimit := $FFFF;
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+ end;
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+ else
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+ InternalError(2020112320);
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+ end;
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+
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+ TestValMin := TestValMin and taicpu(hp1).oper[0]^.val;
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+ TestValMax := TestValMax and taicpu(hp1).oper[0]^.val;
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+ end;
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+ A_SHL:
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+ begin
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+ TestValMin := TestValMin shl taicpu(hp1).oper[0]^.val;
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+ TestValMax := TestValMax shl taicpu(hp1).oper[0]^.val;
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+ end;
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+ A_SHR:
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+ begin
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+ { we might be able to go smaller if SHR appears first }
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+ if InstrMax = -1 then
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+ case MinSize of
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+ S_B:
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+ ;
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+ S_W:
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+ if (taicpu(hp1).oper[0]^.val >= 8) then
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+ begin
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+ TrySmaller := S_B;
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+ TrySmallerLimit := $FF;
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+ end;
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+ S_L:
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+ if (taicpu(hp1).oper[0]^.val >= 24) then
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+ begin
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+ TrySmaller := S_B;
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+ TrySmallerLimit := $FF;
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+ end
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+ else if (taicpu(hp1).oper[0]^.val >= 16) then
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+ begin
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+ TrySmaller := S_W;
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+ TrySmallerLimit := $FFFF;
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+ end;
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+ else
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+ InternalError(2020112321);
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+ end;
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+
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+ TestValMin := TestValMin shr taicpu(hp1).oper[0]^.val;
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+ TestValMax := TestValMax shr taicpu(hp1).oper[0]^.val;
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+ end;
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+ else
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+ InternalError(2020112303);
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+ end;
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+ end;
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+(*
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+ A_IMUL:
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+ case taicpu(hp1).ops of
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+ 2:
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+ begin
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+ if not MatchOpType(hp1, top_reg, top_reg) or
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+ { Has to be an exact match on the register }
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+ (taicpu(hp1).oper[0]^.reg <> ThisReg) or
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+ (taicpu(hp1).oper[1]^.reg <> ThisReg) then
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+ Break;
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+
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+ TestValMin := TestValMin * TestValMin;
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+ TestValMax := TestValMax * TestValMax;
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+ end;
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+ 3:
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+ begin
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+ if not MatchOpType(hp1, top_const, top_reg, top_reg) or
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+ { Has to be an exact match on the register }
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+ (taicpu(hp1).oper[1]^.reg <> ThisReg) or
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+ (taicpu(hp1).oper[2]^.reg <> ThisReg) or
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+ ((taicpu(hp1).oper[0]^.val and UpperLimit) = taicpu(hp1).oper[0]^.val) or
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+ { Is it in the negative range? }
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+ (((not taicpu(hp1).oper[0]^.val) and (UpperLimit shr 1)) = (not taicpu(hp1).oper[0]^.val)) then
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+ Break;
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+
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+ TestValMin := TestValMin * taicpu(hp1).oper[0]^.val;
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+ TestValMax := TestValMax * taicpu(hp1).oper[0]^.val;
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+ end;
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+ else
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+ Break;
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+ end;
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+
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+ A_IDIV:
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+ case taicpu(hp1).ops of
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+ 3:
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+ begin
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+ if not MatchOpType(hp1, top_const, top_reg, top_reg) or
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+ { Has to be an exact match on the register }
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+ (taicpu(hp1).oper[1]^.reg <> ThisReg) or
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+ (taicpu(hp1).oper[2]^.reg <> ThisReg) or
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+ ((taicpu(hp1).oper[0]^.val and UpperLimit) = taicpu(hp1).oper[0]^.val) or
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+ { Is it in the negative range? }
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+ (((not taicpu(hp1).oper[0]^.val) and (UpperLimit shr 1)) = (not taicpu(hp1).oper[0]^.val)) then
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+ Break;
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+
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+ TestValMin := TestValMin div taicpu(hp1).oper[0]^.val;
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+ TestValMax := TestValMax div taicpu(hp1).oper[0]^.val;
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+ end;
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+ else
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+ Break;
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+ end;
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+*)
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+ A_MOVZX:
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+ begin
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+ if not MatchOpType(taicpu(hp1), top_reg, top_reg) then
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+ Break;
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+
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+ { The objective here is to try to find a combination that
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+ removes one of the MOV/Z instructions. }
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+ case taicpu(hp1).opsize of
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+ S_WL:
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+ if (MinSize in [S_B, S_W]) then
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+ begin
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+ TargetSize := S_L;
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+ TargetSubReg := R_SUBD;
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+ end
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+ else if ((TrySmaller in [S_B, S_W]) and not SmallerOverflow) then
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+ begin
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+ TargetSize := TrySmaller;
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+ if TrySmaller = S_B then
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+ TargetSubReg := R_SUBL
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+ else
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+ TargetSubReg := R_SUBW;
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+ end
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+ else
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+ Break;
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+
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+ S_BW:
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+ if (MinSize in [S_B, S_W]) then
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+ begin
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+ TargetSize := S_W;
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+ TargetSubReg := R_SUBW;
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+ end
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+ else if ((TrySmaller = S_B) and not SmallerOverflow) then
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+ begin
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+ TargetSize := S_B;
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+ TargetSubReg := R_SUBL;
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+ end
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+ else
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+ Break;
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+
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+ S_BL:
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+ if (MinSize in [S_B, S_W]) then
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+ begin
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+ TargetSize := S_L;
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+ TargetSubReg := R_SUBD;
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+ end
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+ else if ((TrySmaller = S_B) and not SmallerOverflow) then
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+ begin
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+ TargetSize := S_B;
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+ TargetSubReg := R_SUBL;
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+ end
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+ else
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+ Break;
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+
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+ else
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+ InternalError(2020112302);
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+ end;
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+
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+ { Update the register to its new size }
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+ ThisReg := newreg(R_INTREGISTER, getsupreg(ThisReg), TargetSubReg);
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+
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+ if TargetSize = MinSize then
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+ begin
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+ { Convert the input MOVZX to a MOV }
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+ if (taicpu(p).oper[0]^.typ = top_reg) and
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+ SuperRegistersEqual(taicpu(p).oper[0]^.reg, ThisReg) then
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+ begin
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+ { Or remove it completely! }
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+ DebugMsg(SPeepholeOptimization + 'Movzx2Nop 1', p);
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+ RemoveCurrentP(p);
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+ p_removed := True;
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+ end
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+ else
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'Movzx2Mov 1', p);
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+ taicpu(p).opcode := A_MOV;
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+ taicpu(p).oper[1]^.reg := ThisReg;
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+ taicpu(p).opsize := TargetSize;
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+ end;
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+
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+ Result := True;
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+ end
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+ else if TargetSize <> MaxSize then
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+ begin
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+
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+ case MaxSize of
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+ S_L:
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+ if TargetSize = S_W then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'movzbl2movzbw', p);
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+ taicpu(p).opsize := S_BW;
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+ taicpu(p).oper[1]^.reg := ThisReg;
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+ Result := True;
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+ end
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+ else
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+ InternalError(2020112341);
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+
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+ S_W:
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+ if TargetSize = S_L then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'movzbw2movzbl', p);
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|
|
+ taicpu(p).opsize := S_BL;
|
|
|
+ taicpu(p).oper[1]^.reg := ThisReg;
|
|
|
+ Result := True;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ InternalError(2020112342);
|
|
|
+ else
|
|
|
+ ;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+
|
|
|
+ if (MaxSize = TargetSize) or
|
|
|
+ ((TargetSize = S_L) and (taicpu(hp1).opsize in [S_L, S_BL, S_WL])) or
|
|
|
+ ((TargetSize = S_W) and (taicpu(hp1).opsize in [S_W, S_BW])) then
|
|
|
+ begin
|
|
|
+ { Convert the output MOVZX to a MOV }
|
|
|
+ if (taicpu(hp1).oper[0]^.typ = top_reg) and
|
|
|
+ SuperRegistersEqual(taicpu(hp1).oper[1]^.reg, ThisReg) then
|
|
|
+ begin
|
|
|
+ { Or remove it completely! }
|
|
|
+ DebugMsg(SPeepholeOptimization + 'Movzx2Nop 2', hp1);
|
|
|
+
|
|
|
+ { Be careful; if p = hp1 and p was also removed, p
|
|
|
+ will become a dangling pointer }
|
|
|
+ if p = hp1 then
|
|
|
+ RemoveCurrentp(p) { p = hp1 and will then become the next instruction }
|
|
|
+ else
|
|
|
+ RemoveInstruction(hp1);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ taicpu(hp1).opcode := A_MOV;
|
|
|
+ taicpu(hp1).oper[0]^.reg := ThisReg;
|
|
|
+ taicpu(hp1).opsize := TargetSize;
|
|
|
+
|
|
|
+ { Check to see if the active register is used afterwards;
|
|
|
+ if not, we can change it and make a saving. }
|
|
|
+ RegInUse := False;
|
|
|
+ TransferUsedRegs(TmpUsedRegs);
|
|
|
+
|
|
|
+ { The target register may be marked as in use to cross
|
|
|
+ a jump to a distant label, so exclude it }
|
|
|
+ ExcludeRegFromUsedRegs(taicpu(hp1).oper[1]^.reg, TmpUsedRegs);
|
|
|
+
|
|
|
+ hp2 := p;
|
|
|
+ repeat
|
|
|
+
|
|
|
+ UpdateUsedRegs(TmpUsedRegs, tai(hp2.next));
|
|
|
+
|
|
|
+ { Explicitly check for the excluded register (don't include the first
|
|
|
+ instruction as it may be reading from here }
|
|
|
+ if ((p <> hp2) and (RegInInstruction(taicpu(hp1).oper[1]^.reg, hp2))) or
|
|
|
+ RegInUsedRegs(taicpu(hp1).oper[1]^.reg, TmpUsedRegs) then
|
|
|
+ begin
|
|
|
+ RegInUse := True;
|
|
|
+ Break;
|
|
|
+ end;
|
|
|
+
|
|
|
+ if not GetNextInstruction(hp2, hp2) then
|
|
|
+ InternalError(2020112340);
|
|
|
+
|
|
|
+ until (hp2 = hp1);
|
|
|
+
|
|
|
+ if not RegInUse and not RegUsedAfterInstruction(ThisReg, hp1, TmpUsedRegs) then
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'Simplified register usage so ' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' = ' + debug_regname(taicpu(p).oper[1]^.reg), p);
|
|
|
+ ThisReg := taicpu(hp1).oper[1]^.reg;
|
|
|
+
|
|
|
+ TransferUsedRegs(TmpUsedRegs);
|
|
|
+ AllocRegBetween(ThisReg, p, hp1, TmpUsedRegs);
|
|
|
+
|
|
|
+ DebugMsg(SPeepholeOptimization + 'Movzx2Nop 3', hp1);
|
|
|
+ if p = hp1 then
|
|
|
+ RemoveCurrentp(p) { p = hp1 and will then become the next instruction }
|
|
|
+ else
|
|
|
+ RemoveInstruction(hp1);
|
|
|
+
|
|
|
+ { Instruction will become "mov %reg,%reg" }
|
|
|
+ if not p_removed and (taicpu(p).opcode = A_MOV) and
|
|
|
+ MatchOperand(taicpu(p).oper[0]^, ThisReg) then
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'Movzx2Nop 6', p);
|
|
|
+ RemoveCurrentP(p);
|
|
|
+ p_removed := True;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ taicpu(p).oper[1]^.reg := ThisReg;
|
|
|
+
|
|
|
+ Result := True;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ DebugMsg(SPeepholeOptimization + 'Movzx2Mov 2', hp1);
|
|
|
+
|
|
|
+ end;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ InternalError(2020112330);
|
|
|
+
|
|
|
+ { Now go through every instruction we found and change the
|
|
|
+ size. If TargetSize = MaxSize, then almost no changes are
|
|
|
+ needed and Result can remain False if it hasn't been set
|
|
|
+ yet. }
|
|
|
+
|
|
|
+ if (TargetSize <> MaxSize) and (InstrMax >= 0) then
|
|
|
+ begin
|
|
|
+ for Index := 0 to InstrMax do
|
|
|
+ begin
|
|
|
+
|
|
|
+ { If p_removed is true, then the original MOV/Z was removed
|
|
|
+ and removing the AND instruction may not be safe if it
|
|
|
+ appears first }
|
|
|
+ if (InstrList[Index].oper[InstrList[Index].ops - 1]^.typ <> top_reg) then
|
|
|
+ InternalError(2020112310);
|
|
|
+
|
|
|
+ if InstrList[Index].oper[0]^.typ = top_reg then
|
|
|
+ InstrList[Index].oper[0]^.reg := ThisReg;
|
|
|
+
|
|
|
+ InstrList[Index].oper[InstrList[Index].ops - 1]^.reg := ThisReg;
|
|
|
+ InstrList[Index].opsize := TargetSize;
|
|
|
+ end;
|
|
|
+
|
|
|
+ Result := True;
|
|
|
+ end;
|
|
|
+
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+
|
|
|
+ else
|
|
|
+ { This includes ADC, SBB, IDIV and SAR }
|
|
|
+ Break;
|
|
|
+ end;
|
|
|
+
|
|
|
+ if (TestValMin < 0) or (TestValMax < 0) or
|
|
|
+ (TestValMin > UpperLimit) or (TestValMax > UpperLimit) then
|
|
|
+ { Overflow }
|
|
|
+ Break
|
|
|
+ else if not SmallerOverflow and (TrySmaller <> S_NO) and
|
|
|
+ ((TestValMin > TrySmallerLimit) or (TestValMax > TrySmallerLimit)) then
|
|
|
+ SmallerOverflow := True;
|
|
|
+
|
|
|
+ { Contains highest index (so instruction count - 1) }
|
|
|
+ Inc(InstrMax);
|
|
|
+ if InstrMax > High(InstrList) then
|
|
|
+ SetLength(InstrList, InstrMax + LIST_STEP_SIZE);
|
|
|
+
|
|
|
+ InstrList[InstrMax] := taicpu(hp1);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+
|
|
|
function TX86AsmOptimizer.OptPass2Imul(var p : tai) : boolean;
|
|
|
var
|
|
|
hp1 : tai;
|
|
|
@@ -6691,6 +7216,41 @@ unit aoptx86;
|
|
|
end;
|
|
|
|
|
|
|
|
|
+ function TX86AsmOptimizer.PostPeepholeOptShr(var p : tai) : boolean;
|
|
|
+ var
|
|
|
+ hp1: tai;
|
|
|
+ begin
|
|
|
+ { Detect:
|
|
|
+ shr x, %ax (x > 0)
|
|
|
+ ...
|
|
|
+ movzwl %ax,%eax
|
|
|
+
|
|
|
+ Change movzwl %ax,%eax to cwtl (shorter encoding for movswl %ax,%eax)
|
|
|
+ }
|
|
|
+
|
|
|
+ Result := False;
|
|
|
+ if MatchOpType(taicpu(p), top_const, top_reg) and
|
|
|
+ (taicpu(p).oper[1]^.reg = NR_AX) and { This is also enough to determine that opsize = S_W }
|
|
|
+ (taicpu(p).oper[0]^.val > 0) and
|
|
|
+ GetNextInstructionUsingReg(p, hp1, NR_EAX) and
|
|
|
+ MatchInstruction(hp1, A_MOVZX, [S_WL]) and
|
|
|
+ MatchOperand(taicpu(hp1).oper[0]^, NR_AX) and
|
|
|
+ MatchOperand(taicpu(hp1).oper[1]^, NR_EAX) then
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'Converted movzwl %ax,%eax to cwtl (via ShrMovz2ShrCwtl)', hp1);
|
|
|
+ taicpu(hp1).opcode := A_CWDE;
|
|
|
+ taicpu(hp1).clearop(0);
|
|
|
+ taicpu(hp1).clearop(1);
|
|
|
+ taicpu(hp1).ops := 0;
|
|
|
+
|
|
|
+ { A change was made, but not with p, so move forward 1 }
|
|
|
+ p := tai(p.Next);
|
|
|
+ Result := True;
|
|
|
+ end;
|
|
|
+
|
|
|
+ end;
|
|
|
+
|
|
|
+
|
|
|
function TX86AsmOptimizer.PostPeepholeOptCmp(var p : tai) : Boolean;
|
|
|
begin
|
|
|
Result:=false;
|
|
|
@@ -6864,12 +7424,150 @@ unit aoptx86;
|
|
|
end;
|
|
|
|
|
|
|
|
|
-{$ifdef x86_64}
|
|
|
function TX86AsmOptimizer.PostPeepholeOptMovzx(var p : tai) : Boolean;
|
|
|
+
|
|
|
+ function ConstInRange(const Val: TCGInt; const OpSize: TOpSize): Boolean;
|
|
|
+ begin
|
|
|
+ case OpSize of
|
|
|
+ S_B, S_BW, S_BL{$ifdef x86_64}, S_BQ{$endif x86_64}:
|
|
|
+ Result := (Val <= $FF) and (Val >= -128);
|
|
|
+ S_W, S_WL{$ifdef x86_64}, S_WQ{$endif x86_64}:
|
|
|
+ Result := (Val <= $FFFF) and (Val >= -32768);
|
|
|
+ S_L{$ifdef x86_64}, S_LQ{$endif x86_64}:
|
|
|
+ Result := (Val <= $FFFFFFFF) and (Val >= -2147483648);
|
|
|
+ else
|
|
|
+ Result := True;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
var
|
|
|
+ hp1, hp2 : tai;
|
|
|
+ SizeChange: Boolean;
|
|
|
PreMessage: string;
|
|
|
begin
|
|
|
Result := False;
|
|
|
+
|
|
|
+ if (taicpu(p).oper[0]^.typ = top_reg) and
|
|
|
+ SuperRegistersEqual(taicpu(p).oper[0]^.reg, taicpu(p).oper[1]^.reg) and
|
|
|
+ GetNextInstruction(p, hp1) and (hp1.typ = ait_instruction) then
|
|
|
+ begin
|
|
|
+ { Change (using movzbl %al,%eax as an example):
|
|
|
+
|
|
|
+ movzbl %al, %eax movzbl %al, %eax
|
|
|
+ cmpl x, %eax testl %eax,%eax
|
|
|
+
|
|
|
+ To:
|
|
|
+ cmpb x, %al testb %al, %al (Move one back to avoid a false dependency)
|
|
|
+ movzbl %al, %eax movzbl %al, %eax
|
|
|
+
|
|
|
+ Smaller instruction and minimises pipeline stall as the CPU
|
|
|
+ doesn't have to wait for the register to get zero-extended. [Kit]
|
|
|
+
|
|
|
+ Also allow if the smaller of the two registers is being checked,
|
|
|
+ as this still removes the false dependency.
|
|
|
+ }
|
|
|
+ if
|
|
|
+ (
|
|
|
+ (
|
|
|
+ (taicpu(hp1).opcode = A_CMP) and MatchOpType(taicpu(hp1), top_const, top_reg) and
|
|
|
+ ConstInRange(taicpu(hp1).oper[0]^.val, taicpu(p).opsize)
|
|
|
+ ) or (
|
|
|
+ { If MatchOperand returns True, they must both be registers }
|
|
|
+ (taicpu(hp1).opcode = A_TEST) and MatchOperand(taicpu(hp1).oper[0]^, taicpu(hp1).oper[1]^)
|
|
|
+ )
|
|
|
+ ) and
|
|
|
+ (reg2opsize(taicpu(hp1).oper[1]^.reg) <= reg2opsize(taicpu(p).oper[1]^.reg)) then
|
|
|
+ begin
|
|
|
+ PreMessage := debug_op2str(taicpu(hp1).opcode) + debug_opsize2str(taicpu(hp1).opsize) + ' ' + debug_operstr(taicpu(hp1).oper[0]^) + ',' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' -> ' + debug_op2str(taicpu(hp1).opcode);
|
|
|
+
|
|
|
+ asml.Remove(hp1);
|
|
|
+ asml.InsertBefore(hp1, p);
|
|
|
+
|
|
|
+ { Swap instructions in the case of cmp 0,%reg or test %reg,%reg }
|
|
|
+ if (taicpu(hp1).opcode = A_TEST) or (taicpu(hp1).oper[0]^.val = 0) then
|
|
|
+ begin
|
|
|
+ taicpu(hp1).opcode := A_TEST;
|
|
|
+ taicpu(hp1).loadreg(0, taicpu(p).oper[0]^.reg);
|
|
|
+ end;
|
|
|
+
|
|
|
+ taicpu(hp1).oper[1]^.reg := taicpu(p).oper[0]^.reg;
|
|
|
+
|
|
|
+ case taicpu(p).opsize of
|
|
|
+ S_BW, S_BL:
|
|
|
+ begin
|
|
|
+ SizeChange := taicpu(hp1).opsize <> S_B;
|
|
|
+ taicpu(hp1).changeopsize(S_B);
|
|
|
+ end;
|
|
|
+ S_WL:
|
|
|
+ begin
|
|
|
+ SizeChange := taicpu(hp1).opsize <> S_W;
|
|
|
+ taicpu(hp1).changeopsize(S_W);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ InternalError(2020112701);
|
|
|
+ end;
|
|
|
+
|
|
|
+ UpdateUsedRegs(tai(p.Next));
|
|
|
+
|
|
|
+ { Check if the register is used aferwards - if not, we can
|
|
|
+ remove the movzx instruction completely }
|
|
|
+ if not RegUsedAfterInstruction(taicpu(hp1).oper[1]^.reg, p, UsedRegs) then
|
|
|
+ begin
|
|
|
+ { Hp1 is a better position than p for debugging purposes }
|
|
|
+ DebugMsg(SPeepholeOptimization + 'Movzx2Nop 4a', hp1);
|
|
|
+ RemoveCurrentp(p, hp1);
|
|
|
+ Result := True;
|
|
|
+ end;
|
|
|
+
|
|
|
+ if SizeChange then
|
|
|
+ DebugMsg(SPeepholeOptimization + PreMessage +
|
|
|
+ debug_opsize2str(taicpu(hp1).opsize) + ' ' + debug_operstr(taicpu(hp1).oper[0]^) + ',' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' (smaller and minimises pipeline stall - MovzxCmp2CmpMovzx)', hp1)
|
|
|
+ else
|
|
|
+ DebugMsg(SPeepholeOptimization + 'MovzxCmp2CmpMovzx', hp1);
|
|
|
+
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+
|
|
|
+ { Change (using movzwl %ax,%eax as an example):
|
|
|
+
|
|
|
+ movzwl %ax, %eax
|
|
|
+ movb %al, (dest) (Register is smaller than read register in movz)
|
|
|
+
|
|
|
+ To:
|
|
|
+ movb %al, (dest) (Move one back to avoid a false dependency)
|
|
|
+ movzwl %ax, %eax
|
|
|
+ }
|
|
|
+ if (taicpu(hp1).opcode = A_MOV) and
|
|
|
+ (taicpu(hp1).oper[0]^.typ = top_reg) and
|
|
|
+ not RegInOp(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^) and
|
|
|
+ SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(p).oper[0]^.reg) and
|
|
|
+ (reg2opsize(taicpu(hp1).oper[0]^.reg) <= reg2opsize(taicpu(p).oper[0]^.reg)) then
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'MovzxMov2MovMovzx', hp1);
|
|
|
+
|
|
|
+ hp2 := tai(hp1.Previous); { Effectively the old position of hp1 }
|
|
|
+ asml.Remove(hp1);
|
|
|
+ asml.InsertBefore(hp1, p);
|
|
|
+ if taicpu(hp1).oper[1]^.typ = top_reg then
|
|
|
+ AllocRegBetween(taicpu(hp1).oper[1]^.reg, hp1, hp2, UsedRegs);
|
|
|
+
|
|
|
+ { Check if the register is used aferwards - if not, we can
|
|
|
+ remove the movzx instruction completely }
|
|
|
+
|
|
|
+ if not RegUsedAfterInstruction(taicpu(hp1).oper[0]^.reg, p, UsedRegs) then
|
|
|
+ begin
|
|
|
+ { Hp1 is a better position than p for debugging purposes }
|
|
|
+ DebugMsg(SPeepholeOptimization + 'Movzx2Nop 4b', hp1);
|
|
|
+ RemoveCurrentp(p, hp1);
|
|
|
+ Result := True;
|
|
|
+ end;
|
|
|
+
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+
|
|
|
+ end;
|
|
|
+
|
|
|
+{$ifdef x86_64}
|
|
|
{ Code size reduction by J. Gareth "Kit" Moreton }
|
|
|
{ Convert MOVZBQ and MOVZWQ to MOVZBL and MOVZWL respectively if it removes the REX prefix }
|
|
|
if (taicpu(p).opsize in [S_BQ, S_WQ]) and
|
|
|
@@ -6889,9 +7587,11 @@ unit aoptx86;
|
|
|
DebugMsg(SPeepholeOptimization + PreMessage +
|
|
|
debug_opsize2str(taicpu(p).opsize) + ' ' + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg) + ' (removes REX prefix)', p);
|
|
|
end;
|
|
|
+{$endif}
|
|
|
end;
|
|
|
|
|
|
|
|
|
+{$ifdef x86_64}
|
|
|
function TX86AsmOptimizer.PostPeepholeOptXor(var p : tai) : Boolean;
|
|
|
var
|
|
|
PreMessage, RegName: string;
|
nickysn