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@@ -191,7 +191,7 @@ unit at91sam7x256;
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{ Wait the startup time (until PMC Status register MOSCEN bit is set)
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result: $FFFFFC68 bit 0 will set when main oscillator has stabilized}
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- while (AT91C_PMC_SR and AT91C_PMC_MOSCS)=0 do
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+ while (AT91C_PMC_SR and AT91C_PMC_MOSCS)=0 do
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;
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@@ -310,7 +310,7 @@ unit at91sam7x256;
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ldr r0,.L_stack_top
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(*
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- Setting up SP for IRQ and FIQ mode.
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+ Setting up SP for the different CPU modes.
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Change mode before setting each one
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move back again to Supervisor mode
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Each interrupt has its own link
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@@ -319,18 +319,28 @@ unit at91sam7x256;
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initialized for interrupts to be
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used later.
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*)
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+ msr cpsr_c, #0xdb // switch to Undefined Instruction Mode
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+ mov sp, r0
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+ sub r0, r0, #0x10
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- (*
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- setup irq and fiq stacks each 128 bytes
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- *)
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- msr cpsr_c, #0x12 // switch to irq mode
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- mov sp, r0 // set irq stack pointer
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- sub r0,r0,#128 // irq stack size
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- msr cpsr_c, #0x11 // fiq mode
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- mov sp, r0 // set fiq stack pointer
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- sub r0,r0,#128 // fiq stack size
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- msr cpsr_c, #0x13 // supervisor mode F,I enabled
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- mov sp, r0 // stack
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+ msr cpsr_c, #0xd7 // switch to Abort Mode
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+ mov sp, r0
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+ sub r0, r0, #0x10
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+
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+ msr CPSR_c, #0xd1 // switch to FIQ Mode
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+ mov sp, r0
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+ sub r0, r0, #0x80
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+
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+ msr CPSR_c, #0xd2 // switch to IRQ Mode
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+ mov sp, r0
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+ sub r0, r0, #0x80
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+
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+ msr CPSR_c, #0xd3 // switch to Supervisor Mode
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+ mov sp, r0
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+ sub r0, r0, #0x80
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+
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+ msr CPSR_c, #0x1f // switch to System Mode, interrupts enabled
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+ mov sp, r0
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// for now, all handlers are set to a default one
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ldr r1,.LDefaultHandlerAddr
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florian