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@@ -1430,6 +1430,14 @@ implementation
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output.rex_present:=true;
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output.rex_present:=true;
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output.rex:=output.rex or $41;
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output.rex:=output.rex or $41;
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inc(output.size,1);
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inc(output.size,1);
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+ end
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+ else if (getregtype(input.reg)=R_INTREGISTER) and
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+ (getsubreg(input.reg)=R_SUBL) and
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+ (getsupreg(input.reg) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
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+ begin
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+ output.rex_present:=true;
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+ output.rex:=output.rex or $40;
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+ inc(output.size,1);
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end;
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end;
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process_ea:=true;
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process_ea:=true;
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@@ -1757,7 +1765,17 @@ implementation
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if rex=0 then
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if rex=0 then
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inc(len);
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inc(len);
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rex:=rex or $41;
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rex:=rex or $41;
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+ end
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+ else if (getregtype(oper[c-8]^.reg)=R_INTREGISTER) and
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+ (getsubreg(oper[c-8]^.reg)=R_SUBL) and
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+ (getsupreg(oper[c-8]^.reg) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
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+ begin
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+ if rex=0 then
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+ inc(len);
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+
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+ rex:=rex or $40;
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end;
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end;
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+
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{$endif x86_64}
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{$endif x86_64}
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inc(codes);
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inc(codes);
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inc(len);
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inc(len);
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@@ -1852,6 +1870,15 @@ implementation
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inc(len);
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inc(len);
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rex:=rex or $44;
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rex:=rex or $44;
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+ end
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+ else if (getregtype(oper[c and 7]^.reg)=R_INTREGISTER) and
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+ (getsubreg(oper[c and 7]^.reg)=R_SUBL) and
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+ (getsupreg(oper[c and 7]^.reg) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
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+ begin
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+ if rex=0 then
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+ inc(len);
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+
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+ rex:=rex or $40;
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end;
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end;
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end;
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end;
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end;
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end;
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