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* encode new 8 bit registers correctly

git-svn-id: trunk@3064 -
florian 19 years ago
parent
commit
7a34d58a15
1 changed files with 27 additions and 0 deletions
  1. 27 0
      compiler/x86/aasmcpu.pas

+ 27 - 0
compiler/x86/aasmcpu.pas

@@ -1430,6 +1430,14 @@ implementation
                 output.rex_present:=true;
                 output.rex_present:=true;
                 output.rex:=output.rex or $41;
                 output.rex:=output.rex or $41;
                 inc(output.size,1);
                 inc(output.size,1);
+              end
+            else if (getregtype(input.reg)=R_INTREGISTER) and
+              (getsubreg(input.reg)=R_SUBL) and
+              (getsupreg(input.reg) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
+              begin
+                output.rex_present:=true;
+                output.rex:=output.rex or $40;
+                inc(output.size,1);
               end;
               end;
 
 
             process_ea:=true;
             process_ea:=true;
@@ -1757,7 +1765,17 @@ implementation
                     if rex=0 then
                     if rex=0 then
                       inc(len);
                       inc(len);
                     rex:=rex or $41;
                     rex:=rex or $41;
+                  end
+                else if (getregtype(oper[c-8]^.reg)=R_INTREGISTER) and
+                  (getsubreg(oper[c-8]^.reg)=R_SUBL) and
+                  (getsupreg(oper[c-8]^.reg) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
+                  begin
+                    if rex=0 then
+                      inc(len);
+
+                    rex:=rex or $40;
                   end;
                   end;
+
 {$endif x86_64}
 {$endif x86_64}
                 inc(codes);
                 inc(codes);
                 inc(len);
                 inc(len);
@@ -1852,6 +1870,15 @@ implementation
                               inc(len);
                               inc(len);
 
 
                             rex:=rex or $44;
                             rex:=rex or $44;
+                          end
+                        else if (getregtype(oper[c and 7]^.reg)=R_INTREGISTER) and
+                          (getsubreg(oper[c and 7]^.reg)=R_SUBL) and
+                          (getsupreg(oper[c and 7]^.reg) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
+                          begin
+                            if rex=0 then
+                              inc(len);
+
+                            rex:=rex or $40;
                           end;
                           end;
                       end;
                       end;
                   end;
                   end;