* RiscV: factor out some common stuff into cpuinfo.inc

compiler/riscv/cpuinfo.inc

@@ -0,0 +1,70 @@
+{
+    Copyright (c) 1998-2002 by the Free Pascal development team
+
+    Basic Processor information common for all RiscV variants
+
+    See the file COPYING.FPC, included in this distribution,
+    for details about the copyright.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+
+ **********************************************************************}
+
+type
+  bestreal = double;
+  bestrealrec = TDoubleRec;
+  ts32real = single;
+  ts64real = double;
+  ts80real = extended;
+  ts128real = extended;
+  ts64comp = comp;
+
+  pbestreal = ^bestreal;
+
+  tcpuflags =
+     (CPURV_HAS_MUL,
+      CPURV_HAS_ATOMIC,
+      CPURV_HAS_COMPACT,
+      CPURV_HAS_16REGISTERS,
+      CPURV_HAS_ZBA,
+      CPURV_HAS_ZBB,
+      CPURV_HAS_ZBC,
+      CPURV_HAS_ZBS,
+      CPURV_HAS_ZBKB,
+      CPURV_HAS_ZBKC,
+      CPURV_HAS_ZBKX,
+      CPURV_HAS_CSR_INSTRUCTIONS,   { extension Zicsr    }
+      CPURV_HAS_FETCH_FENCE,        { extension Zifencei }
+      CPURV_HAS_ZIHINTPAUSE,
+      CPURV_HAS_F,
+      CPURV_HAS_D,
+      CPURV_HAS_Q,
+      CPURV_HAS_ZFH,
+      CPURV_HAS_ZFHMIN,
+      CPURV_HAS_ZFA,
+      CPURV_HAS_ZFINX,
+      CPURV_HAS_ZDINX,
+      CPURV_HAS_ZHINX,
+      CPURV_HAS_ZHINXMIN,
+      CPURV_HAS_ZICOND,
+      CPURV_HAS_ZMMUL
+     );
+
+  tfputype =
+    (fpu_none,
+    fpu_libgcc,
+    fpu_soft,
+    fpu_fd
+    );
+
+const
+  fputypestr: array[tfputype] of string[8] = (
+    'NONE',
+    'LIBGCC',
+    'SOFT',
+    'FD'
+    );
+
+

compiler/riscv32/cpuinfo.pas

@@ -21,17 +21,9 @@ Interface
   uses
     globtype;
 
-Type
-   bestreal = double;
-   bestrealrec = TDoubleRec;
-   ts32real = single;
-   ts64real = double;
-   ts80real = extended;
-   ts128real = extended;
-   ts64comp = comp;
-
-   pbestreal=^bestreal;
+{$I cpuinfo.inc}
 
+Type
    { possible supported processors for this target }
    tcputype =
       (cpu_none,
@@ -52,13 +44,6 @@ Type
        cpu_rv32gcb
       );
 
-   tfputype =
-     (fpu_none,  
-      fpu_libgcc,
-      fpu_soft,
-      fpu_fd
-     );
-
    tcontrollertype =
      (ct_none,
       ct_fe310g000,
@@ -191,13 +176,6 @@ Const
      'RV32GCB'
    );
 
-   fputypestr : array[tfputype] of string[8] = (         
-     'LIBGCC',
-     'NONE',
-     'SOFT',
-     'FD'
-   );
-
    { Supported optimizations, only used for information }
    supported_optimizerswitches = genericlevel1optimizerswitches+
                                  genericlevel2optimizerswitches+
@@ -213,36 +191,6 @@ Const
    level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches;
    level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_opt_stackframe]; 
 
- type
-   tcpuflags =
-      (CPURV_HAS_MUL,
-       CPURV_HAS_ATOMIC,
-       CPURV_HAS_COMPACT,
-       CPURV_HAS_16REGISTERS,
-       CPURV_HAS_ZBA,
-       CPURV_HAS_ZBB,
-       CPURV_HAS_ZBC,
-       CPURV_HAS_ZBS,
-       CPURV_HAS_ZBKB,
-       CPURV_HAS_ZBKC,
-       CPURV_HAS_ZBKX,
-       CPURV_HAS_CSR_INSTRUCTIONS,   { extension Zicsr    }
-       CPURV_HAS_FETCH_FENCE,        { extension Zifencei }
-       CPURV_HAS_ZIHINTPAUSE,
-       CPURV_HAS_F,
-       CPURV_HAS_D,
-       CPURV_HAS_Q,
-       CPURV_HAS_ZFH,
-       CPURV_HAS_ZFHMIN,
-       CPURV_HAS_ZFA,
-       CPURV_HAS_ZFINX,
-       CPURV_HAS_ZDINX,
-       CPURV_HAS_ZHINX,
-       CPURV_HAS_ZHINXMIN,
-       CPURV_HAS_ZICOND,
-       CPURV_HAS_ZMMUL
-      );
-
  const
    cpu_capabilities : array[tcputype] of set of tcpuflags =
      ( { cpu_none      } [],

compiler/riscv64/cpuinfo.pas

@@ -21,17 +21,9 @@ interface
 uses
   globtype;
 
-type
-  bestreal = double;
-  bestrealrec = TDoubleRec;
-  ts32real = single;
-  ts64real = double;
-  ts80real = extended;
-  ts128real = extended;
-  ts64comp = comp;
-
-  pbestreal = ^bestreal;
+{$I cpuinfo.inc}
 
+type
   { possible supported processors for this target }
   tcputype = (cpu_none,
     cpu_rv64imac,
@@ -44,23 +36,15 @@ type
     cpu_rv64gcb
   );
 
-  tfputype =
-    (fpu_none,
-    fpu_libgcc,
-    fpu_soft,
-    fpu_fd
+  tcontrollertype =
+    (ct_none
     );
 
-   tcontrollertype =
-     (ct_none
-     );
-
-   tcontrollerdatatype = record
-      controllertypestr, controllerunitstr: string[20];
-      cputype: tcputype; fputype: tfputype;
-      flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
-   end;
-
+  tcontrollerdatatype = record
+     controllertypestr, controllerunitstr: string[20];
+     cputype: tcputype; fputype: tfputype;
+     flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
+  end;
 
 Const
   { Is there support for dealing with multiple microcontrollers available }
@@ -101,13 +85,6 @@ Const
     'RV64GCB'
     );
 
-  fputypestr: array[tfputype] of string[8] = (
-    'NONE',
-    'LIBGCC',
-    'SOFT',
-    'FD'
-    );
-
    { Supported optimizations, only used for information }
    supported_optimizerswitches = genericlevel1optimizerswitches+
                                  genericlevel2optimizerswitches+
@@ -124,36 +101,6 @@ Const
    level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches;
    level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_opt_stackframe];
 
- type
-   tcpuflags =
-      (CPURV_HAS_MUL,
-       CPURV_HAS_ATOMIC,
-       CPURV_HAS_COMPACT,
-       CPURV_HAS_16REGISTERS,
-       CPURV_HAS_ZBA,
-       CPURV_HAS_ZBB,
-       CPURV_HAS_ZBC,
-       CPURV_HAS_ZBS,
-       CPURV_HAS_ZBKB,
-       CPURV_HAS_ZBKC,
-       CPURV_HAS_ZBKX,
-       CPURV_HAS_CSR_INSTRUCTIONS,   { extension Zicsr    }
-       CPURV_HAS_FETCH_FENCE,        { extension Zifencei }
-       CPURV_HAS_ZIHINTPAUSE,
-       CPURV_HAS_F,
-       CPURV_HAS_D,
-       CPURV_HAS_Q,
-       CPURV_HAS_ZFH,
-       CPURV_HAS_ZFHMIN,
-       CPURV_HAS_ZFA,
-       CPURV_HAS_ZFINX,
-       CPURV_HAS_ZDINX,
-       CPURV_HAS_ZHINX,
-       CPURV_HAS_ZHINXMIN,
-       CPURV_HAS_ZICOND,
-       CPURV_HAS_ZMMUL
-      );
-
  const
    cpu_capabilities : array[tcputype] of set of tcpuflags =
      ( { cpu_none       } [],