Fix ARM LoadScheduler in case of Pre/PostIndexed addressing

There was an interference between the load scheduler and then
Str/LdrAdd/Sub2Str/Ldr peephole optimizer.

ldrb r0, [r2]
ldrb r1, [r2, #1]
orr r3, r0, r1
add r2, r2, #2

got changed pre-regalloc to:
ldrb r1, [r2, #1]
ldrb r0, [r2]
orr r3, r0, r1
add r2, r2, #2

and the peephole optimizer collapsed the add into the second ldrd:
ldrb r1, [r2, #1]
ldrb r0, [r2], #2
orr r3, r0, r1

Then the post-peephole optimizer changed that into:
ldrb r0, [r2], #2
ldrb r1, [r2, #1]
orr r3, r0, r1

so r1 got loaded from a modified base-register.

This patch prevents the scheduler from moving an ldr-instruction if it
uses Pre/Post-indexing and the instruction before it uses the
base-register.

git-svn-id: trunk@28284 -

compiler/arm/aoptcpu.pas

@@ -2435,7 +2435,10 @@ Implementation
             { first instruction might not change the register used as index }
             ((taicpu(hp1).oper[1]^.ref^.index=NR_NO) or
              not(RegModifiedByInstruction(taicpu(hp1).oper[1]^.ref^.index,p))
-            ) then
+            ) and
+            { if we modify the basereg AND the first instruction used that reg, we can not schedule }
+            ((taicpu(hp1).oper[1]^.ref^.addressmode = AM_OFFSET) or
+             not(instructionLoadsFromReg(taicpu(hp1).oper[1]^.ref^.base,p))) then
             begin
               hp3:=tai(p.Previous);
               hp5:=tai(p.next);