* cr*, dr*, tr* registers are 64 bit on x86-64

git-svn-id: trunk@18243 -

.gitattributes

@@ -9138,6 +9138,7 @@ tests/tbs/tb0575.pp svneol=native#text/plain
 tests/tbs/tb0576.pp svneol=native#text/plain
 tests/tbs/tb0577.pp svneol=native#text/plain
 tests/tbs/tb0577a.pp svneol=native#text/plain
+tests/tbs/tb0578.pp svneol=native#text/pascal
 tests/tbs/tb205.pp svneol=native#text/plain
 tests/tbs/ub0060.pp svneol=native#text/plain
 tests/tbs/ub0069.pp svneol=native#text/plain

compiler/x86/aasmcpu.pas

@@ -92,7 +92,11 @@ interface
       OT_REG_SMASK = otf_sub0 or otf_sub1 or otf_sub2 or otf_sub3;
 
       { register class 0: CRx, DRx and TRx }
+{$ifdef x86_64}
+      OT_REG_CDT   = OT_REGISTER or otf_reg_cdt or OT_BITS64;
+{$else x86_64}
       OT_REG_CDT   = OT_REGISTER or otf_reg_cdt or OT_BITS32;
+{$endif x86_64}
       OT_REG_CREG  = OT_REG_CDT or otf_sub0;  { CRn  }
       OT_REG_DREG  = OT_REG_CDT or otf_sub1;  { DRn  }
       OT_REG_TREG  = OT_REG_CDT or otf_sub2;  { TRn  }

compiler/x86/cpubase.pas

@@ -348,7 +348,11 @@ implementation
           R_SPECIALREGISTER :
             case reg of
               NR_CS,NR_DS,NR_ES,NR_SS,NR_FS,NR_GS:
-                reg_cgsize:=OS_16
+                reg_cgsize:=OS_16;
+{$ifdef x86_64}
+              NR_DR0..NR_TR7:
+                reg_cgsize:=OS_64;
+{$endif x86_64}
               else
                 reg_cgsize:=OS_32
             end

tests/tbs/tb0578.pp

@@ -0,0 +1,14 @@
+{ %OPT=-Sew }
+{ %CPU=x86_64 }
+{ %NORUN }
+
+{$asmmode intel}
+begin
+  asm
+    mov rax,cr0
+    mov rax,cr4
+    mov rax,tr3
+    mov rax,cr3
+    mov rax,dr0
+  end;
+end.