* RiscV: check if the currently selected instruction set supports pause

compiler/msg/errore.msg

@@ -2696,6 +2696,9 @@ cg_w_interrupt_does_not_save_registers=06062_W_The target CPU does not support p
 cg_f_unknown_internal_procedure_number=06063_F_Unknown internal procedure number "$1"
 % The directive \var{internproc} is used with a number not known by the compiler. \var{internproc} should be used only by the
 % supplied RTL or by users really knowing what they are doing.
+cg_e_intrinsic_not_supported_by_instruction_set=06064_E_Intrinsic not supported by the currently selected instruction set
+% The intrinsic translates into an assembler instruction which is not supported by the instruction set
+% selected by \var{-Cp}
 %
 % \end{description}
 # EndOfTeX

compiler/riscv/nrvinl.pas

@@ -83,7 +83,11 @@ implementation
          Result:=nil;
          case inlinenumber of
            in_riscv_pause:
-             resultdef:=voidtype;
+             begin
+               if not(CPURV_HAS_ZIHINTPAUSE in cpu_capabilities[current_settings.cputype]) then
+                 Message(cg_e_intrinsic_not_supported_by_instruction_set);
+               resultdef:=voidtype;
+             end;
            else
              result:=inherited;
          end;

compiler/riscv/nrvutil.pas

@@ -93,6 +93,8 @@ implementation
             attr_arch:=attr_arch+'_zicsr2p0';
           if CPURV_HAS_FETCH_FENCE in cpu_capabilities[current_settings.cputype] then
             attr_arch:=attr_arch+'_zifencei2p0';
+          if CPURV_HAS_ZIHINTPAUSE in cpu_capabilities[current_settings.cputype] then
+            attr_arch:=attr_arch+'_zihintpause1p0';
           if CPURV_HAS_ZMMUL in cpu_capabilities[current_settings.cputype] then
             attr_arch:=attr_arch+'_zmmul1p0';
           if CPURV_HAS_ZFA in cpu_capabilities[current_settings.cputype] then

compiler/riscv32/cpuinfo.pas

@@ -228,6 +228,7 @@ Const
        CPURV_HAS_ZBKX,
        CPURV_HAS_CSR_INSTRUCTIONS,   { extension Zicsr    }
        CPURV_HAS_FETCH_FENCE,        { extension Zifencei }
+       CPURV_HAS_ZIHINTPAUSE,
        CPURV_HAS_F,
        CPURV_HAS_D,
        CPURV_HAS_Q,

compiler/riscv64/cpuinfo.pas

@@ -139,6 +139,7 @@ Const
        CPURV_HAS_ZBKX,
        CPURV_HAS_CSR_INSTRUCTIONS,   { extension Zicsr    }
        CPURV_HAS_FETCH_FENCE,        { extension Zifencei }
+       CPURV_HAS_ZIHINTPAUSE,
        CPURV_HAS_F,
        CPURV_HAS_D,
        CPURV_HAS_Q,