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@@ -1216,7 +1216,8 @@ Implementation
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add r1, r3, #imm
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ldr r0, [r1, r2, lsl #2]
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}
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- if (taicpu(p).opcode = A_MOV) and
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+ if (not(current_settings.cputype in cpu_thumb)) and
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+ (taicpu(p).opcode = A_MOV) and
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(taicpu(p).ops = 3) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[2]^.typ = top_shifterop) and
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@@ -1224,6 +1225,12 @@ Implementation
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it is also extremly unlikely to be emitted this way}
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(taicpu(p).oper[2]^.shifterop^.shiftmode <> SM_RRX) and
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(taicpu(p).oper[2]^.shifterop^.shiftimm <> 0) and
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+ { thumb2 allows only lsl #0..#3 }
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+ (not(current_settings.cputype in cpu_thumb2) or
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+ ((taicpu(p).oper[2]^.shifterop^.shiftimm in [0..3]) and
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+ (taicpu(p).oper[2]^.shifterop^.shiftmode=SM_LSL)
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+ )
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+ ) and
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(taicpu(p).oppostfix = PF_NONE) and
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GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
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{Only LDR, LDRB, STR, STRB can handle scaled register indexing}
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florian