+ RiscV: vector registers

compiler/riscv/rvreg.dat

@@ -73,5 +73,39 @@ F29,$02,$00,$1d,f29,29,29
 F30,$02,$00,$1e,f30,30,30
 F31,$02,$00,$1f,f31,31,31
 
+; Vector registers
+V0,$04,$00,$00,v0,96,96
+V1,$04,$00,$01,v1,97,97
+V2,$04,$00,$02,v2,98,98
+V3,$04,$00,$03,v3,99,99
+V4,$04,$00,$04,v4,100,100
+V5,$04,$00,$05,v5,101,101
+V6,$04,$00,$06,v6,102,102
+V7,$04,$00,$07,v7,103,103
+V8,$04,$00,$08,v8,104,104
+V9,$04,$00,$09,v9,105,105
+V10,$04,$00,$0A,v10,106,106
+V11,$04,$00,$0B,v11,107,107
+V12,$04,$00,$0C,v12,108,108
+V13,$04,$00,$0D,v13,109,109
+V14,$04,$00,$0E,v14,110,110
+V15,$04,$00,$0F,v15,111,111
+V16,$04,$00,$10,v16,112,112
+V17,$04,$00,$11,v17,113,113
+V18,$04,$00,$12,v18,114,114
+V19,$04,$00,$13,v19,115,115
+V20,$04,$00,$14,v20,116,116
+V21,$04,$00,$15,v21,117,117
+V22,$04,$00,$16,v22,118,118
+V23,$04,$00,$17,v23,119,119
+V24,$04,$00,$18,v24,120,120
+V25,$04,$00,$19,v25,121,121
+V26,$04,$00,$1A,v26,122,122
+V27,$04,$00,$1B,v27,123,123
+V28,$04,$00,$1C,v28,124,124
+V29,$04,$00,$1D,v29,125,125
+V30,$04,$00,$1E,v30,126,126
+V31,$04,$00,$1F,v31,127,127
+
 ; Special registers
 FCSR,$05,$00,$01,fcsr,0,0

compiler/riscv32/rrv32con.inc

@@ -64,4 +64,36 @@ NR_F28 = tregister($0200001c);
 NR_F29 = tregister($0200001d);
 NR_F30 = tregister($0200001e);
 NR_F31 = tregister($0200001f);
+NR_V0 = tregister($04000000);
+NR_V1 = tregister($04000001);
+NR_V2 = tregister($04000002);
+NR_V3 = tregister($04000003);
+NR_V4 = tregister($04000004);
+NR_V5 = tregister($04000005);
+NR_V6 = tregister($04000006);
+NR_V7 = tregister($04000007);
+NR_V8 = tregister($04000008);
+NR_V9 = tregister($04000009);
+NR_V10 = tregister($0400000A);
+NR_V11 = tregister($0400000B);
+NR_V12 = tregister($0400000C);
+NR_V13 = tregister($0400000D);
+NR_V14 = tregister($0400000E);
+NR_V15 = tregister($0400000F);
+NR_V16 = tregister($04000010);
+NR_V17 = tregister($04000011);
+NR_V18 = tregister($04000012);
+NR_V19 = tregister($04000013);
+NR_V20 = tregister($04000014);
+NR_V21 = tregister($04000015);
+NR_V22 = tregister($04000016);
+NR_V23 = tregister($04000017);
+NR_V24 = tregister($04000018);
+NR_V25 = tregister($04000019);
+NR_V26 = tregister($0400001A);
+NR_V27 = tregister($0400001B);
+NR_V28 = tregister($0400001C);
+NR_V29 = tregister($0400001D);
+NR_V30 = tregister($0400001E);
+NR_V31 = tregister($0400001F);
 NR_FCSR = tregister($05000001);

compiler/riscv32/rrv32dwa.inc

@@ -64,4 +64,36 @@
 29,
 30,
 31,
+96,
+97,
+98,
+99,
+100,
+101,
+102,
+103,
+104,
+105,
+106,
+107,
+108,
+109,
+110,
+111,
+112,
+113,
+114,
+115,
+116,
+117,
+118,
+119,
+120,
+121,
+122,
+123,
+124,
+125,
+126,
+127,
 0

compiler/riscv32/rrv32nor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from rv32reg.dat }
-66
+98

compiler/riscv32/rrv32num.inc

@@ -64,4 +64,36 @@ tregister($0200001c),
 tregister($0200001d),
 tregister($0200001e),
 tregister($0200001f),
+tregister($04000000),
+tregister($04000001),
+tregister($04000002),
+tregister($04000003),
+tregister($04000004),
+tregister($04000005),
+tregister($04000006),
+tregister($04000007),
+tregister($04000008),
+tregister($04000009),
+tregister($0400000A),
+tregister($0400000B),
+tregister($0400000C),
+tregister($0400000D),
+tregister($0400000E),
+tregister($0400000F),
+tregister($04000010),
+tregister($04000011),
+tregister($04000012),
+tregister($04000013),
+tregister($04000014),
+tregister($04000015),
+tregister($04000016),
+tregister($04000017),
+tregister($04000018),
+tregister($04000019),
+tregister($0400001A),
+tregister($0400001B),
+tregister($0400001C),
+tregister($0400001D),
+tregister($0400001E),
+tregister($0400001F),
 tregister($05000001)

compiler/riscv32/rrv32rni.inc

@@ -64,4 +64,36 @@
 62,
 63,
 64,
-65
+65,
+66,
+67,
+68,
+69,
+70,
+71,
+72,
+73,
+74,
+75,
+76,
+77,
+78,
+79,
+80,
+81,
+82,
+83,
+84,
+85,
+86,
+87,
+88,
+89,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97

compiler/riscv32/rrv32sri.inc

@@ -32,7 +32,39 @@
 40,
 41,
 42,
+97,
 65,
+66,
+75,
+76,
+77,
+78,
+79,
+80,
+81,
+82,
+83,
+84,
+67,
+85,
+86,
+87,
+88,
+89,
+90,
+91,
+92,
+93,
+94,
+68,
+95,
+96,
+69,
+70,
+71,
+72,
+73,
+74,
 1,
 2,
 11,

compiler/riscv32/rrv32sta.inc

@@ -64,4 +64,36 @@
 29,
 30,
 31,
+96,
+97,
+98,
+99,
+100,
+101,
+102,
+103,
+104,
+105,
+106,
+107,
+108,
+109,
+110,
+111,
+112,
+113,
+114,
+115,
+116,
+117,
+118,
+119,
+120,
+121,
+122,
+123,
+124,
+125,
+126,
+127,
 0

compiler/riscv32/rrv32std.inc

@@ -64,4 +64,36 @@
 'f29',
 'f30',
 'f31',
+'v0',
+'v1',
+'v2',
+'v3',
+'v4',
+'v5',
+'v6',
+'v7',
+'v8',
+'v9',
+'v10',
+'v11',
+'v12',
+'v13',
+'v14',
+'v15',
+'v16',
+'v17',
+'v18',
+'v19',
+'v20',
+'v21',
+'v22',
+'v23',
+'v24',
+'v25',
+'v26',
+'v27',
+'v28',
+'v29',
+'v30',
+'v31',
 'fcsr'

compiler/riscv32/rrv32sup.inc

@@ -64,4 +64,36 @@ RS_F28 = $1c;
 RS_F29 = $1d;
 RS_F30 = $1e;
 RS_F31 = $1f;
+RS_V0 = $00;
+RS_V1 = $01;
+RS_V2 = $02;
+RS_V3 = $03;
+RS_V4 = $04;
+RS_V5 = $05;
+RS_V6 = $06;
+RS_V7 = $07;
+RS_V8 = $08;
+RS_V9 = $09;
+RS_V10 = $0A;
+RS_V11 = $0B;
+RS_V12 = $0C;
+RS_V13 = $0D;
+RS_V14 = $0E;
+RS_V15 = $0F;
+RS_V16 = $10;
+RS_V17 = $11;
+RS_V18 = $12;
+RS_V19 = $13;
+RS_V20 = $14;
+RS_V21 = $15;
+RS_V22 = $16;
+RS_V23 = $17;
+RS_V24 = $18;
+RS_V25 = $19;
+RS_V26 = $1A;
+RS_V27 = $1B;
+RS_V28 = $1C;
+RS_V29 = $1D;
+RS_V30 = $1E;
+RS_V31 = $1F;
 RS_FCSR = $01;

compiler/riscv64/rrv64con.inc

@@ -64,4 +64,36 @@ NR_F28 = tregister($0200001c);
 NR_F29 = tregister($0200001d);
 NR_F30 = tregister($0200001e);
 NR_F31 = tregister($0200001f);
+NR_V0 = tregister($04000000);
+NR_V1 = tregister($04000001);
+NR_V2 = tregister($04000002);
+NR_V3 = tregister($04000003);
+NR_V4 = tregister($04000004);
+NR_V5 = tregister($04000005);
+NR_V6 = tregister($04000006);
+NR_V7 = tregister($04000007);
+NR_V8 = tregister($04000008);
+NR_V9 = tregister($04000009);
+NR_V10 = tregister($0400000A);
+NR_V11 = tregister($0400000B);
+NR_V12 = tregister($0400000C);
+NR_V13 = tregister($0400000D);
+NR_V14 = tregister($0400000E);
+NR_V15 = tregister($0400000F);
+NR_V16 = tregister($04000010);
+NR_V17 = tregister($04000011);
+NR_V18 = tregister($04000012);
+NR_V19 = tregister($04000013);
+NR_V20 = tregister($04000014);
+NR_V21 = tregister($04000015);
+NR_V22 = tregister($04000016);
+NR_V23 = tregister($04000017);
+NR_V24 = tregister($04000018);
+NR_V25 = tregister($04000019);
+NR_V26 = tregister($0400001A);
+NR_V27 = tregister($0400001B);
+NR_V28 = tregister($0400001C);
+NR_V29 = tregister($0400001D);
+NR_V30 = tregister($0400001E);
+NR_V31 = tregister($0400001F);
 NR_FCSR = tregister($05000001);

compiler/riscv64/rrv64dwa.inc

@@ -64,4 +64,36 @@
 29,
 30,
 31,
+96,
+97,
+98,
+99,
+100,
+101,
+102,
+103,
+104,
+105,
+106,
+107,
+108,
+109,
+110,
+111,
+112,
+113,
+114,
+115,
+116,
+117,
+118,
+119,
+120,
+121,
+122,
+123,
+124,
+125,
+126,
+127,
 0

compiler/riscv64/rrv64nor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from rv32reg.dat }
-66
+98

compiler/riscv64/rrv64num.inc

@@ -64,4 +64,36 @@ tregister($0200001c),
 tregister($0200001d),
 tregister($0200001e),
 tregister($0200001f),
+tregister($04000000),
+tregister($04000001),
+tregister($04000002),
+tregister($04000003),
+tregister($04000004),
+tregister($04000005),
+tregister($04000006),
+tregister($04000007),
+tregister($04000008),
+tregister($04000009),
+tregister($0400000A),
+tregister($0400000B),
+tregister($0400000C),
+tregister($0400000D),
+tregister($0400000E),
+tregister($0400000F),
+tregister($04000010),
+tregister($04000011),
+tregister($04000012),
+tregister($04000013),
+tregister($04000014),
+tregister($04000015),
+tregister($04000016),
+tregister($04000017),
+tregister($04000018),
+tregister($04000019),
+tregister($0400001A),
+tregister($0400001B),
+tregister($0400001C),
+tregister($0400001D),
+tregister($0400001E),
+tregister($0400001F),
 tregister($05000001)

compiler/riscv64/rrv64rni.inc

@@ -64,4 +64,36 @@
 62,
 63,
 64,
-65
+65,
+66,
+67,
+68,
+69,
+70,
+71,
+72,
+73,
+74,
+75,
+76,
+77,
+78,
+79,
+80,
+81,
+82,
+83,
+84,
+85,
+86,
+87,
+88,
+89,
+90,
+91,
+92,
+93,
+94,
+95,
+96,
+97

compiler/riscv64/rrv64sri.inc

@@ -32,7 +32,39 @@
 40,
 41,
 42,
+97,
 65,
+66,
+75,
+76,
+77,
+78,
+79,
+80,
+81,
+82,
+83,
+84,
+67,
+85,
+86,
+87,
+88,
+89,
+90,
+91,
+92,
+93,
+94,
+68,
+95,
+96,
+69,
+70,
+71,
+72,
+73,
+74,
 1,
 2,
 11,

compiler/riscv64/rrv64sta.inc

@@ -64,4 +64,36 @@
 29,
 30,
 31,
+96,
+97,
+98,
+99,
+100,
+101,
+102,
+103,
+104,
+105,
+106,
+107,
+108,
+109,
+110,
+111,
+112,
+113,
+114,
+115,
+116,
+117,
+118,
+119,
+120,
+121,
+122,
+123,
+124,
+125,
+126,
+127,
 0

compiler/riscv64/rrv64std.inc

@@ -64,4 +64,36 @@
 'f29',
 'f30',
 'f31',
+'v0',
+'v1',
+'v2',
+'v3',
+'v4',
+'v5',
+'v6',
+'v7',
+'v8',
+'v9',
+'v10',
+'v11',
+'v12',
+'v13',
+'v14',
+'v15',
+'v16',
+'v17',
+'v18',
+'v19',
+'v20',
+'v21',
+'v22',
+'v23',
+'v24',
+'v25',
+'v26',
+'v27',
+'v28',
+'v29',
+'v30',
+'v31',
 'fcsr'

compiler/riscv64/rrv64sup.inc

@@ -64,4 +64,36 @@ RS_F28 = $1c;
 RS_F29 = $1d;
 RS_F30 = $1e;
 RS_F31 = $1f;
+RS_V0 = $00;
+RS_V1 = $01;
+RS_V2 = $02;
+RS_V3 = $03;
+RS_V4 = $04;
+RS_V5 = $05;
+RS_V6 = $06;
+RS_V7 = $07;
+RS_V8 = $08;
+RS_V9 = $09;
+RS_V10 = $0A;
+RS_V11 = $0B;
+RS_V12 = $0C;
+RS_V13 = $0D;
+RS_V14 = $0E;
+RS_V15 = $0F;
+RS_V16 = $10;
+RS_V17 = $11;
+RS_V18 = $12;
+RS_V19 = $13;
+RS_V20 = $14;
+RS_V21 = $15;
+RS_V22 = $16;
+RS_V23 = $17;
+RS_V24 = $18;
+RS_V25 = $19;
+RS_V26 = $1A;
+RS_V27 = $1B;
+RS_V28 = $1C;
+RS_V29 = $1D;
+RS_V30 = $1E;
+RS_V31 = $1F;
 RS_FCSR = $01;

compiler/utils/genrvvreg.pp

@@ -0,0 +1,10 @@
+{ utility to avoid the tedious typing of register numbers for RiscV Vector registers }
+var
+  i : longint;
+
+begin
+  for i:=0 to 31 do
+    begin
+      writeln('V',i,',$04,$00,$',hexstr(i,2),',v',i,',',i+96,',',i+96);
+    end;
+end.