* made internal errors for M68K unique

* fixed comment
* added comment regarding the potential usage of an address register instead of an int one

git-svn-id: trunk@22744 -

compiler/m68k/cgcpu.pas

@@ -188,7 +188,7 @@ unit cgcpu;
          if ref.index <> NR_NO then
            begin
              if ref.base <> NR_NO then
-                internalerror(20020814);
+                internalerror(2002081401);
              if (ref.offset < low(shortint)) or (ref.offset > high(shortint)) then
                 isvalidrefoffset := false
            end
@@ -926,7 +926,7 @@ unit cgcpu;
               begin
                 if (a >= 1) and (a <= 8) then
                  begin
-                   { now allowed to shift an address register }
+                   { not allowed to shift an address register }
                    if (isaddressregister(reg)) then
                      begin
                        scratch_reg := getintregister(list,OS_INT);

compiler/m68k/n68kcnv.pas

@@ -130,7 +130,7 @@ implementation
           internalerror(200110011);
         { has to be handled by a helper }
         if not signed then
-           internalerror(20020814);
+           internalerror(2002081404);
 
         location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,opsize);
         if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER,LOC_REFERENCE,LOC_CREFERENCE]) then

compiler/ncgutil.pas

@@ -639,6 +639,12 @@ implementation
               end
             else
 {$endif cpu64bitalu}
+            { Note: for withs of records (and maybe objects, classes, etc.) an
+                    address register could be set here, but that is later
+                    changed to an intregister neverthless when in the
+                    tcgassignmentnode maybechangeloadnodereg is called for the
+                    temporary node; so the workaround for now is to fix the
+                    symptoms... }
               l.register:=cg.getintregister(list,l.size);
           end;
       end;