Merged revisions 7567 via svnmerge from

http://svn.freepascal.org/svn/fpc/branches/ssa/compiler

........
  r7567 | florian | 2007-06-03 22:53:07 +0200 (So, 03 Jun 2007) | 2 lines
  
  * better code generation for op_reg_reg_reg if src1 and dst are equal
........

git-svn-id: trunk@7569 -

compiler/cgobj.pas

@@ -2695,10 +2695,16 @@ implementation
           end
         else
           begin
-            tmpreg:=getintregister(list,size);
-            a_load_reg_reg(list,size,size,src2,tmpreg);
-            a_op_reg_reg(list,op,size,src1,tmpreg);
-            a_load_reg_reg(list,size,size,tmpreg,dst);
+            { can we do a direct operation on the target register ? }
+            if op in [OP_ADD,OP_MUL,OP_AND,OP_MOVE,OP_XOR,OP_IMUL,OP_OR] then
+              a_op_reg_reg(list,op,size,src2,dst)
+            else
+              begin
+                tmpreg:=getintregister(list,size);
+                a_load_reg_reg(list,size,size,src2,tmpreg);
+                a_op_reg_reg(list,op,size,src1,tmpreg);
+                a_load_reg_reg(list,size,size,tmpreg,dst);
+              end;
           end;
       end;