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@@ -3076,6 +3076,55 @@ unit aoptx86;
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Result:=true;
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exit;
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end;
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+
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+{$ifdef x86_64}
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+ { Convert:
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+ movq x(ref),%reg64
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+ shrq y,%reg64
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+ To:
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+ movq x+4(ref),%reg32
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+ shrq y-32,%reg32 (Remove if y = 32)
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+ }
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+ if (taicpu(p).opsize = S_Q) and
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+ (taicpu(p).oper[0]^.typ = top_ref) and { Second operand will be a register }
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+ (taicpu(p).oper[0]^.ref^.offset <= $7FFFFFFB) and
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+ MatchInstruction(hp1, A_SHR, [taicpu(p).opsize]) and
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+ MatchOpType(taicpu(hp1), top_const, top_reg) and
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+ (taicpu(hp1).oper[0]^.val >= 32) and
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+ (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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+ begin
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+ RegName1 := debug_regname(taicpu(hp1).oper[1]^.reg);
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+ PreMessage := 'movq ' + debug_operstr(taicpu(p).oper[0]^) + ',' + RegName1 + '; ' +
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+ 'shrq $' + debug_tostr(taicpu(hp1).oper[0]^.val) + ',' + RegName1 + ' -> movl ';
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+
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+ { Convert to 32-bit }
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+ setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
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+ taicpu(p).opsize := S_L;
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+
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+ Inc(taicpu(p).oper[0]^.ref^.offset, 4);
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+
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+ PreMessage := PreMessage + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg);
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+ if (taicpu(hp1).oper[0]^.val = 32) then
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+ begin
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+ DebugMsg(SPeepholeOptimization + PreMessage + ' (MovShr2Mov)', p);
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+ RemoveInstruction(hp1);
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+ end
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+ else
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+ begin
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+ { This will potentially open up more arithmetic operations since
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+ the peephole optimizer now has a big hint that only the lower
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+ 32 bits are currently in use (and opcodes are smaller in size) }
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+ setsubreg(taicpu(hp1).oper[1]^.reg, R_SUBD);
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+ taicpu(hp1).opsize := S_L;
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+
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+ Dec(taicpu(hp1).oper[0]^.val, 32);
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+ DebugMsg(SPeepholeOptimization + PreMessage +
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+ '; shrl $' + debug_tostr(taicpu(hp1).oper[0]^.val) + ',' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' (MovShr2MovShr)', p);
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+ end;
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+ Result := True;
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+ Exit;
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+ end;
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+{$endif x86_64}
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end;
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florian