* initial revision of new register naming

compiler/arm/agarmgas.pas

@@ -187,7 +187,7 @@ unit agarmgas;
     end;
 
     const
-      shifterop2str: array[tshiftertype] of string[3] = ('','asr','lsl','lsr','ror','rrx');
+      shiftmode2str: array[tshiftmode] of string[3] = ('','lsl','lsr','asr','ror','rrx');
 
     function getopstr(const o:toper) : string;
     var
@@ -208,12 +208,12 @@ unit agarmgas;
             if (o.shifterop^.rs.enum<>R_NO) and (o.shifterop^.shiftimm=0) then
               begin
                 if o.shifterop^.rs.enum=R_INTREGISTER then
-                  getopstr:=shifterop2str[o.shifterop^.shiftertype]+' '+gas_regname(o.shifterop^.rs.number)
+                  getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' '+gas_regname(o.shifterop^.rs.number)
                 else
-                  getopstr:=shifterop2str[o.shifterop^.shiftertype]+' '+gas_reg2str[o.shifterop^.rs.enum];
+                  getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' '+gas_reg2str[o.shifterop^.rs.enum];
               end
             else if (o.shifterop^.rs.enum=R_NO) then
-              getopstr:=shifterop2str[o.shifterop^.shiftertype]+' #'+tostr(o.shifterop^.shiftimm)
+              getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' #'+tostr(o.shifterop^.shiftimm)
             else internalerror(200308282);
           end;
         top_const:
@@ -330,7 +330,10 @@ begin
 end.
 {
   $Log$
-  Revision 1.7  2003-09-01 15:11:16  florian
+  Revision 1.8  2003-09-03 19:10:30  florian
+    * initial revision of new register naming
+
+  Revision 1.7  2003/09/01 15:11:16  florian
     * fixed reference handling
     * fixed operand postfix for floating point instructions
     * fixed wrong shifter constant handling

compiler/arm/cgcpu.pas

@@ -54,7 +54,6 @@ unit cgcpu;
           size: tcgsize; src1, src2, dst: tregister); override;
 
         { move instructions }
-        procedure handle_load_store(list:taasmoutput;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference);
         procedure a_load_const_reg(list : taasmoutput; size: tcgsize; a : aword;reg : tregister);override;
         procedure a_load_reg_ref(list : taasmoutput; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
         procedure a_load_ref_reg(list : taasmoutput; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
@@ -92,6 +91,8 @@ unit cgcpu;
         procedure g_restore_all_registers(list : taasmoutput;accused,acchiused:boolean);override;
 
         procedure a_jmp_cond(list : taasmoutput;cond : TOpCmp;l: tasmlabel);
+        procedure fixref(list : taasmoutput;var ref : treference);
+        procedure handle_load_store(list:taasmoutput;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference);
       end;
 
       tcg64farm = class(tcg64f32)
@@ -267,7 +268,7 @@ unit cgcpu;
                   if a>32 then
                     internalerror(200308291);
                   shifterop_reset(so);
-                  so.shiftertype:=SO_LSL;
+                  so.shiftmode:=SM_LSL;
                   so.shiftimm:=a;
                   list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
                 end;
@@ -276,7 +277,7 @@ unit cgcpu;
                   if a>32 then
                     internalerror(200308292);
                   shifterop_reset(so);
-                  so.shiftertype:=SO_LSR;
+                  so.shiftmode:=SM_LSR;
                   so.shiftimm:=a;
                   list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
                 end;
@@ -285,7 +286,7 @@ unit cgcpu;
                   if a>32 then
                     internalerror(200308291);
                   shifterop_reset(so);
-                  so.shiftertype:=SO_LSL;
+                  so.shiftmode:=SM_LSL;
                   so.shiftimm:=a;
                   list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
                 end;
@@ -326,21 +327,21 @@ unit cgcpu;
              begin
                shifterop_reset(so);
                so.rs:=src1;
-               so.shiftertype:=SO_LSL;
+               so.shiftmode:=SM_LSL;
                list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
              end;
            OP_SHR:
              begin
                shifterop_reset(so);
                so.rs:=src1;
-               so.shiftertype:=SO_LSR;
+               so.shiftmode:=SM_LSR;
                list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
              end;
            OP_SAR:
              begin
                shifterop_reset(so);
                so.rs:=src1;
-               so.shiftertype:=SO_ASR;
+               so.shiftmode:=SM_ASR;
                list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
              end;
            OP_IMUL,
@@ -562,28 +563,28 @@ unit cgcpu;
                    reg2,reg1,$ff);
                OS_S8:
                  begin
-                   so.shiftertype:=SO_LSL;
+                   so.shiftmode:=SM_LSL;
                    so.shiftimm:=24;
                    list.concat(taicpu.op_reg_reg_shifterop(A_MOV,reg2,reg1,so));
-                   so.shiftertype:=SO_ASR;
+                   so.shiftmode:=SM_ASR;
                    so.shiftimm:=24;
                    list.concat(taicpu.op_reg_reg_shifterop(A_MOV,reg2,reg2,so));
                  end;
                OS_16:
                  begin
-                   so.shiftertype:=SO_LSL;
+                   so.shiftmode:=SM_LSL;
                    so.shiftimm:=16;
                    list.concat(taicpu.op_reg_reg_shifterop(A_MOV,reg2,reg1,so));
-                   so.shiftertype:=SO_LSR;
+                   so.shiftmode:=SM_LSR;
                    so.shiftimm:=16;
                    list.concat(taicpu.op_reg_reg_shifterop(A_MOV,reg2,reg2,so));
                  end;
                OS_S16:
                  begin
-                   so.shiftertype:=SO_LSL;
+                   so.shiftmode:=SM_LSL;
                    so.shiftimm:=16;
                    list.concat(taicpu.op_reg_reg_shifterop(A_MOV,reg2,reg1,so));
-                   so.shiftertype:=SO_ASR;
+                   so.shiftmode:=SM_ASR;
                    so.shiftimm:=16;
                    list.concat(taicpu.op_reg_reg_shifterop(A_MOV,reg2,reg2,so));
                  end;
@@ -773,24 +774,39 @@ unit cgcpu;
 
     procedure tcgarm.a_loadaddr_ref_reg(list : taasmoutput;const ref : treference;r : tregister);
       var
-        tmpreg : tregister;
+        b : byte;
         tmpref : treference;
-        instr : taicpu;
-        l : tasmlabel;
       begin
-        {
-        tmpreg.enum:=R_INTREGISTER;
-        tmpreg.number:=NR_NO;
-
+        tmpref:=ref;
         { Be sure to have a base register }
-        if (ref.base.number=NR_NO) then
+        if (tmpref.base.number=NR_NO) then
           begin
-            if ref.shiftmode<>SM_None then
+            if tmpref.shiftmode<>SM_None then
               internalerror(200308294);
-            ref.base:=ref.index;
-            ref.index.number:=NR_NO;
+            tmpref.base:=tmpref.index;
+            tmpref.index.number:=NR_NO;
           end;
 
+        if assigned(tmpref.symbol) or
+           not(is_shifter_const(tmpref.offset,b)) or
+           ((tmpref.base.number<>NR_NO) and tmpref.index.number<>NR_NO)) then
+          fixref(list,tmpref);
+
+        if ref.index.number<>NR_NO then
+          begin
+          end
+        else
+          list.concat(taicpu.op_reg_reg(A_MOV,r,));
+          ref.signindex<0 then
+      end;
+
+
+    procedure tcgarm.fixref(list : taasmoutput;var ref : treference);
+      var
+        tmpreg : tregister;
+        tmpref : treference;
+        l : tasmlabel;
+      begin
         { absolute symbols can't be handled directly, we've to store the symbol reference
           in the text segment and access it pc relative
 
@@ -802,59 +818,49 @@ unit cgcpu;
           if the symbol is absolute or relative there.
         }
 
-        if (assigned(ref.symbol) and
-            not(is_pc(ref.base)) and
-            not(is_pc(ref.index))
-           ) or
-           (ref.offset<-4095) or
-           (ref.offset>4095) then
-          begin
-            { check consts distance }
+        { check consts distance }
+        {!!!!!}
 
-            { create consts entry }
-            objectlibrary.getdatalabel(l);
-            current_procinfo.aktlocaldata.concat(Tai_symbol.Create(l,0));
-            if assigned(ref.symbol) then
-              current_procinfo.aktlocaldata.concat(tai_const_symbol.Create_offset(ref.symbol,ref.offset))
-            else
-              current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(ref.offset));
+        { create consts entry }
+        objectlibrary.getdatalabel(l);
+        current_procinfo.aktlocaldata.concat(Tai_symbol.Create(l,0));
+        if assigned(ref.symbol) then
+          current_procinfo.aktlocaldata.concat(tai_const_symbol.Create_offset(ref.symbol,ref.offset))
+        else
+          current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(ref.offset));
 
-            { load consts entry }
-            tmpreg:=rg.getregisterint(list,OS_INT);
-            reference_reset(tmpref);
-            tmpref.symbol:=l;
-            tmpref.base.enum:=R_INTREGISTER;
-            tmpref.base.number:=NR_R15;
-            list.concat(taicpu.op_reg_ref(A_LDR,tmpreg,tmpref));
+        { load consts entry }
+        tmpreg:=rg.getregisterint(list,OS_INT);
+        reference_reset(tmpref);
+        tmpref.symbol:=l;
+        tmpref.base.enum:=R_INTREGISTER;
+        tmpref.base.number:=NR_R15;
+        list.concat(taicpu.op_reg_ref(A_LDR,tmpreg,tmpref));
 
-            if (ref.base.number<>NR_NO) then
+        if (ref.base.number<>NR_NO) then
+          begin
+            if ref.index.number<>NR_NO then
               begin
-                if ref.index.number<>NR_NO then
-                  begin
-                    list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
-                    rg.ungetregister(list,ref.base);
-                    ref.base:=tmpreg;
-                  end
-                else
-                  begin
-                    ref.index:=tmpreg;
-                    ref.shiftimm:=0;
-                    ref.signindex:=1;
-                    ref.shiftmode:=SM_None;
-                  end;
+                list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
+                rg.ungetregister(list,ref.base);
+                ref.base:=tmpreg;
               end
             else
-              ref.base:=tmpreg;
-            ref.offset:=0;
-            ref.symbol:=nil;
-          end;
-        list.concat(setoppostfix(taicpu.op_reg_ref(op,reg,ref),oppostfix);
-        if (tmpreg.number<>NR_NO) then
-          rg.ungetregisterint(list,tmpreg);
-        }
+              begin
+                ref.index:=tmpreg;
+                ref.shiftimm:=0;
+                ref.signindex:=1;
+                ref.shiftmode:=SM_None;
+              end;
+          end
+        else
+          ref.base:=tmpreg;
+        ref.offset:=0;
+        ref.symbol:=nil;
       end;
 
 
+
     procedure tcgarm.g_concatcopy(list : taasmoutput;const source,dest : treference;len : aword; delsource,loadref : boolean);
       var
         srcref,dstref:treference;
@@ -886,12 +892,12 @@ unit cgcpu;
 
       begin
         helpsize:=12;
+        dstref:=dest;
+        srcref:=source;
         if cs_littlesize in aktglobalswitches then
           helpsize:=8;
         if not loadref and (len<=helpsize) then
           begin
-            dstref:=dest;
-            srcref:=source;
             copysize:=4;
             cgsize:=OS_32;
             while len<>0 do
@@ -1121,7 +1127,10 @@ begin
 end.
 {
   $Log$
-  Revision 1.11  2003-09-03 11:18:37  florian
+  Revision 1.12  2003-09-03 19:10:30  florian
+    * initial revision of new register naming
+
+  Revision 1.11  2003/09/03 11:18:37  florian
     * fixed arm concatcopy
     + arm support in the common compiler sources added
     * moved some generic cg code around

compiler/arm/cpubase.pas

@@ -79,47 +79,7 @@ uses
                                   Registers
 *****************************************************************************}
 
-    type
-      {# Enumeration for all possible registers for cpu. It
-        is to note that all registers of the same type
-        (for example all FPU registers), should be grouped
-        together.
-      }
-      { don't change the order }
-      { it's used by the register size conversions        }
-      toldregister = (R_NO,
-        R_R0,R_R1,R_R2,R_R3,R_R4,R_R5,R_R6,R_R7,
-        R_R8,R_R9,R_R10,R_R11,R_R12,R_R13,R_R14,R_PC,
-        R_CPSR,
-        { FPA registers }
-        R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,
-        R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
-        { VPA registers }
-        R_S0,R_S1,R_S2,R_S3,R_S4,R_S5,R_S6,R_S7,
-        R_S8,R_S9,R_S10,R_S11,R_S12,R_S13,R_S14,R_S15,
-        R_S16,R_S17,R_S18,R_S19,R_S20,R_S21,R_S22,R_S23,
-        R_S24,R_S25,R_S26,R_S27,R_S28,R_S29,R_S30,R_S31,
-        R_D0,R_D1,R_D2,R_D3,R_D4,R_D5,R_D6,R_D7,
-        R_D8,R_D9,R_D10,R_D11,R_D12,R_D13,R_D14,R_D15,
-        R_INTREGISTER,R_FLOATREGISTER,R_MMXREGISTER,R_KNIREGISTER
-      );
-
     const
-      { special registers }
-      { Invalid register }
-      NR_NO    = $0000;
-
-      { Normal registers:}
-
-      { General purpose registers }
-      NR_R0 = $0100; NR_R1 = $0200; NR_R2 = $0300;
-      NR_R3 = $0400; NR_R4 = $0500; NR_R5 = $0600;
-      NR_R6 = $0700; NR_R7 = $0800; NR_R8 = $0900;
-      NR_R9 = $0A00; NR_R10 = $0B00; NR_R11 = $0C00;
-      NR_R12 = $0D00; NR_R13 = $0E00; NR_R14 = $0F00;
-      NR_R15 = $1000;
-      NR_PC  = NR_R15;
-
       { Super registers: }
       RS_NONE=$00;
       RS_R0 = $01;  RS_R1 = $02; RS_R2 = $03;
@@ -130,59 +90,47 @@ uses
       RS_R15 = $10;
       RS_PC = RS_R15;
 
-      first_supreg = RS_R0;
-      last_supreg = RS_R15;
+      RS_F0=$00;
+      RS_F1=$01;
+      RS_F2=$02;
+      RS_F3=$03;
+      RS_F4=$04;
+      RS_F5=$05;
+      RS_F6=$06;
+      RS_F7=$07;
 
-      { registers which may be destroyed by calls }
-      VOLATILE_INTREGISTERS = [RS_R0..RS_R3,RS_R12..RS_R15];
-      VOLATILE_FPUREGISTERS = [R_F0..R_F3];
+      RS_D0 = $01;  RS_D1 = $02; RS_D2 = $03;
+      RS_D3 = $04;  RS_D4 = $05; RS_D5 = $06;
+      RS_D6 = $07;  RS_D7 = $08; RS_D8 = $09;
+      RS_D9 = $0A;  RS_D10 = $0B; RS_D11 = $0C;
+      RS_D12 = $0D; RS_D13 = $0E; RS_D14 = $0F;
+      RS_D15 = $10;
 
-      { Number of first and last imaginary register. }
-      first_imreg     = $21;
-      last_imreg      = $ff;
+      { No Subregisters }
+      R_SUBWHOLE = R_SUBNONE;
 
-      { Subregisters, situation unknown!!.}
-      R_SUBWHOLE=$00;
-      R_SUBL=$00;
+      { Available Registers }
+      {$i rarmcon.inc}
 
     type
-      tnewregister=word;
-
-      Tregister = packed record
-        enum : Toldregister;
-        { This is a word for now, change to cardinal
-          when the old register coding is away.}
-        number : Tnewregister;
-      end;
-
-      Tsuperregister = byte;
-      Tsubregister = byte;
+      { Number of registers used for indexing in tables }
+      tregisterindex=0..{$i rarmnor.inc}-1;
 
-      { A type to store register locations for 64 Bit values. }
-      tregister64 = packed record
-        reglo,reghi : tregister;
-      end;
-
-      { alias for compact code }
-      treg64 = tregister64;
+    const
+      regnumber_table : array[tregisterindex] of tregister = (
+        {$i rarmnum.inc}
+      );
 
-      { Set type definition for registers }
-      tregisterset = set of toldregister;
-      tsupregset = set of tsuperregister;
+      regstabs_table : array[tregisterindex] of tregister = (
+        {$i rarmsta.inc}
+      );
 
-    const
-      { First register in the tregister enumeration }
-      firstreg = low(toldregister);
-      { Last register in the tregister enumeration }
-      lastreg  = R_D15;
+      { registers which may be destroyed by calls }
+      VOLATILE_INTREGISTERS = [RS_R0..RS_R3,RS_R12..RS_R15];
+      VOLATILE_FPUREGISTERS = [RS_F0..RS_F3];
 
     type
-      { Type definition for the array of string of register names }
-      reg2strtable = array[firstreg..lastreg] of string[6];
-      regname2regnumrec = record
-        name:string[6];
-        number:Tnewregister;
-      end;
+      totherregisterset = set of tregisterindex;
 
 {*****************************************************************************
                           Instruction post fixes
@@ -291,13 +239,10 @@ uses
 
       tupdatereg = (UR_None,UR_Update);
 
-
-      tshiftertype = (SO_None,SO_ASR,SO_LSL,SO_LSR,SO_ROR,SO_RRX);
-
       pshifterop = ^tshifterop;
 
       tshifterop = record
-        shiftertype : tshiftertype;
+        shiftmode : tshiftmode;
         rs : tregister;
         shiftimm : byte;
       end;
@@ -309,7 +254,7 @@ uses
          top_ref    : (ref:preference);
          top_const  : (val:aword);
          top_symbol : (sym:tasmsymbol;symofs:longint);
-         top_regset : (regset:tsupregset);
+         top_regset : (regset:set of RS_R0..RS_R15);
          top_shifterop : (shifterop : pshifterop);
       end;
 
@@ -384,21 +329,10 @@ uses
       max_operands = 3;
 
       {# Constant defining possibly all registers which might require saving }
-      ALL_REGISTERS = [firstreg..lastreg];
+      ALL_OTHERREGISTERS = [];
 
-      general_registers = [R_R0..R_PC];
       general_superregisters = [RS_R0..RS_PC];
 
-      {# low and high of the available maximum width integer general purpose }
-      { registers                                                            }
-      LoGPReg = R_R0;
-      HiGPReg = R_R14;
-
-      {# low and high of every possible width general purpose register (same as }
-      { above on most architctures apart from the 80x86)                        }
-      LoReg = R_R0;
-      HiReg = R_R14;
-
       {# Table of registers which can be allocated by the code generator
          internally, when generating the code.
       }
@@ -412,19 +346,22 @@ uses
       { c_countusableregsxxx = amount of registers in the usableregsxxx set    }
 
       maxintregs = 15;
-      maxintscratchregs = 2;
-      intregs = [R_R0..R_R14];
       usableregsint = [RS_R4..RS_R10];
       c_countusableregsint = 7;
 
       maxfpuregs = 8;
-      fpuregs = [R_F0..R_F7];
-      usableregsfpu = [R_F4..R_F7];
+      fpuregs = [RS_F0..RS_F7];
+      usableregsfpu = [RS_F4..RS_F7];
       c_countusableregsfpu = 4;
 
-      mmregs = [R_S0..R_D7];
-      usableregsmm = [R_S16..R_S31];
-      c_countusableregsmm  = 16;
+      mmregs = [RS_D0..RS_D15];
+      usableregsmm = [RS_D8..RS_D15];
+      c_countusableregsmm  = 8;
+
+      maxaddrregs = 0;
+      addrregs    = [];
+      usableregsaddr = [];
+      c_countusableregsaddr = 0;
 
 {*****************************************************************************
                                 Operand Sizes
@@ -465,67 +402,24 @@ uses
                 { VPA coprocessor codes }
                 );
 
-        { Standard register table (for each tregister enumeration). The
-          register strings should conform to the the names as defined
-          by the processor manufacturer
-        }
-        std_reg2str : reg2strtable = ('',
-          'r0','r1','r2','r3','r4','r5','r6','r7',
-          'r8','r9','r10','r11','r12','r13','r14','pc',
-          'cpsr',
-          { FPA registers }
-          'f0','f1','f2','f3','f4','f5','f6','f7',
-          'f8','f9','f10','f11','f12','f13','f14','f15',
-          { VPA registers }
-          's0','s1','s2','s3','s4','s5','s6','s7',
-          's8','s9','s10','s11','s12','s13','s14','s15',
-          's16','s17','s18','s19','s20','s21','s22','s23',
-          's24','s25','s26','s27','s28','s29','s30','s31',
-          'd0','d1','d2','d3','d4','d5','d6','d7',
-          'd8','d9','d10','d11','d12','d13','d14','d15'
-        );
-
 {*****************************************************************************
                                  Constants
 *****************************************************************************}
 
       firstsaveintreg = RS_R4;
       lastsaveintreg  = RS_R10;
-      firstsavefpureg = R_F4;
-      lastsavefpureg  = R_F7;
-      firstsavemmreg  = R_S16;
-      lastsavemmreg   = R_S31;
-
-//!!!      general_registers = [R_EAX,R_EBX,R_ECX,R_EDX];
-//!!!      general_superregisters = [RS_EAX,RS_EBX,RS_ECX,RS_EDX];
-
-
-//!!!      usableregsint = [first_imreg..last_imreg];
-//!!!      c_countusableregsint = 4;
-
-      maxaddrregs = 0;
-      addrregs    = [];
-      usableregsaddr = [];
-      c_countusableregsaddr = 0;
+      firstsavefpureg = RS_F4;
+      lastsavefpureg  = RS_F7;
+      firstsavemmreg  = RS_D8;
+      lastsavemmreg   = RS_D15;
 
       maxvarregs = 7;
-      varregs : Array [1..maxvarregs] of Tnewregister =
+      varregs : Array [1..maxvarregs] of tsuperregister =
                 (RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,RS_R10);
 
       maxfpuvarregs = 4;
-      fpuvarregs : Array [1..maxfpuvarregs] of Toldregister =
-                (R_F4,R_F5,R_F6,R_F7);
-
-{*****************************************************************************
-                               GDB Information
-*****************************************************************************}
-
-      {
-        I don't know where I could get this information for the arm
-      }
-      stab_regindex : array[0..0] of shortint =
-        (0
-      );
+      fpuvarregs : Array [1..maxfpuvarregs] of tsuperregister =
+                (RS_F4,RS_F5,RS_F6,RS_F7);
 
 {*****************************************************************************
                           Default generic sizes
@@ -548,7 +442,6 @@ uses
       NR_STACK_POINTER_REG = NR_R13;
       RS_STACK_POINTER_REG = RS_R13;
       { Frame pointer register }
-      frame_pointer_reg = R_R11;
       RS_FRAME_POINTER_REG = RS_R11;
       NR_FRAME_POINTER_REG = NR_R11;
       { Register for addressing absolute data in a position independant way,
@@ -575,8 +468,9 @@ uses
       NR_FUNCTION_RESULT64_HIGH_REG = NR_FUNCTION_RETURN64_HIGH_REG;
       RS_FUNCTION_RESULT64_HIGH_REG = RS_FUNCTION_RETURN64_HIGH_REG;
 
-      fpu_result_reg = R_F0;
-//!!!      mmresultreg = R_MM0;
+      NR_FPU_RESULT_REG = NR_F0;
+
+      NR_MM_RESULT_REG  = NR_NO;
 
       { Offset where the parent framepointer is pushed }
       PARENT_FRAMEPOINTER_OFFSET = 0;
@@ -593,7 +487,7 @@ uses
         This value can be deduced from the CALLED_USED_REGISTERS array in the
         GCC source.
       }
-      std_saved_registers = [R_R4..R_R10];
+      std_saved_registers = [RS_R4..RS_R10];
       { Required parameter alignment when calling a routine declared as
         stdcall and cdecl. The alignment value should be the one defined
         by GCC or the target ABI.
@@ -703,7 +597,10 @@ uses
 end.
 {
   $Log$
-  Revision 1.10  2003-09-01 15:11:16  florian
+  Revision 1.11  2003-09-03 19:10:30  florian
+    * initial revision of new register naming
+
+  Revision 1.10  2003/09/01 15:11:16  florian
     * fixed reference handling
     * fixed operand postfix for floating point instructions
     * fixed wrong shifter constant handling

compiler/arm/rarmcon.inc

@@ -0,0 +1,74 @@
+{ don't edit, this file is generated from armreg.dat }
+NR_NO = $00000000;
+NR_R0 = $01000000;
+NR_R1 = $01000001;
+NR_R2 = $01000002;
+NR_R3 = $01000003;
+NR_R4 = $01000004;
+NR_R5 = $01000005;
+NR_R6 = $01000006;
+NR_R7 = $01000007;
+NR_R8 = $01000008;
+NR_R9 = $01000009;
+NR_R10 = $0100000a;
+NR_R11 = $0100000b;
+NR_R12 = $0100000c;
+NR_R13 = $0100000d;
+NR_R14 = $0100000e;
+NR_R15 = $0100000f;
+NR_F0 = $02000000;
+NR_F1 = $02000001;
+NR_F2 = $02000002;
+NR_F3 = $02000003;
+NR_F4 = $02000004;
+NR_F5 = $02000005;
+NR_F6 = $02000006;
+NR_F7 = $02000007;
+NR_S0 = $02000000;
+NR_S1 = $02000000;
+NR_D0 = $02000000;
+NR_S2 = $02000000;
+NR_S3 = $02000000;
+NR_D1 = $02000000;
+NR_S4 = $02000000;
+NR_S5 = $02000000;
+NR_D2 = $02000000;
+NR_S6 = $02000000;
+NR_S7 = $02000000;
+NR_D3 = $02000000;
+NR_S8 = $02000000;
+NR_S9 = $02000000;
+NR_D4 = $02000000;
+NR_S10 = $02000000;
+NR_S11 = $02000000;
+NR_D5 = $02000000;
+NR_S12 = $02000000;
+NR_S13 = $02000000;
+NR_D6 = $02000000;
+NR_S14 = $02000000;
+NR_S15 = $02000000;
+NR_D7 = $02000000;
+NR_S16 = $02000000;
+NR_S17 = $02000000;
+NR_D8 = $02000000;
+NR_S18 = $02000000;
+NR_S19 = $02000000;
+NR_D9 = $02000000;
+NR_S20 = $02000000;
+NR_S21 = $02000000;
+NR_D10 = $02000000;
+NR_S22 = $02000000;
+NR_S23 = $02000000;
+NR_D11 = $02000000;
+NR_S24 = $02000000;
+NR_S25 = $02000000;
+NR_D12 = $02000000;
+NR_S26 = $02000000;
+NR_S27 = $02000000;
+NR_D13 = $02000000;
+NR_S28 = $02000000;
+NR_S29 = $02000000;
+NR_D14 = $02000000;
+NR_S30 = $02000000;
+NR_S31 = $02000000;
+NR_D15 = $02000000;

compiler/arm/rarmnor.inc

@@ -0,0 +1,2 @@
+{ don't edit, this file is generated from armreg.dat }
+73

compiler/arm/rarmnum.inc

@@ -0,0 +1,74 @@
+{ don't edit, this file is generated from armreg.dat }
+NR_NO,
+NR_R0,
+NR_R1,
+NR_R2,
+NR_R3,
+NR_R4,
+NR_R5,
+NR_R6,
+NR_R7,
+NR_R8,
+NR_R9,
+NR_R10,
+NR_R11,
+NR_R12,
+NR_R13,
+NR_R14,
+NR_R15,
+NR_F0,
+NR_F1,
+NR_F2,
+NR_F3,
+NR_F4,
+NR_F5,
+NR_F6,
+NR_F7,
+NR_S0,
+NR_S1,
+NR_D0,
+NR_S2,
+NR_S3,
+NR_D1,
+NR_S4,
+NR_S5,
+NR_D2,
+NR_S6,
+NR_S7,
+NR_D3,
+NR_S8,
+NR_S9,
+NR_D4,
+NR_S10,
+NR_S11,
+NR_D5,
+NR_S12,
+NR_S13,
+NR_D6,
+NR_S14,
+NR_S15,
+NR_D7,
+NR_S16,
+NR_S17,
+NR_D8,
+NR_S18,
+NR_S19,
+NR_D9,
+NR_S20,
+NR_S21,
+NR_D10,
+NR_S22,
+NR_S23,
+NR_D11,
+NR_S24,
+NR_S25,
+NR_D12,
+NR_S26,
+NR_S27,
+NR_D13,
+NR_S28,
+NR_S29,
+NR_D14,
+NR_S30,
+NR_S31,
+NR_D15

compiler/arm/rarmrni.inc

@@ -0,0 +1,74 @@
+{ don't edit, this file is generated from armreg.dat }
+0,
+1,
+66,
+67,
+68,
+69,
+70,
+71,
+72,
+41,
+42,
+43,
+44,
+45,
+46,
+47,
+48,
+17,
+50,
+51,
+52,
+53,
+54,
+55,
+56,
+25,
+26,
+27,
+28,
+29,
+30,
+31,
+32,
+33,
+34,
+35,
+36,
+37,
+38,
+39,
+40,
+57,
+58,
+59,
+60,
+61,
+62,
+63,
+64,
+49,
+65,
+18,
+2,
+19,
+3,
+20,
+4,
+21,
+5,
+22,
+6,
+23,
+7,
+24,
+8,
+9,
+10,
+11,
+12,
+13,
+14,
+15,
+16

compiler/arm/rarmsri.inc

@@ -0,0 +1,74 @@
+{ don't edit, this file is generated from armreg.dat }
+0,
+27,
+30,
+57,
+60,
+63,
+66,
+69,
+72,
+33,
+36,
+39,
+42,
+45,
+48,
+51,
+54,
+17,
+18,
+19,
+20,
+21,
+22,
+23,
+24,
+1,
+2,
+11,
+12,
+13,
+14,
+15,
+16,
+3,
+4,
+5,
+6,
+7,
+8,
+9,
+10,
+25,
+26,
+40,
+41,
+43,
+44,
+46,
+47,
+49,
+50,
+52,
+53,
+28,
+55,
+70,
+71,
+56,
+58,
+59,
+61,
+62,
+64,
+65,
+67,
+68,
+29,
+31,
+32,
+34,
+35,
+37,
+38

compiler/arm/rarmsta.inc

@@ -0,0 +1,74 @@
+{ don't edit, this file is generated from armreg.dat }
+-1,
+0,
+1,
+2,
+3,
+4,
+5,
+6,
+7,
+8,
+9,
+10,
+11,
+12,
+13,
+14,
+15,
+32,
+32,
+32,
+32,
+32,
+32,
+32,
+32,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0,
+0

compiler/arm/rarmstd.inc

@@ -0,0 +1,74 @@
+{ don't edit, this file is generated from armreg.dat }
+'INVALID',
+'r0',
+'r1',
+'r2',
+'r3',
+'r4',
+'r5',
+'r6',
+'r7',
+'r8',
+'r9',
+'r10',
+'r11',
+'r12',
+'r13',
+'r14',
+'r15',
+'f0',
+'f1',
+'f2',
+'f3',
+'f4',
+'f5',
+'f6',
+'f7',
+'s0',
+'s1',
+'d0',
+'s2',
+'s3',
+'d1',
+'s4',
+'s5',
+'d2',
+'s6',
+'s7',
+'d3',
+'s8',
+'s9',
+'d4',
+'s10',
+'s11',
+'d5',
+'s12',
+'s13',
+'d6',
+'s14',
+'s15',
+'d7',
+'s16',
+'s17',
+'d8',
+'s18',
+'s19',
+'d9',
+'s20',
+'s21',
+'d10',
+'s22',
+'s23',
+'d11',
+'s24',
+'s25',
+'d12',
+'s26',
+'s27',
+'d13',
+'s28',
+'s29',
+'d14',
+'s20',
+'s21',
+'d15'

compiler/arm/rarmsup.inc

@@ -0,0 +1,74 @@
+{ don't edit, this file is generated from armreg.dat }
+RS_NO = $00;
+RS_R0 = $00;
+RS_R1 = $01;
+RS_R2 = $02;
+RS_R3 = $03;
+RS_R4 = $04;
+RS_R5 = $05;
+RS_R6 = $06;
+RS_R7 = $07;
+RS_R8 = $08;
+RS_R9 = $09;
+RS_R10 = $0a;
+RS_R11 = $0b;
+RS_R12 = $0c;
+RS_R13 = $0d;
+RS_R14 = $0e;
+RS_R15 = $0f;
+RS_F0 = $00;
+RS_F1 = $01;
+RS_F2 = $02;
+RS_F3 = $03;
+RS_F4 = $04;
+RS_F5 = $05;
+RS_F6 = $06;
+RS_F7 = $07;
+RS_S0 = $00;
+RS_S1 = $00;
+RS_D0 = $00;
+RS_S2 = $00;
+RS_S3 = $00;
+RS_D1 = $00;
+RS_S4 = $00;
+RS_S5 = $00;
+RS_D2 = $00;
+RS_S6 = $00;
+RS_S7 = $00;
+RS_D3 = $00;
+RS_S8 = $00;
+RS_S9 = $00;
+RS_D4 = $00;
+RS_S10 = $00;
+RS_S11 = $00;
+RS_D5 = $00;
+RS_S12 = $00;
+RS_S13 = $00;
+RS_D6 = $00;
+RS_S14 = $00;
+RS_S15 = $00;
+RS_D7 = $00;
+RS_S16 = $00;
+RS_S17 = $00;
+RS_D8 = $00;
+RS_S18 = $00;
+RS_S19 = $00;
+RS_D9 = $00;
+RS_S20 = $00;
+RS_S21 = $00;
+RS_D10 = $00;
+RS_S22 = $00;
+RS_S23 = $00;
+RS_D11 = $00;
+RS_S24 = $00;
+RS_S25 = $00;
+RS_D12 = $00;
+RS_S26 = $00;
+RS_S27 = $00;
+RS_D13 = $00;
+RS_S28 = $00;
+RS_S29 = $00;
+RS_D14 = $00;
+RS_S30 = $00;
+RS_S31 = $00;
+RS_D15 = $00;