+ R_SUBH support added in x86/aasmcpu.spilling_create_load and spilling_create_store

git-svn-id: trunk@24477 -

compiler/x86/aasmcpu.pas

@@ -2947,12 +2947,19 @@ implementation
 
 
     function spilling_create_load(const ref:treference;r:tregister):Taicpu;
+      var
+        tmpref: treference;
       begin
         case getregtype(r) of
           R_INTREGISTER :
-            { we don't need special code here for 32 bit loads on x86_64, since
-              those will automatically zero-extend the upper 32 bits. }
-            result:=taicpu.op_ref_reg(A_MOV,reg2opsize(r),ref,r);
+            begin
+              tmpref:=ref;
+              if getsubreg(r)=R_SUBH then
+                inc(tmpref.offset);
+              { we don't need special code here for 32 bit loads on x86_64, since
+                those will automatically zero-extend the upper 32 bits. }
+              result:=taicpu.op_ref_reg(A_MOV,reg2opsize(r),tmpref,r);
+            end;
           R_MMREGISTER :
             case getsubreg(r) of
               R_SUBMMD:
@@ -2974,10 +2981,14 @@ implementation
     function spilling_create_store(r:tregister; const ref:treference):Taicpu;
       var
         size: topsize;
+        tmpref: treference;
       begin
         case getregtype(r) of
           R_INTREGISTER :
             begin
+              tmpref:=ref;
+              if getsubreg(r)=R_SUBH then
+                inc(tmpref.offset);
               size:=reg2opsize(r);
 {$ifdef x86_64}
               { even if it's a 32 bit reg, we still have to spill 64 bits
@@ -2988,7 +2999,7 @@ implementation
                   r:=newreg(getregtype(r),getsupreg(r),R_SUBWHOLE);
                 end;
 {$endif x86_64}
-              result:=taicpu.op_reg_ref(A_MOV,size,r,ref);
+              result:=taicpu.op_reg_ref(A_MOV,size,r,tmpref);
             end;
           R_MMREGISTER :
             case getsubreg(r) of