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@@ -443,11 +443,11 @@ Implementation
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For example:
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ldr reg2,[reg1, xxx]!
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mov reg1,reg2
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- is translated to:
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+ must be translated to:
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ldr reg1,[reg1, xxx]
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Preindexing must be removed there, since the same register is used as the base and as the target.
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- It is not allowed for ARM CPU and produces wrong results. }
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+ Such case is not allowed for ARM CPU and produces crash. }
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if (taicpu(p).opcode = A_LDR) and (taicpu(p).oper[1]^.typ = top_ref)
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and (taicpu(movp).oper[0]^.reg = taicpu(p).oper[1]^.ref^.base)
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then
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yury