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@@ -167,10 +167,14 @@ Implementation
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exit;
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{Take care of post/preincremented store and loads, they will change their base register}
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A_STR, A_LDR:
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- regLoadedWithNewValue :=
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- (taicpu(p).oper[1]^.typ=top_ref) and
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- (taicpu(p).oper[1]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) and
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- (taicpu(p).oper[1]^.ref^.base = reg);
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+ begin
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+ regLoadedWithNewValue :=
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+ (taicpu(p).oper[1]^.typ=top_ref) and
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+ (taicpu(p).oper[1]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) and
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+ (taicpu(p).oper[1]^.ref^.base = reg);
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+ {STR does not load into it's first register}
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+ if p.opcode = A_STR then exit;
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+ end;
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{ These four are writing into the first 2 register, UMLAL and SMLAL will also read from them }
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A_UMLAL, A_UMULL, A_SMLAL, A_SMULL:
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regLoadedWithNewValue :=
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