+ RiscV: support ZMMUL extension

compiler/riscv/cgrv.pas

@@ -316,7 +316,7 @@ unit cgrv;
               end
             else
 {$endif RISCV64}
-            if (op in [OP_IMUL,OP_MUL]) and not(CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype]) then
+            if (op in [OP_IMUL,OP_MUL]) and ([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]=[]) then
               begin
                 case size of
                   OS_8:

compiler/riscv/nrvadd.pas

@@ -213,7 +213,7 @@ implementation
 
     function trvaddnode.use_mul_helper: boolean;
       begin
-        if (nodetype=muln) and not(CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype]) then
+        if (nodetype=muln) and ([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]=[]) then
           result:=true
         else
           Result:=inherited use_mul_helper;
@@ -279,7 +279,7 @@ implementation
       begin
         if (nodetype=muln) and
            (left.resultdef.typ=orddef) and (left.resultdef.typ=orddef) and
-           (CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype])
+           ([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]<>[])
 {$ifdef cpu32bitalu}
            and (not (is_64bit(left.resultdef) or
                      is_64bit(right.resultdef)))
@@ -294,7 +294,7 @@ implementation
             expectloc:=LOC_REGISTER;
           end
         else if (nodetype=muln) and
-           (not (CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype])) and
+           ([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]=[]) and
            (is_64bit(left.resultdef) or
             is_64bit(right.resultdef)) then
           begin

compiler/riscv/nrvutil.pas

@@ -87,6 +87,8 @@ implementation
             attr_arch:=attr_arch+'_zicrs2p0';
           if CPURV_HAS_FETCH_FENCE in cpu_capabilities[current_settings.cputype] then
             attr_arch:=attr_arch+'_zifencei2p0';
+          if CPURV_HAS_ZMMUL in cpu_capabilities[current_settings.cputype] then
+            attr_arch:=attr_arch+'_zmmul1p0';
           if CPURV_HAS_ZFA in cpu_capabilities[current_settings.cputype] then
             attr_arch:=attr_arch+'_zfa1p0';
           if CPURV_HAS_ZBA in cpu_capabilities[current_settings.cputype] then

compiler/riscv32/cpuinfo.pas

@@ -225,7 +225,8 @@ Const
        CPURV_HAS_ZDINX,
        CPURV_HAS_ZHINX,
        CPURV_HAS_ZHINXMIN,
-       CPURV_HAS_ZICOND
+       CPURV_HAS_ZICOND,
+       CPURV_HAS_ZMMUL
       );
 
  const

compiler/riscv64/cpuinfo.pas

@@ -143,7 +143,8 @@ Const
        CPURV_HAS_ZDINX,
        CPURV_HAS_ZHINX,
        CPURV_HAS_ZHINXMIN,
-       CPURV_HAS_ZICOND
+       CPURV_HAS_ZICOND,
+       CPURV_HAS_ZMMUL
       );
 
  const

compiler/riscv64/nrv64add.pas

@@ -57,7 +57,7 @@ unit nrv64add;
       begin
         if (nodetype=muln) and
            (left.resultdef.typ=orddef) and (left.resultdef.typ=orddef) and
-           (CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype]) then
+           ([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]<>[]) then
           begin
             result:=nil;
 
@@ -67,7 +67,7 @@ unit nrv64add;
             expectloc:=LOC_REGISTER;
           end
         else if (nodetype=muln) and
-           (not (CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype])) and
+           ([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]=[]) and
            (is_64bit(left.resultdef) or
             is_64bit(right.resultdef)) then
           begin