--- Merging r21510 into '.':

C    compiler/arm/cgcpu.pas
Summary of conflicts:
  Text conflicts: 1

# revisions: 21510
r21510 | florian | 2012-06-06 21:45:26 +0200 (Wed, 06 Jun 2012) | 18 lines
Changed paths:
   M /trunk/compiler/arm/cgcpu.pas

* patch by Nico Erfurth: Support the usage of BIC instead of AND on ARM
BIC clears the specified bits, while AND keeps them. The usage of BIC
allows a broader range of shifterconsts to be used on the ARM cpu, often
saving a cycle.

Previously code like:
Data:=Data and $FFFFFF00

would result in

mvn r1, #255
and r0, r0, r1

This patch changes this to

bic r0, r0, #255

git-svn-id: branches/fixes_2_6@22523 -

compiler/arm/cgcpu.pas

@@ -770,6 +770,20 @@ unit cgcpu;
                 so.shiftimm:=l1;
                 list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,src,src,so));
               end
+            { for example : b=a*7 -> b=a*8-a with rsb instruction and shl }
+            else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a+1,l1) and not(cgsetflags or setflags) then
+              begin
+                if l1>32 then{does this ever happen?}
+                  internalerror(201205181);
+                shifterop_reset(so);
+                so.shiftmode:=SM_LSL;
+                so.shiftimm:=l1;
+                list.concat(taicpu.op_reg_reg_reg_shifterop(A_RSB,dst,src,src,so));
+              end
+            { BIC clears the specified bits, while AND keeps them, using BIC allows to use a
+              broader range of shifterconstants.}
+            else if (op = OP_AND) and is_shifter_const(not(dword(a)),shift) then
+              list.concat(taicpu.op_reg_reg_const(A_BIC,dst,src,not(dword(a))))
             else
               begin
                 tmpreg:=getintregister(list,size);