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@@ -5210,31 +5210,114 @@ unit aoptx86;
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end;
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- if (aoc_MovAnd2Mov_3 in OptsToCheck) and
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- (taicpu(p).oper[1]^.typ = top_reg) and
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- (taicpu(p).opsize = S_L) and
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+ if (taicpu(p).oper[1]^.typ = top_reg) and
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+ (
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+{$ifndef x86_64}
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+ (
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+ { See if we can catch:
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+ mov ###,%ecx (or any of the ecx family)
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+ ...
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+ shl %cl,### (or another shift or rotate instruction)
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+
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+ And change to...
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+ mov ###,%cl (using only %cl)
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+ ...
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+ shl %cl,###
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+ }
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+ (taicpu(p).opsize <> S_B) and
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+ (getsupreg(taicpu(p).oper[1]^.reg) = RS_ECX) and
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+ (
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+ (taicpu(p).oper[0]^.typ <> top_reg) or
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+ (getsupreg(taicpu(p).oper[0]^.reg) in [RS_EAX, RS_EBX, RS_EDX])
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+ )
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+ ) or
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+{$endif not x86_64}
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+ (
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+ { Tends to be a very slow operation that is rarely successful,
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+ so only enable if it's definitely not impossible }
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+ (aoc_MovAnd2Mov_3 in OptsToCheck) and
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+ (taicpu(p).opsize = S_L)
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+ )
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+ ) and
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GetNextInstructionUsingRegTrackingUse(p,hp2,taicpu(p).oper[1]^.reg) and
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- (hp2.typ = ait_instruction) and
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- (taicpu(hp2).opcode = A_AND) and
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- (MatchOpType(taicpu(hp2),top_const,top_reg) or
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- (MatchOpType(taicpu(hp2),top_reg,top_reg) and
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- MatchOperand(taicpu(hp2).oper[0]^,taicpu(hp2).oper[1]^))
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- ) then
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+ (hp2.typ = ait_instruction) then
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begin
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- if SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp2).oper[1]^.reg) then
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+ if (taicpu(hp2).opcode = A_AND) then
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begin
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- if ((taicpu(hp2).oper[0]^.typ=top_const) and (taicpu(hp2).oper[0]^.val = $ffffffff)) or
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- ((taicpu(hp2).oper[0]^.typ=top_reg) and (taicpu(hp2).opsize=S_L)) then
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+ if (MatchOpType(taicpu(hp2),top_const,top_reg) or
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+ (MatchOpType(taicpu(hp2),top_reg,top_reg) and
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+ MatchOperand(taicpu(hp2).oper[0]^,taicpu(hp2).oper[1]^))
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+ ) then
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begin
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- { Optimize out:
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- mov x, %reg
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- and ffffffffh, %reg
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- }
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- DebugMsg(SPeepholeOptimization + 'MovAnd2Mov 3 done',p);
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- RemoveInstruction(hp2);
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- Result:=true;
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- exit;
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+ if SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp2).oper[1]^.reg) then
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+ begin
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+ if ((taicpu(hp2).oper[0]^.typ=top_const) and (taicpu(hp2).oper[0]^.val = $ffffffff)) or
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+ ((taicpu(hp2).oper[0]^.typ=top_reg) and (taicpu(hp2).opsize=S_L)) then
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+ begin
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+ { Optimize out:
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+ mov x, %reg
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+ and ffffffffh, %reg
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+ }
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+ DebugMsg(SPeepholeOptimization + 'MovAnd2Mov 3 done',p);
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+ RemoveInstruction(hp2);
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+ Result:=true;
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+ exit;
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+ end;
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+ end;
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end;
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+{$ifndef x86_64} { This is handled during the code generation stage under x86_64 }
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+ end
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+ else if
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+ { Need to check again in case we entered this block because aoc_MovAnd2Mov_3 was set }
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+ (getsupreg(taicpu(p).oper[1]^.reg) = RS_ECX) and
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+ MatchInstruction(hp2, [A_SHL, A_SHR, A_SHLD, A_SHRD, A_SAR, A_ROR, A_ROL, A_RCR, A_RCL], []) and
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+ (taicpu(hp2).oper[0]^.typ = top_reg) { Will be %cl } and
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+ (
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+ (
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+ (taicpu(hp2).oper[1]^.typ = top_reg) and
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+ (getsupreg(taicpu(hp2).oper[1]^.reg) <> RS_ECX) and
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+ (
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+ (taicpu(hp2).ops = 2) or
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+ (
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+ { For SHLD/SHRD }
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+ (
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+ (taicpu(hp2).oper[2]^.typ = top_reg) and
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+ (getsupreg(taicpu(hp2).oper[2]^.reg) <> RS_ECX)
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+ ) or (
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+ (taicpu(hp2).oper[2]^.typ = top_ref) and
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+ not RegInRef(NR_ECX, taicpu(hp2).oper[2]^.ref^)
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+ )
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+ )
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+ )
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+ ) or (
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+ (taicpu(hp2).oper[1]^.typ = top_ref) and
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+ not RegInRef(NR_ECX, taicpu(hp2).oper[1]^.ref^)
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+ )
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+ ) then
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+ begin
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+ TransferUsedRegs(TmpUsedRegs);
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+ UpdateUsedRegsBetween(TmpUsedRegs, p, hp2);
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+ if not RegUsedAfterInstruction(NR_ECX, hp2, TmpUsedRegs) then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'Resized mov' + debug_opsize2str(taicpu(p).opsize) + ' to 8-bit to match ' + debug_op2str(taicpu(hp2).opcode)+debug_opsize2str(taicpu(hp2).opsize) + ' instruction (MovOp2MovOp 1)', p);
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+
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+ taicpu(p).opsize := S_B;
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+
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+ setsubreg(taicpu(p).oper[1]^.reg, R_SUBL);
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+ case taicpu(p).oper[0]^.typ of
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+ top_reg:
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+ setsubreg(taicpu(p).oper[0]^.reg, R_SUBL);
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+ top_const:
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+ if (taicpu(p).oper[0]^.val < -128) or (taicpu(p).oper[0]^.val > 127) then
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+ taicpu(p).oper[0]^.val := taicpu(p).oper[0]^.val and $FF;
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+ else
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+ { i.e. a reference, which doesn't change };
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+ end;
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+
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+ Result := True;
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+ Exit;
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+ end;
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+{$endif not x86_64}
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end;
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end;
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J. Gareth "Curious Kit" Moreton