+ ARM: started on vfpv5 support

compiler/arm/aasmcpu.pas

@@ -2245,7 +2245,9 @@ implementation
             { fpu_fpv4_s16   } IF_NONE,
             { fpu_vfpv4      } IF_VFPv2 or IF_VFPv3 or IF_VFPv4,
             { fpu_vfpv4      } IF_VFPv2 or IF_VFPv3 or IF_VFPv4,
-            { fpu_neon_vfpv4 } IF_VFPv2 or IF_VFPv3 or IF_VFPv4 or IF_NEON
+            { fpu_neon_vfpv4 } IF_VFPv2 or IF_VFPv3 or IF_VFPv4 or IF_NEON,
+            { fpu_fpv5_d16   } IF_VFPv2 or IF_VFPv3 or IF_VFPv4,
+            { fpu_fpv5_sp_d16} IF_VFPv2 or IF_VFPv3 or IF_VFPv4
           );
       begin
         fArmVMask:=Masks[current_settings.cputype] or FPUMasks[current_settings.fputype];

compiler/arm/agarmgas.pas

@@ -129,6 +129,10 @@ unit agarmgas;
             result:='-mfpu=vfpv4 '+result;
           fpu_neon_vfpv4:
             result:='-mfpu=neon-vfpv4 '+result;
+          fpu_fpv5_sp_d16:
+            result:='-mfpu=fpv5-sp-d16 '+result;
+          fpu_fpv5_d16:
+            result:='-mfpu=fpv5-d16 '+result;
           else
             ;
         end;

compiler/arm/cpuinfo.pas

@@ -74,7 +74,9 @@ Type
       fpu_fpv4_s16,     { same as fpu_fpv4_sp_d32, kept for backwards compatibility }
       fpu_vfpv4,
       fpu_fpv4_sp_d16,  { 32 registers single precision, for load/store/move they can be accessed as 16 double registers }
-      fpu_neon_vfpv4
+      fpu_neon_vfpv4,
+      fpu_fpv5_d16,
+      fpu_fpv5_sp_d16
       { when new elements added afterwards, update
         class procedure tarmnodeutils.InsertObjectInfo; in narmutil.pas }
      );
@@ -93,7 +95,9 @@ Const
     'fpu=vfpv4-s16',
     'fpu=vfpv4',
     'fpu=fpv4-sp-d16',
-    'fpu=neon-vfpv4'
+    'fpu=neon-vfpv4',
+    'fpu=fpv5-sp-d16',
+    'fpu=fpv5-d16'
   );
 
 Type
@@ -586,7 +590,9 @@ Const
      'FPV4_S16',
      'VFPV4',
      'FPV4_SP_D16',
-     'NEON_VFPV4'
+     'NEON_VFPV4',
+     'FPV5_D16',
+     'FPV5_SP_D16'
    );
 
 
@@ -1129,7 +1135,9 @@ Const
          { fpu_fpv4_s16     } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VFP_DOUBLE_MOVLDST,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
          { fpu_vfpv4        } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_DOUBLE,FPUARM_HAS_32REGS,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
          { fpu_fpv4_sp_d16  } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VFP_DOUBLE_MOVLDST,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
-         { fpu_neon_vfpv4   } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_DOUBLE,FPUARM_HAS_32REGS,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_NEON,FPUARM_HAS_FMA]
+         { fpu_neon_vfpv4   } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_DOUBLE,FPUARM_HAS_32REGS,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_NEON,FPUARM_HAS_FMA],
+         { fpu_fpv5_d16     } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VFP_DOUBLE_MOVLDST,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
+         { fpu_fpv5_sp_d16  } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VFP_DOUBLE_MOVLDST,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA]
        );
 
    { contains all CPU supporting any kind of thumb instruction set }

compiler/arm/narmutil.pas

@@ -218,6 +218,9 @@ interface
               fpu_vfpv4,
               fpu_neon_vfpv4:
                 current_asmdata.asmlists[al_start].Concat(tai_eabi_attribute.create(Tag_FP_Arch,5));
+              fpu_fpv5_sp_d16,
+              fpu_fpv5_d16:
+                current_asmdata.asmlists[al_start].Concat(tai_eabi_attribute.create(Tag_FP_Arch,8));
               { else not needed anymore PM 2020/04/13
                 Internalerror(2019100603); }
             end;