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@@ -407,7 +407,7 @@ implementation
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begin
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statement_syssym:=geninlinenode(in_sizeof_x,false,p1);
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{ no packed bit support for these things }
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- if (l = in_bitsizeof_x) then
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+ if l=in_bitsizeof_x then
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statement_syssym:=caddnode.create(muln,statement_syssym,cordconstnode.create(8,sinttype,true));
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end
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else
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