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@@ -1208,19 +1208,17 @@ Implementation
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result:=true;
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list:=TAsmList.Create;
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p := BlockStart;
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- { UsedRegs := []; }
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while (p <> BlockEnd) Do
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begin
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if (p.typ=ait_instruction) and
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GetNextInstruction(p,hp1) and
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(hp1.typ=ait_instruction) and
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+ (taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH]) and
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{ for now we don't reschedule if the previous instruction changes potentially a memory location }
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( (not(taicpu(p).opcode in opcode_could_mem_write) and
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- not(RegModifiedByInstruction(NR_PC,p)) and
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- (taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH])
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+ not(RegModifiedByInstruction(NR_PC,p))
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) or
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((taicpu(p).opcode in [A_STM,A_STRB,A_STRH,A_STR]) and
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- (taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH]) and
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((taicpu(hp1).oper[1]^.ref^.base=NR_PC) or
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(assigned(taicpu(hp1).oper[1]^.ref^.symboldata) and
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(taicpu(hp1).oper[1]^.ref^.offset=0)
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@@ -1228,7 +1226,6 @@ Implementation
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) or
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{ try to prove that the memory accesses don't overlapp }
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((taicpu(p).opcode in [A_STRB,A_STRH,A_STR]) and
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- (taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH]) and
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(taicpu(p).oper[1]^.ref^.base=taicpu(hp1).oper[1]^.ref^.base) and
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(taicpu(p).oppostfix=PF_None) and
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(taicpu(hp1).oppostfix=PF_None) and
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@@ -1300,8 +1297,12 @@ Implementation
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{$endif DEBUG_PREREGSCHEDULER}
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asml.InsertBefore(hp1,hp2);
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asml.InsertListBefore(hp2,list);
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- end;
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- p := tai(p.next)
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+ p := tai(p.next)
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+ end
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+ else if p.typ=ait_instruction then
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+ p:=hp1
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+ else
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+ p := tai(p.next);
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end;
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list.Free;
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end;
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