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@@ -1,7 +1,6 @@
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{******************************************************************************
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Register definitions and startup code for ATMEL ATmega128
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-
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******************************************************************************}
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unit atmega128;
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@@ -9,6 +8,505 @@ unit atmega128;
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{$macro on}
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interface
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+ type
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+ const
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+ _SFR_OFFSET = $20; //indirect addressing
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+ var
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+ PINF : byte absolute $00+_SFR_OFFSET;
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+ PINE : byte absolute $01+_SFR_OFFSET;
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+ DDRE : byte absolute $02+_SFR_OFFSET;
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+ PORTE : byte absolute $03+_SFR_OFFSET;
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+ ADCW : word absolute $04+_SFR_OFFSET;
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+ ADC : word absolute $04+_SFR_OFFSET;
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+ ADCL : byte absolute $04+_SFR_OFFSET;
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+ ADCH : byte absolute $05+_SFR_OFFSET;
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+ ADCSR : byte absolute $06+_SFR_OFFSET;
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+ ADCSRA : byte absolute $06+_SFR_OFFSET;
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+ ADMUX : byte absolute $07+_SFR_OFFSET;
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+ ACSR : byte absolute $08+_SFR_OFFSET;
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+ UBRR0L : byte absolute $09+_SFR_OFFSET;
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+ UCSR0B : byte absolute $0A+_SFR_OFFSET;
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+ UCSR0A : byte absolute $0B+_SFR_OFFSET;
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+ UDR0 : byte absolute $0C+_SFR_OFFSET;
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+ SPCR : byte absolute $0D+_SFR_OFFSET;
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+ SPSR : byte absolute $0E+_SFR_OFFSET;
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+ SPDR : byte absolute $0F+_SFR_OFFSET;
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+ PIND : byte absolute $10+_SFR_OFFSET;
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+ DDRD : byte absolute $11+_SFR_OFFSET;
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+ PORTD : byte absolute $12+_SFR_OFFSET;
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+ PINC : byte absolute $13+_SFR_OFFSET;
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+ DDRC : byte absolute $14+_SFR_OFFSET;
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+ PORTC : byte absolute $15+_SFR_OFFSET;
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+ PINB : byte absolute $16+_SFR_OFFSET;
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+ DDRB : byte absolute $17+_SFR_OFFSET;
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+ PORTB : byte absolute $18+_SFR_OFFSET;
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+ PINA : byte absolute $19+_SFR_OFFSET;
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+ DDRA : byte absolute $1A+_SFR_OFFSET;
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+ PORTA : byte absolute $1B+_SFR_OFFSET;
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+ EECR : byte absolute $1C+_SFR_OFFSET;
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+ EEDR : byte absolute $1D+_SFR_OFFSET;
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+ EEAR : word absolute $1E+_SFR_OFFSET;
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+ EEARL : byte absolute $1E+_SFR_OFFSET;
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+ EEARH : byte absolute $1F+_SFR_OFFSET;
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+ SFIOR : byte absolute $20+_SFR_OFFSET;
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+ WDTCR : byte absolute $21+_SFR_OFFSET;
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+ OCDR : byte absolute $22+_SFR_OFFSET;
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+ OCR2 : byte absolute $23+_SFR_OFFSET;
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+ TCNT2 : byte absolute $24+_SFR_OFFSET;
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+ TCCR2 : byte absolute $25+_SFR_OFFSET;
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+ ICR1 : word absolute $26+_SFR_OFFSET;
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+ ICR1L : byte absolute $26+_SFR_OFFSET;
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+ ICR1H : byte absolute $27+_SFR_OFFSET;
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+ OCR1B : word absolute $28+_SFR_OFFSET;
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+ OCR1BL : byte absolute $28+_SFR_OFFSET;
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+ OCR1BH : byte absolute $29+_SFR_OFFSET;
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+ OCR1A : word absolute $2A+_SFR_OFFSET;
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+ OCR1AL : byte absolute $2A+_SFR_OFFSET;
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+ OCR1AH : byte absolute $2B+_SFR_OFFSET;
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+ TCNT1 : word absolute $2C+_SFR_OFFSET;
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+ TCNT1L : byte absolute $2C+_SFR_OFFSET;
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+ TCNT1H : byte absolute $2D+_SFR_OFFSET;
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+ TCCR1B : byte absolute $2E+_SFR_OFFSET;
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+ TCCR1A : byte absolute $2F+_SFR_OFFSET;
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+ TCCR1B : byte absolute $2E+_SFR_OFFSET;
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+ ASSR : byte absolute $30+_SFR_OFFSET;
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+ OCR0 : byte absolute $31+_SFR_OFFSET;
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+ TCNT0 : byte absolute $32+_SFR_OFFSET;
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+ TCCR0 : byte absolute $33+_SFR_OFFSET;
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+ MCUSR : byte absolute $34+_SFR_OFFSET;
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+ MCUCSR : byte absolute $34+_SFR_OFFSET;
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+ MCUCR : byte absolute $35+_SFR_OFFSET;
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+ TIFR : byte absolute $36+_SFR_OFFSET;
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+ TIMSK : byte absolute $37+_SFR_OFFSET;
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+ EIFR : byte absolute $38+_SFR_OFFSET;
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+ EIMSK : byte absolute $39+_SFR_OFFSET;
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+ EICRB : byte absolute $3A+_SFR_OFFSET;
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+ RAMPZ : byte absolute $3B+_SFR_OFFSET;
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+ XDIV : byte absolute $3C+_SFR_OFFSET;
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+ DDRF : byte absolute $61;
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+ PORTF : byte absolute $62;
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+ PING : byte absolute $63;
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+ DDRG : byte absolute $64;
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+ PORTG : byte absolute $65;
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+ SPMCSR : byte absolute $68;
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+ EICRA : byte absolute $6A;
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+ XMCRB : byte absolute $6C;
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+ XMCRA : byte absolute $6D;
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+ OSCCAL : byte absolute $6F;
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+ TWBR : byte absolute $70;
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+ TWSR : byte absolute $71;
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+ TWAR : byte absolute $72;
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+ TWDR : byte absolute $73;
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+ TWCR : byte absolute $74;
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+ OCR1C : word absolute $78;
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+ OCR1CL : byte absolute $78;
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+ OCR1CH : byte absolute $79;
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+ TCCR1C : byte absolute $7A;
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+ ETIFR : byte absolute $7C;
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+ ETIMSK : byte absolute $7D;
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+ ICR3 : word absolute $80;
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+ ICR3L : byte absolute $80;
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+ ICR3H : byte absolute $81;
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+ OCR3C : word absolute $82;
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+ OCR3CL : byte absolute $82;
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+ OCR3CH : byte absolute $83;
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+ OCR3B : word absolute $84;
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+ OCR3BL : byte absolute $84;
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+ OCR3BH : byte absolute $85;
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+ OCR3A : word absolute $86;
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+ OCR3AL : byte absolute $86;
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+ OCR3AH : byte absolute $87;
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+ TCNT3 : word absolute $88;
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+ TCNT3L : byte absolute $88;
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+ TCNT3H : byte absolute $89;
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+ TCCR3B : byte absolute $8A;
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+ TCCR3A : byte absolute $8B;
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+ TCCR3C : byte absolute $8C;
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+ UBRR0H : byte absolute $90;
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+ UCSR0C : byte absolute $95;
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+ UBRR1H : byte absolute $98;
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+ UBRR1L : byte absolute $99;
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+ UCSR1B : byte absolute $9A;
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+ UCSR1A : byte absolute $9B;
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+ UDR1 : byte absolute $9C;
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+ UCSR1C : byte absolute $9D;
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+ const
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+ TWINT = 7;
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+ TWEA = 6;
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+ TWSTA = 5;
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+ TWSTO = 4;
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+ TWWC = 3;
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+ TWEN = 2;
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+ TWIE = 0;
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+
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+ TWA6 = 7;
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+ TWA5 = 6;
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+ TWA4 = 5;
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+ TWA3 = 4;
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+ TWA2 = 3;
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+ TWA1 = 2;
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+ TWA0 = 1;
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+ TWGCE = 0;
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+
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+ TWS7 = 7;
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+ TWS6 = 6;
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+ TWS5 = 5;
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+ TWS4 = 4;
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+ TWS3 = 3;
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+ TWPS1 = 1;
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+ TWPS0 = 0;
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+
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+ SRL2 = 6;
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+ SRL1 = 5;
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+ SRL0 = 4;
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+ SRW01 = 3;
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+ SRW00 = 2;
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+ SRW11 = 1;
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+
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+ XMBK = 7;
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+ XMM2 = 2;
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+ XMM1 = 1;
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+ XMM0 = 0;
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+
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+ XDIVEN = 7;
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+ XDIV6 = 6;
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+ XDIV5 = 5;
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+ XDIV4 = 4;
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+ XDIV3 = 3;
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+ XDIV2 = 2;
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+ XDIV1 = 1;
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+ XDIV0 = 0;
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+
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+ RAMPZ0 = 0;
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+
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+ ISC31 = 7;
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+ ISC30 = 6;
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+ ISC21 = 5;
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+ ISC20 = 4;
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+ ISC11 = 3;
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+ ISC10 = 2;
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+ ISC01 = 1;
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+ ISC00 = 0;
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+
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+ ISC71 = 7;
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+ ISC70 = 6;
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+ ISC61 = 5;
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+ ISC60 = 4;
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+ ISC51 = 3;
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+ ISC50 = 2;
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+ ISC41 = 1;
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+ ISC40 = 0;
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+
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+ SPMIE = 7;
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+ RWWSB = 6;
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+ RWWSRE = 4;
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+ BLBSET = 3;
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+ PGWRT = 2;
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+ PGERS = 1;
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+ SPMEN = 0;
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+
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+ INT7 = 7;
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+ INT6 = 6;
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+ INT5 = 5;
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+ INT4 = 4;
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+ INT3 = 3;
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+ INT2 = 2;
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+ INT1 = 1;
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+ INT0 = 0;
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+
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+ INTF7 = 7;
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+ INTF6 = 6;
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+ INTF5 = 5;
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+ INTF4 = 4;
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+ INTF3 = 3;
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+ INTF2 = 2;
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+ INTF1 = 1;
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+ INTF0 = 0;
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+
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+ OCIE2 = 7;
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+ TOIE2 = 6;
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+ TICIE1 = 5;
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+ OCIE1A = 4;
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+ OCIE1B = 3;
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+ TOIE1 = 2;
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+ OCIE0 = 1;
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+ TOIE0 = 0;
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+
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+ OCF2 = 7;
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+ TOV2 = 6;
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+ ICF1 = 5;
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+ OCF1A = 4;
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+ OCF1B = 3;
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+ TOV1 = 2;
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+ OCF0 = 1;
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+ TOV0 = 0;
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+
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+ TICIE3 = 5;
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+ OCIE3A = 4;
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+ OCIE3B = 3;
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+ TOIE3 = 2;
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+ OCIE3C = 1;
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+ OCIE1C = 0;
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+
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+ ICF3 = 5;
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+ OCF3A = 4;
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+ OCF3B = 3;
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+ TOV3 = 2;
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+ OCF3C = 1;
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+ OCF1C = 0;
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+
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+ SRE = 7;
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+ SRW = 6;
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+ SRW10 = 6;
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+ SE = 5;
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+ SM1 = 4;
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+ SM0 = 3;
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+ SM2 = 2;
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+ IVSEL = 1;
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+ IVCE = 0;
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+
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+ JTD = 7;
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+ JTRF = 4;
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+ WDRF = 3;
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+ BORF = 2;
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+ EXTRF = 1;
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+ PORF = 0;
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+
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+ FOC = 7;
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+ WGM0 = 6;
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+ COM1 = 5;
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+ COM0 = 4;
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+ WGM1 = 3;
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+ CS2 = 2;
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+ CS1 = 1;
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+ CS0 = 0;
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+
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+ FOC0 = 7;
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+ WGM00 = 6;
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+ COM01 = 5;
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+ COM00 = 4;
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+ WGM01 = 3;
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+ CS02 = 2;
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+ CS01 = 1;
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+ CS00 = 0;
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+
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+ FOC2 = 7;
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+ WGM20 = 6;
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+ COM21 = 5;
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+ COM20 = 4;
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+ WGM21 = 3;
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+ CS22 = 2;
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+ CS21 = 1;
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+ CS20 = 0;
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+
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+ AS0 = 3;
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+ TCN0UB = 2;
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+ OCR0UB = 1;
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+ TCR0UB = 0;
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+
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+ COMA1 = 7;
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+ COMA0 = 6;
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+ COMB1 = 5;
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+ COMB0 = 4;
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+ COMC1 = 3;
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+ COMC0 = 2;
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+ WGMA1 = 1;
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+ WGMA0 = 0;
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+
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+ COM1A1 = 7;
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+ COM1A0 = 6;
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+ COM1B1 = 5;
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+ COM1B0 = 4;
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+ COM1C1 = 3;
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+ COM1C0 = 2;
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+ WGM11 = 1;
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+ WGM10 = 0;
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+
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+ COM3A1 = 7;
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+ COM3A0 = 6;
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+ COM3B1 = 5;
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+ COM3B0 = 4;
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+ COM3C1 = 3;
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+ COM3C0 = 2;
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+ WGM31 = 1;
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+ WGM30 = 0;
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+
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+ ICNC = 7;
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+ ICES = 6;
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+ WGMB3 = 4;
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+ WGMB2 = 3;
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+ CSB2 = 2;
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+ CSB1 = 1;
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+ CSB0 = 0;
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+
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+ ICNC1 = 7;
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+ ICES1 = 6;
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+ WGM13 = 4;
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+ WGM12 = 3;
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+ CS12 = 2;
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+ CS11 = 1;
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+ CS10 = 0;
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+
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+ ICNC3 = 7;
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+ ICES3 = 6;
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+ WGM33 = 4;
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+ WGM32 = 3;
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+ CS32 = 2;
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+ CS31 = 1;
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+ CS30 = 0;
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+
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+ FOCA = 7;
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+ FOCB = 6;
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+ FOCC = 5;
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+
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+ FOC3A = 7;
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+ FOC3B = 6;
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+ FOC3C = 5;
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+
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+ FOC1A = 7;
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+ FOC1B = 6;
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+ FOC1C = 5;
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+
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+ IDRD = 7;
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+ OCDR7 = 7;
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+ OCDR6 = 6;
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+ OCDR5 = 5;
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+ OCDR4 = 4;
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+ OCDR3 = 3;
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+ OCDR2 = 2;
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+ OCDR1 = 1;
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+ OCDR0 = 0;
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+
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+ WDCE = 4;
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+ WDE = 3;
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+ WDP2 = 2;
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+ WDP1 = 1;
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+ WDP0 = 0;
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+
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+ TSM = 7;
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+ ACME = 3;
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+ PUD = 2;
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+ PSR0 = 1;
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+ PSR321 = 0;
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+
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+ SPIF = 7;
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+ WCOL = 6;
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+ SPI2X = 0;
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+
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+ SPIE = 7;
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+ SPE = 6;
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+ DORD = 5;
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+ MSTR = 4;
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+ CPOL = 3;
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+ CPHA = 2;
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+ SPR1 = 1;
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+ SPR0 = 0;
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+
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+ UMSEL = 6;
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+ UPM1 = 5;
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+ UPM0 = 4;
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+ USBS = 3;
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+ UCSZ1 = 2;
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+ UCSZ0 = 1;
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+ UCPOL = 0;
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+
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+ UMSEL1 = 6;
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+ UPM11 = 5;
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+ UPM10 = 4;
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+ USBS1 = 3;
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+ UCSZ11 = 2;
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+ UCSZ10 = 1;
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+ UCPOL1 = 0;
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+
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+ UMSEL0 = 6;
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+ UPM01 = 5;
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+ UPM00 = 4;
|
|
|
+ USBS0 = 3;
|
|
|
+ UCSZ01 = 2;
|
|
|
+ UCSZ00 = 1;
|
|
|
+ UCPOL0 = 0;
|
|
|
+
|
|
|
+ RXC = 7;
|
|
|
+ TXC = 6;
|
|
|
+ UDRE = 5;
|
|
|
+ FE = 4;
|
|
|
+ DOR = 3;
|
|
|
+ UPE = 2;
|
|
|
+ U2X = 1;
|
|
|
+ MPCM = 0;
|
|
|
+
|
|
|
+ RXC1 = 7;
|
|
|
+ TXC1 = 6;
|
|
|
+ UDRE1 = 5;
|
|
|
+ FE1 = 4;
|
|
|
+ DOR1 = 3;
|
|
|
+ UPE1 = 2;
|
|
|
+ U2X1 = 1;
|
|
|
+ MPCM1 = 0;
|
|
|
+
|
|
|
+ RXC0 = 7;
|
|
|
+ TXC0 = 6;
|
|
|
+ UDRE0 = 5;
|
|
|
+ FE0 = 4;
|
|
|
+ DOR0 = 3;
|
|
|
+ UPE0 = 2;
|
|
|
+ U2X0 = 1;
|
|
|
+ MPCM0 = 0;
|
|
|
+
|
|
|
+ RXCIE = 7;
|
|
|
+ TXCIE = 6;
|
|
|
+ UDRIE = 5;
|
|
|
+ RXEN = 4;
|
|
|
+ TXEN = 3;
|
|
|
+ UCSZ = 2;
|
|
|
+ UCSZ2 = 2;
|
|
|
+ RXB8 = 1;
|
|
|
+ TXB8 = 0;
|
|
|
+
|
|
|
+ RXCIE1 = 7;
|
|
|
+ TXCIE1 = 6;
|
|
|
+ UDRIE1 = 5;
|
|
|
+ RXEN1 = 4;
|
|
|
+ TXEN1 = 3;
|
|
|
+ UCSZ12 = 2;
|
|
|
+ RXB81 = 1;
|
|
|
+ TXB81 = 0;
|
|
|
+
|
|
|
+ RXCIE0 = 7;
|
|
|
+ TXCIE0 = 6;
|
|
|
+ UDRIE0 = 5;
|
|
|
+ RXEN0 = 4;
|
|
|
+ TXEN0 = 3;
|
|
|
+ UCSZ02 = 2;
|
|
|
+ RXB80 = 1;
|
|
|
+ TXB80 = 0;
|
|
|
+
|
|
|
+ ACD = 7;
|
|
|
+ ACBG = 6;
|
|
|
+ ACO = 5;
|
|
|
+ ACI = 4;
|
|
|
+ ACIE = 3;
|
|
|
+ ACIC = 2;
|
|
|
+ ACIS1 = 1;
|
|
|
+ ACIS0 = 0;
|
|
|
+
|
|
|
+ ADEN = 7;
|
|
|
+ ADSC = 6;
|
|
|
+ ADFR = 5;
|
|
|
+ ADIF = 4;
|
|
|
+ ADIE = 3;
|
|
|
+ ADPS2 = 2;
|
|
|
+ ADPS1 = 1;
|
|
|
+ ADPS0 = 0;
|
|
|
+
|
|
|
+ REFS1 = 7;
|
|
|
+ REFS0 = 6;
|
|
|
+ ADLAR = 5;
|
|
|
+ MUX4 = 4;
|
|
|
+ MUX3 = 3;
|
|
|
+ MUX2 = 2;
|
|
|
+ MUX1 = 1;
|
|
|
+ MUX0 = 0;
|
|
|
|
|
|
{$define DOCALL:=call}
|
|
|
{$define DOJMP:=jmp}
|
|
|
@@ -32,54 +530,91 @@ unit atmega128;
|
|
|
_bss_end: record end; external name '_bss_end';
|
|
|
_stack_top: record end; external name '_stack_top';
|
|
|
|
|
|
+ Int00Handler,
|
|
|
+ Int01Handler,
|
|
|
+ Int02Handler,
|
|
|
+ Int03Handler,
|
|
|
+ Int04Handler,
|
|
|
+ Int05Handler,
|
|
|
+ Int06Handler,
|
|
|
+ Int07Handler,
|
|
|
+ Int08Handler,
|
|
|
+ Int09Handler,
|
|
|
+ Int10Handler,
|
|
|
+ Int11Handler,
|
|
|
+ Int12Handler,
|
|
|
+ Int13Handler,
|
|
|
+ Int14Handler,
|
|
|
+ Int15Handler,
|
|
|
+ Int16Handler,
|
|
|
+ Int17Handler,
|
|
|
+ Int18Handler,
|
|
|
+ Int19Handler,
|
|
|
+ Int20Handler,
|
|
|
+ Int21Handler,
|
|
|
+ Int22Handler,
|
|
|
+ Int23Handler,
|
|
|
+ Int24Handler,
|
|
|
+ Int25Handler,
|
|
|
+ Int26Handler,
|
|
|
+ Int27Handler,
|
|
|
+ Int28Handler,
|
|
|
+ Int29Handler,
|
|
|
+ Int30Handler,
|
|
|
+ Int31Handler,
|
|
|
+ Int32Handler,
|
|
|
+ Int33Handler,
|
|
|
+ Int34Handler : Pointer = Default_IRQ_handler;
|
|
|
+
|
|
|
+ procedure Default_IRQ_handler; assembler; nostackframe; public name '_Default_IRQ_handler';
|
|
|
+ asm
|
|
|
+ .Lloop:
|
|
|
+ b .Lloop
|
|
|
+ end;
|
|
|
+
|
|
|
procedure _FPC_start; assembler; nostackframe;
|
|
|
label
|
|
|
_start;
|
|
|
asm
|
|
|
- // code derived from phillips appnote 10254
|
|
|
.init
|
|
|
- .align 16
|
|
|
.globl _start
|
|
|
-{ b _start
|
|
|
- b .LUndefined_Addr // Undefined Instruction vector
|
|
|
- b .LSWI_Addr // Software Interrupt vector
|
|
|
- b .LPrefetch_Addr // Prefetch abort vector
|
|
|
- b .LAbort_Addr // Data abort vector
|
|
|
- nop // reserved
|
|
|
- b .LIRQ_Addr // Interrupt Request (IRQ) vector
|
|
|
- b .LFIQ_Addr // Fast interrupt request (FIQ) vector
|
|
|
-
|
|
|
- .LUndefined_Addr:
|
|
|
- ldr r0,.L1
|
|
|
- ldr pc,[r0]
|
|
|
- .LSWI_Addr:
|
|
|
- ldr r0,.L2
|
|
|
- ldr pc,[r0]
|
|
|
- .LPrefetch_Addr:
|
|
|
- ldr r0,.L3
|
|
|
- ldr pc,[r0]
|
|
|
- .LAbort_Addr:
|
|
|
- ldr r0,.L4
|
|
|
- ldr pc,[r0]
|
|
|
- .LIRQ_Addr:
|
|
|
- ldr r0,.L5
|
|
|
- ldr pc,[r0]
|
|
|
- .LFIQ_Addr:
|
|
|
- ldr r0,.L5
|
|
|
- ldr pc,[r0]
|
|
|
- .L1:
|
|
|
- .long Undefined_Handler
|
|
|
- .L2:
|
|
|
- .long SWI_Handler
|
|
|
- .L3:
|
|
|
- .long Prefetch_Handler
|
|
|
- .L4:
|
|
|
- .long Abort_Handler
|
|
|
- .L5:
|
|
|
- .long IRQ_Handler
|
|
|
- .L6:
|
|
|
- .long FIQ_Handler
|
|
|
-}
|
|
|
+// .org 0x00
|
|
|
+ rjmp _start
|
|
|
+ rjump Int00Handler
|
|
|
+ rjump Int01Handler
|
|
|
+ rjump Int02Handler
|
|
|
+ rjump Int03Handler
|
|
|
+ rjump Int04Handler
|
|
|
+ rjump Int05Handler
|
|
|
+ rjump Int06Handler
|
|
|
+ rjump Int07Handler
|
|
|
+ rjump Int08Handler
|
|
|
+ rjump Int09Handler
|
|
|
+ rjump Int10Handler
|
|
|
+ rjump Int11Handler
|
|
|
+ rjump Int12Handler
|
|
|
+ rjump Int13Handler
|
|
|
+ rjump Int14Handler
|
|
|
+ rjump Int15Handler
|
|
|
+ rjump Int16Handler
|
|
|
+ rjump Int17Handler
|
|
|
+ rjump Int18Handler
|
|
|
+ rjump Int19Handler
|
|
|
+ rjump Int20Handler
|
|
|
+ rjump Int21Handler
|
|
|
+ rjump Int22Handler
|
|
|
+ rjump Int23Handler
|
|
|
+ rjump Int24Handler
|
|
|
+ rjump Int25Handler
|
|
|
+ rjump Int26Handler
|
|
|
+ rjump Int27Handler
|
|
|
+ rjump Int28Handler
|
|
|
+ rjump Int29Handler
|
|
|
+ rjump Int30Handler
|
|
|
+ rjump Int31Handler
|
|
|
+ rjump Int32Handler
|
|
|
+ rjump Int33Handler
|
|
|
+ rjump Int34Handler
|
|
|
{
|
|
|
all ATMEL MCUs use the same startup code, the details are
|
|
|
governed by defines
|
|
|
@@ -88,3 +623,4 @@ unit atmega128;
|
|
|
end;
|
|
|
|
|
|
end.
|
|
|
+
|
florian