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@@ -0,0 +1,394 @@
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+unit at91sam7x256;
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+
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+{$goto on}
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+
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+ interface
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+
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+ type
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+ AT91_REG = DWord;
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+ TBitvector32 = bitpacked array[0..31] of 0..1;
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+
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+ const
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+ // (CKGR)
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+ AT91C_CKGR_DIV = dword($000000FF); // Divider Selected
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+ AT91C_CKGR_MOSCEN = dword($00000001); // Main Oscillator Enable
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+ AT91C_CKGR_MUL = dword($07FF0000); // PLL Multiplier
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+ AT91C_CKGR_OSCOUNT = dword($0000FF00); // Main Oscillator Start-up Time
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+ AT91C_CKGR_OUT_0 = dword($00000000); // Please refer to the PLL datasheet
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+ AT91C_CKGR_PLLCOUNT = dword($00003F00); // PLL Counter
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+
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+ AT91C_MC_FMCN = dword($00FF0000); // (MC) Flash Microsecond Cycle Number
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+ AT91C_MC_FWS_1FWS = dword($00000100);
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+
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+ AT91C_WDTC_WDDIS = dword($00008000);
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+
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+ type
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+ TAT91C_Low_Lewel_Settings = record
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+ osc_div_factor:byte;
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+ osc_mul_factor:word;
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+ end;
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+
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+ var
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+ AIC_SMR : array[0..31] of AT91_REG absolute $FFFFF000; // Source Mode Register
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+ AIC_SVR : array[0..31] of AT91_REG absolute $FFFFF020; // Source Vector Register
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+ AIC_IVR : AT91_REG absolute $FFFFF040; // IRQ Vector Register
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+ AIC_FVR : AT91_REG absolute $FFFFF044; // FIQ Vector Register
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+ AIC_ISR : AT91_REG absolute $FFFFF048; // Interrupt Status Register
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+ AIC_IPR : AT91_REG absolute $FFFFF04C; // Interrupt Pending Register
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+ AIC_IMR : AT91_REG absolute $FFFFF050; // Interrupt Mask Register
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+ AIC_CISR : AT91_REG absolute $FFFFF054; // Core Interrupt Status Register }
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+ // Reserved0 : array[0..1] of AT91_REG;
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+ AIC_IECR : AT91_REG absolute $FFFFF060; // Interrupt Enable Command Register
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+ AIC_IDCR : AT91_REG absolute $FFFFF064; // Interrupt Disable Command Register
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+ AIC_ICCR : AT91_REG absolute $FFFFF068; // Interrupt Clear Command Register
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+ AIC_ISCR : AT91_REG absolute $FFFFF06C; // Interrupt Set Command Register
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+ AIC_EOICR : AT91_REG absolute $FFFFF070; // End of Interrupt Command Register
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+ AIC_SPU : AT91_REG absolute $FFFFF074; // Spurious Vector Register
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+ AIC_DCR : AT91_REG absolute $FFFFF078; // Debug Control Register (Protect) }
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+ // Reserved1 : array[0..0] of AT91_REG;
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+
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+ // ========== Register definition for PIOA peripheral ==========
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+ AT91C_PIOA_IMR : DWord absolute $FFFFF448; // Interrupt Mask Register
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+ AT91C_PIOA_IER : DWord absolute $FFFFF440; // Interrupt Enable Register
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+ AT91C_PIOA_OWDR : DWord absolute $FFFFF4A4; // Output Write Disable Register
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+ AT91C_PIOA_ISR : DWord absolute $FFFFF44C; // Interrupt Status Register
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+ AT91C_PIOA_PPUDR : DWord absolute $FFFFF460; // Pull-up Disable Register
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+ AT91C_PIOA_MDSR : DWord absolute $FFFFF458; // Multi-driver Status Register
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+ AT91C_PIOA_MDER : DWord absolute $FFFFF450; // Multi-driver Enable Register
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+ AT91C_PIOA_PER : DWord absolute $FFFFF400; // PIO Enable Register
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+ AT91C_PIOA_PSR : DWord absolute $FFFFF408; // PIO Status Register
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+ AT91C_PIOA_OER : DWord absolute $FFFFF410; // Output Enable Register
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+ AT91C_PIOA_BSR : DWord absolute $FFFFF474; // Select B Register
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+ AT91C_PIOA_PPUER : DWord absolute $FFFFF464; // Pull-up Enable Register
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+ AT91C_PIOA_MDDR : DWord absolute $FFFFF454; // Multi-driver Disable Register
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+ AT91C_PIOA_PDR : DWord absolute $FFFFF404; // PIO Disable Register
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+ AT91C_PIOA_ODR : DWord absolute $FFFFF414; // Output Disable Registerr
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+ AT91C_PIOA_IFDR : DWord absolute $FFFFF424; // Input Filter Disable Register
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+ AT91C_PIOA_ABSR : DWord absolute $FFFFF478; // AB Select Status Register
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+ AT91C_PIOA_ASR : DWord absolute $FFFFF470; // Select A Register
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+ AT91C_PIOA_PPUSR : DWord absolute $FFFFF468; // Pull-up Status Register
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+ AT91C_PIOA_ODSR : DWord absolute $FFFFF438; // Output Data Status Register
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+ AT91C_PIOA_SODR : DWord absolute $FFFFF430; // Set Output Data Register
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+ AT91C_PIOA_IFSR : DWord absolute $FFFFF428; // Input Filter Status Register
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+ AT91C_PIOA_IFER : DWord absolute $FFFFF420; // Input Filter Enable Register
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+ AT91C_PIOA_OSR : DWord absolute $FFFFF418; // Output Status Register
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+ AT91C_PIOA_IDR : DWord absolute $FFFFF444; // Interrupt Disable Register
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+ AT91C_PIOA_PDSR : DWord absolute $FFFFF43C; // Pin Data Status Register
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+ AT91C_PIOA_CODR : DWord absolute $FFFFF434; // Clear Output Data Register
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+ AT91C_PIOA_OWSR : DWord absolute $FFFFF4A8; // Output Write Status Register
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+ AT91C_PIOA_OWER : DWord absolute $FFFFF4A0; // Output Write Enable Register
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+ // ========== Register definition for CKGR peripheral ==========
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+ AT91C_CKGR_PLLR : DWord absolute $FFFFFC2C; // PLL Register
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+ AT91C_CKGR_MCFR : DWord absolute $FFFFFC24; // Main Clock Frequency Register
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+ AT91C_CKGR_MOR : DWord absolute $FFFFFC20; // Main Oscillator Register
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+ // ========== Register definition for PMC peripheral ==========
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+ AT91C_PMC_SCSR : DWord absolute $FFFFFC08; // System Clock Status Register
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+ AT91C_PMC_SCER : DWord absolute $FFFFFC00; // System Clock Enable Register
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+ AT91C_PMC_IMR : DWord absolute $FFFFFC6C; // Interrupt Mask Register
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+ AT91C_PMC_IDR : DWord absolute $FFFFFC64; // Interrupt Disable Register
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+ AT91C_PMC_PCDR : DWord absolute $FFFFFC14; // Peripheral Clock Disable Register
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+ AT91C_PMC_SCDR : DWord absolute $FFFFFC04; // System Clock Disable Register
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+ AT91C_PMC_SR : DWord absolute $FFFFFC68; // Status Register
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+ AT91C_PMC_IER : DWord absolute $FFFFFC60; // Interrupt Enable Register
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+ AT91C_PMC_MCKR : DWord absolute $FFFFFC30; // Master Clock Register
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+ AT91C_PMC_MOR : DWord absolute $FFFFFC20; // Main Oscillator Register
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+ AT91C_PMC_PCER : DWord absolute $FFFFFC10; // Peripheral Clock Enable Register
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+ AT91C_PMC_PCSR : DWord absolute $FFFFFC18; // Peripheral Clock Status Register
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+ AT91C_PMC_PLLR : DWord absolute $FFFFFC2C; // PLL Register
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+ AT91C_PMC_MCFR : DWord absolute $FFFFFC24; // Main Clock Frequency Register
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+ AT91C_PMC_PCKR : DWord absolute $FFFFFC40; // Programmable Clock Register
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+
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+ const
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+ AT91C_PMC_CSS_PLL_CLK = dword($3); // (PMC) Clock from PLL is selected
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+ AT91C_PMC_PRES_CLK_2 = dword($1) shl 2; // (PMC) Selected clock divided by 2
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+ AT91C_PMC_MOSCS = dword($1) shl 0; // (PMC) MOSC Status/Enable/Disable/Mask
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+ AT91C_PMC_LOCK = dword($1) shl 2; // (PMC) PLL Status/Enable/Disable/Mask
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+ AT91C_PMC_MCKRDY = dword($1) shl 3; // (PMC) MCK_RDY Status/Enable/Disable/Mask
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+
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+ var
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+ // ========== Register definition for RSTC peripheral ==========
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+ AT91C_RSTC_RSR : DWord absolute $FFFFFD04; // Reset Status Register
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+ AT91C_RSTC_RMR : DWord absolute $FFFFFD08; // Reset Mode Register
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+ AT91C_RSTC_RCR : DWord absolute $FFFFFD00; // Reset Control Register
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+
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+ // ========== Register definition for WDTC peripheral ==========
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+ AT91C_WDTC_WDMR : DWord absolute $FFFFFD44; // Watchdog Mode Register
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+ AT91C_WDTC_WDSR : DWord absolute $FFFFFD48; // Watchdog Status Register
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+ AT91C_WDTC_WDCR : DWord absolute $FFFFFD40; // Watchdog Control Register
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+ // ========== Register definition for VREG peripheral ==========
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+ AT91C_VREG_MR : DWord absolute $FFFFFD60; // Voltage Regulator Mode Register
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+ // ========== Register definition for MC peripheral ==========
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+ AT91C_MC_FCR : DWord absolute $FFFFFF64; // MC Flash Command Register
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+ AT91C_MC_ASR : DWord absolute $FFFFFF04; // MC Abort Status Register
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+ AT91C_MC_FSR : DWord absolute $FFFFFF68; // MC Flash Status Register
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+ AT91C_MC_FMR : DWord absolute $FFFFFF60; // MC Flash Mode Register
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+ AT91C_MC_AASR : DWord absolute $FFFFFF08; // MC Abort Address Status Register
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+ AT91C_MC_RCR : DWord absolute $FFFFFF00; // MC Remap Control Register
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+
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+
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+ // *****************************************************************************
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+ // BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
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+ // *****************************************************************************
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+ AT91C_BASE_SYS : DWord absolute $FFFFF000; // (SYS) Base Address
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+ AT91C_BASE_AIC : DWord absolute $FFFFF000; // (AIC) Base Address
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+ AT91C_BASE_PIOA : DWord absolute $FFFFF400; // (PIOA) Base Address
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+ AT91C_BASE_CKGR : DWord absolute $FFFFFC20; // (CKGR) Base Address
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+ AT91C_BASE_PMC : DWord absolute $FFFFFC00; // (PMC) Base Address
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+ AT91C_BASE_WDTC : DWord absolute $FFFFFD40; // (WDTC) Base Address
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+ AT91C_BASE_VREG : DWord absolute $FFFFFD60; // (VREG) Base Address
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+ AT91C_BASE_MC : DWord absolute $FFFFFF00; // (MC) Base Address
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+
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+ procedure lowlevelinit(LowLewelValues:TAT91C_Low_Lewel_Settings);
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+
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+ var
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+ Undefined_Handler,
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+ SWI_Handler,
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+ Prefetch_Handler,
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+ Abort_Handler,
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+ IRQ_Handler,
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+ FIQ_Handler : pointer;
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+
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+ implementation
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+
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+
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+ procedure AT91F_Default_FIQ_handler; assembler; nostackframe; public name 'AT91F_Default_FIQ_handler';
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+ asm
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+ .Lloop:
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+ b .Lloop
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+ end;
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+
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+
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+ procedure AT91F_Default_IRQ_handler; assembler; nostackframe; public name 'AT91F_Default_IRQ_handler';
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+ asm
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+ .Lloop:
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+ b .Lloop
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+ end;
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+
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+
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+ procedure AT91F_Spurious_handler; assembler; nostackframe; public name 'AT91F_Spurious_handler';
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+ asm
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+ .Lloop:
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+ b .Lloop
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+ end;
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+
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+
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+ { Basic hardware initialization
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+
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+ Note: see page 5 - 6 of Atmel's
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+ "Getting Started with AT91SAM7X Microcontrollers" for details.}
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+ procedure lowlevelinit(LowLewelValues:TAT91C_Low_Lewel_Settings);
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+ var
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+ i : Longint;
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+ begin
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+ { Set Flash Wait state (AT91C_MC_FMR = MC Flash Mode Register)}
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+ AT91C_MC_FMR := ((AT91C_MC_FMCN) and (50*$10000)) or AT91C_MC_FWS_1FWS;
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+
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+ { Watchdog Disable (AT91C_WDTC_WDMR = Watchdog Mode Register)}
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+ AT91C_WDTC_WDMR := AT91C_WDTC_WDDIS;
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+
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+ {Enable the Main Oscillator (AT91C_PMC_MOR = Main Oscillator Register)}
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+ AT91C_PMC_MOR := (( AT91C_CKGR_OSCOUNT and ($0800) or AT91C_CKGR_MOSCEN ));
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+
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+ { Wait the startup time (until PMC Status register MOSCEN bit is set)
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+ result: $FFFFFC68 bit 0 will set when main oscillator has stabilized}
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+ while (AT91C_PMC_SR and AT91C_PMC_MOSCS)=0 do
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+ ;
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+
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+
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+ { PMC Clock Generator PLL Register setup }
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+ AT91C_PMC_PLLR :=((AT91C_CKGR_OUT_0) or
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+ (AT91C_CKGR_DIV and LowLewelValues.osc_div_factor) or
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+ (AT91C_CKGR_PLLCOUNT and (40 shl 10)) or
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+ (AT91C_CKGR_MUL and (LowLewelValues.osc_mul_factor shl 16)));
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+
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+ { Wait the startup time (until PMC Status register LOCK bit is set)
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+ result: 0xFFFFFC68 bit 2 will set when PLL has locked }
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+ while (AT91C_PMC_SR and AT91C_PMC_LOCK)=0 do
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+ ;
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+
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+
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+ { PMC Master Clock Register setup (AT91C_PMC_MCKR = Master Clock Register)}
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+ AT91C_PMC_MCKR := AT91C_PMC_PRES_CLK_2;
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+
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+ { Wait the startup time (until PMC Status register MCKRDY bit is set)
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+ result: $FFFFFC68 bit 3 will set when Master Clock has stabilized }
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+
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+ while (AT91C_PMC_SR and AT91C_PMC_MCKRDY)=0 do
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+ ;
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+
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+ {(AT91C_PMC_MCKR = Master Clock Register) }
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+ AT91C_PMC_MCKR := AT91C_PMC_MCKR or AT91C_PMC_CSS_PLL_CLK;
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+
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+ { Wait the startup time (until PMC Status register MCKRDY bit is set)
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+ result: $FFFFFC68 bit 3 will set when Master Clock has stabilized }
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+ while (AT91C_PMC_SR and AT91C_PMC_MCKRDY)=0 do
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+ ;
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+
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+ { Set up the default interrupts handler vectors }
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+ AIC_SVR[0]:=AT91_REG(@AT91F_Default_FIQ_handler);
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+
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+ for i:=1 to 30 do
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+ AIC_SVR[i]:=AT91_REG(@AT91F_Default_IRQ_handler);
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+
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+ AIC_SPU:=AT91_REG(@AT91F_Spurious_handler);
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+ end;
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+
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+
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+ procedure PASCALMAIN; external name 'PASCALMAIN';
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+
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+ procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
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+ asm
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+ .Lhalt:
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+ b .Lhalt
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+ end;
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+
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+ var
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+ _data: record end; external name '_data';
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+ _edata: record end; external name '_edata';
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+ _etext: record end; external name '_etext';
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+ _bss_start: record end; external name '_bss_start';
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+ _bss_end: record end; external name '_bss_end';
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+ _stack_top: record end; external name '_stack_top';
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+
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+ procedure _FPC_start; assembler; nostackframe;
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+ label
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+ _start;
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+ asm
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+ .init
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+ .align 16
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+ .globl _start
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+ b _start
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+ b .LUndefined_Addr // Undefined Instruction vector
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+ b .LSWI_Addr // Software Interrupt vector
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+ b .LPrefetch_Addr // Prefetch abort vector
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+ b .LAbort_Addr // Data abort vector
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+ nop // reserved
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+ b .LIRQ_Addr // Interrupt Request (IRQ) vector
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+ b .LFIQ_Addr // Fast interrupt request (FIQ) vector
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+
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+ .LUndefined_Addr:
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+ ldr r0,.L1
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+ ldr pc,[r0]
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+ .LSWI_Addr:
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+ ldr r0,.L2
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+ ldr pc,[r0]
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+ .LPrefetch_Addr:
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+ ldr r0,.L3
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+ ldr pc,[r0]
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+ .LAbort_Addr:
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+ ldr r0,.L4
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+ ldr pc,[r0]
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+ .LIRQ_Addr:
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+ ldr r0,.L5
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+ ldr pc,[r0]
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+ .LFIQ_Addr:
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+ ldr r0,.L5
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+ ldr pc,[r0]
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+
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+ .L1:
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+ .long Undefined_Handler
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+ .L2:
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+ .long SWI_Handler
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+ .L3:
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+ .long Prefetch_Handler
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+ .L4:
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+ .long Abort_Handler
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+ .L5:
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+ .long IRQ_Handler
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+ .L6:
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+ .long FIQ_Handler
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+
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+ _start:
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+ (*
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+ Set absolute stack top
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+
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+ stack is already set by bootloader
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+ but if this point is entered by any
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+ other means than reset, the stack pointer
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+ needs to be set explicity
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+ *)
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+ ldr r0,.L_stack_top
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+
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+ (*
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+ Setting up SP for IRQ and FIQ mode.
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+ Change mode before setting each one
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+ move back again to Supervisor mode
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+ Each interrupt has its own link
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+ register, stack pointer and program
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+ counter The stack pointers must be
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+ initialized for interrupts to be
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+ used later.
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+ *)
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+
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+ (*
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+ setup irq and fiq stacks each 128 bytes
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+ *)
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+ msr cpsr_c, #0x12 // switch to irq mode
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+ mov sp, r0 // set irq stack pointer
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+ sub r0,r0,#128 // irq stack size
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+ msr cpsr_c, #0x11 // fiq mode
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+ mov sp, r0 // set fiq stack pointer
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+ sub r0,r0,#128 // fiq stack size
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+ msr cpsr_c, #0x13 // supervisor mode F,I enabled
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+ mov sp, r0 // stack
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+
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+ // for now, all handlers are set to a default one
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+ ldr r1,.LDefaultHandlerAddr
|
|
|
+ ldr r0,.L1
|
|
|
+ str r1,[r0]
|
|
|
+ ldr r0,.L2
|
|
|
+ str r1,[r0]
|
|
|
+ ldr r0,.L3
|
|
|
+ str r1,[r0]
|
|
|
+ ldr r0,.L4
|
|
|
+ str r1,[r0]
|
|
|
+ ldr r0,.L5
|
|
|
+ str r1,[r0]
|
|
|
+ ldr r0,.L6
|
|
|
+ str r1,[r0]
|
|
|
+
|
|
|
+ // copy initialized data from flash to ram
|
|
|
+ ldr r1,.L_etext
|
|
|
+ ldr r2,.L_data
|
|
|
+ ldr r3,.L_edata
|
|
|
+.Lcopyloop:
|
|
|
+ cmp r2,r3
|
|
|
+ ldrls r0,[r1],#4
|
|
|
+ strls r0,[r2],#4
|
|
|
+ bls .Lcopyloop
|
|
|
+
|
|
|
+ // clear onboard ram
|
|
|
+ ldr r1,.L_bss_start
|
|
|
+ ldr r2,.L_bss_end
|
|
|
+ mov r0,#0
|
|
|
+.Lzeroloop:
|
|
|
+ cmp r1,r2
|
|
|
+ strls r0,[r1],#4
|
|
|
+ bls .Lzeroloop
|
|
|
+
|
|
|
+ bl PASCALMAIN
|
|
|
+ bl _FPC_haltproc
|
|
|
+.L_bss_start:
|
|
|
+ .long _bss_start
|
|
|
+.L_bss_end:
|
|
|
+ .long _bss_end
|
|
|
+.L_etext:
|
|
|
+ .long _etext
|
|
|
+.L_data:
|
|
|
+ .long _data
|
|
|
+.L_edata:
|
|
|
+ .long _edata
|
|
|
+.L_stack_top:
|
|
|
+ .long _stack_top
|
|
|
+.LDefaultHandlerAddr:
|
|
|
+ .long .LDefaultHandler
|
|
|
+ // default irq handler just returns
|
|
|
+.LDefaultHandler:
|
|
|
+ mov pc,r14
|
|
|
+ .text
|
|
|
+ end;
|
|
|
+
|
|
|
+end.
|
|
|
+
|
|
|
+end.
|
|
|
+
|
florian