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@@ -53,6 +53,8 @@ unit cgcpu;
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procedure a_load_reg_ref(list : TAsmList;fromsize,tosize : tcgsize;register : tregister;const ref : treference);override;
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procedure a_load_reg_reg(list : TAsmList;fromsize,tosize : tcgsize;reg1,reg2 : tregister);override;
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procedure a_load_ref_reg(list : TAsmList;fromsize,tosize : tcgsize;const ref : treference;register : tregister);override;
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+ procedure a_load_ref_ref(list : TAsmList;fromsize,tosize : tcgsize;const sref : treference;const dref : treference);override;
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+
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procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
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procedure a_loadfpu_reg_reg(list: TAsmList; size: tcgsize; reg1, reg2: tregister); override;
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procedure a_loadfpu_ref_reg(list: TAsmList; size: tcgsize; const ref: treference; reg: tregister); override;
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@@ -231,22 +233,28 @@ unit cgcpu;
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procedure tcg68k.a_param_reg(list : TAsmList;size : tcgsize;r : tregister;const cgpara : tcgpara);
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var
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pushsize : tcgsize;
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+ ref : treference;
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begin
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writeln('a_param_reg');
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- {
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- check_register_size(size,r);
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- if use_push(cgpara) then
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+
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+ { it's probably necessary to port this from x86 later, or provide an m68k solution (KB) }
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+{$WARNING FIX ME! check_register_size()}
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+ // check_register_size(size,r);
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+ { remove "not" to trigger the location bug (KB) }
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+ if not use_push(cgpara) then
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begin
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cgpara.check_simple_location;
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if tcgsize2size[cgpara.location^.size]>cgpara.alignment then
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pushsize:=cgpara.location^.size
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else
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pushsize:=int_cgsize(cgpara.alignment);
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- list.concat(taicpu.op_reg(A_PUSH,tcgsize2opsize[pushsize],makeregsize(list,r,pushsize)));
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+
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+ reference_reset_base(ref, NR_STACK_POINTER_REG, 0);
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+ ref.direction := dir_dec;
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+ list.concat(taicpu.op_reg_ref(A_MOVE,tcgsize2opsize[pushsize],makeregsize(list,r,pushsize),ref));
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end
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else
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- }
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-// inherited a_param_reg(list,size,r,cgpara);
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+ inherited a_param_reg(list,size,r,cgpara);
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end;
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@@ -276,19 +284,22 @@ unit cgcpu;
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procedure tcg68k.a_param_ref(list : TAsmList;size : tcgsize;const r : treference;const cgpara : tcgpara);
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-(*
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+
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procedure pushdata(paraloc:pcgparalocation;ofs:aint);
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var
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pushsize : tcgsize;
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tmpreg : tregister;
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href : treference;
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+ ref : treference;
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begin
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if not assigned(paraloc) then
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exit;
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- if (paraloc^.loc<>LOC_REFERENCE) or
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+{$WARNING FIX ME!!! this also triggers location bug }
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+ {if (paraloc^.loc<>LOC_REFERENCE) or
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(paraloc^.reference.index<>NR_STACK_POINTER_REG) or
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(tcgsize2size[paraloc^.size]>sizeof(aint)) then
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- internalerror(200501162);
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+ internalerror(200501162);}
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+
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{ Pushes are needed in reverse order, add the size of the
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current location to the offset where to load from. This
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prevents wrong calculations for the last location when
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@@ -302,24 +313,29 @@ unit cgcpu;
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pushsize:=paraloc^.size
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else
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pushsize:=int_cgsize(cgpara.alignment);
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+
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+ reference_reset_base(ref, NR_STACK_POINTER_REG, 0);
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+ ref.direction := dir_dec;
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+
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if tcgsize2size[paraloc^.size]<cgpara.alignment then
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begin
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tmpreg:=getintregister(list,pushsize);
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a_load_ref_reg(list,paraloc^.size,pushsize,href,tmpreg);
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- list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize],tmpreg));
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+ list.concat(taicpu.op_reg_ref(A_MOVE,tcgsize2opsize[pushsize],tmpreg,ref));
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end
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else
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- list.concat(taicpu.op_ref(A_PUSH,TCgsize2opsize[pushsize],href));
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+ list.concat(taicpu.op_ref_ref(A_MOVE,tcgsize2opsize[pushsize],href,ref));
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end;
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-*)
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+
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var
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len : aint;
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href : treference;
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begin
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writeln('a_param_ref');
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- {
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+
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{ cgpara.size=OS_NO requires a copy on the stack }
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- if use_push(cgpara) then
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+ { remove "not" to trigger the location bug (KB) }
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+ if not use_push(cgpara) then
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begin
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{ Record copy? }
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if (cgpara.size in [OS_NO,OS_F64]) or (size=OS_NO) then
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@@ -340,7 +356,6 @@ unit cgcpu;
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end
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end
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else
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- }
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inherited a_param_ref(list,size,r,cgpara);
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end;
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@@ -353,36 +368,35 @@ unit cgcpu;
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writeln('a_paramaddr_ref');
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with r do
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begin
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- {
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- if (segment<>NR_NO) then
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- cgmessage(cg_e_cant_use_far_pointer_there);
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- if use_push(cgpara) then
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+ { i suppose this is not required for m68k (KB) }
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+// if (segment<>NR_NO) then
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+// cgmessage(cg_e_cant_use_far_pointer_there);
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+ if not use_push(cgpara) then
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begin
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cgpara.check_simple_location;
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opsize:=tcgsize2opsize[OS_ADDR];
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if (segment=NR_NO) and (base=NR_NO) and (index=NR_NO) then
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begin
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if assigned(symbol) then
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- list.concat(Taicpu.Op_sym_ofs(A_PUSH,opsize,symbol,offset))
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- else
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- list.concat(Taicpu.Op_const(A_PUSH,opsize,offset));
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+// list.concat(Taicpu.Op_sym_ofs(A_PUSH,opsize,symbol,offset))
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+ else;
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+// list.concat(Taicpu.Op_const(A_PUSH,opsize,offset));
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end
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else if (segment=NR_NO) and (base=NR_NO) and (index<>NR_NO) and
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(offset=0) and (scalefactor=0) and (symbol=nil) then
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- list.concat(Taicpu.Op_reg(A_PUSH,opsize,index))
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+// list.concat(Taicpu.Op_reg(A_PUSH,opsize,index))
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else if (segment=NR_NO) and (base<>NR_NO) and (index=NR_NO) and
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(offset=0) and (symbol=nil) then
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- list.concat(Taicpu.Op_reg(A_PUSH,opsize,base))
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+// list.concat(Taicpu.Op_reg(A_PUSH,opsize,base))
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else
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begin
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tmpreg:=getaddressregister(list);
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a_loadaddr_ref_reg(list,r,tmpreg);
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- list.concat(taicpu.op_reg(A_PUSH,opsize,tmpreg));
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+// list.concat(taicpu.op_reg(A_PUSH,opsize,tmpreg));
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end;
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end
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else
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- }
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-// inherited a_paramaddr_ref(list,r,cgpara);
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+ inherited a_paramaddr_ref(list,r,cgpara);
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end;
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end;
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@@ -483,6 +497,20 @@ unit cgcpu;
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{ move to destination reference }
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list.concat(taicpu.op_reg_ref(A_MOVE,TCGSize2OpSize[fromsize],register,href));
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end;
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+
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+
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+ procedure tcg68k.a_load_ref_ref(list : TAsmList;fromsize,tosize : tcgsize;const sref : treference;const dref : treference);
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+ var
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+ aref: treference;
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+ bref: treference;
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+ begin
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+ aref := sref;
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+ bref := dref;
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+ fixref(list,aref);
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+ fixref(list,bref);
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+ writeln('a_load_ref_ref');
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+ list.concat(taicpu.op_ref_ref(A_MOVE,TCGSize2OpSize[fromsize],aref,bref));
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+ end;
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procedure tcg68k.a_load_reg_reg(list : TAsmList;fromsize,tosize : tcgsize;reg1,reg2 : tregister);
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