* Moved x86_64 mod/div code to x86, with minimal changes to ensure it compiles on i386/i8086. Merging optimized division-by-const code from i386 is pending...

git-svn-id: trunk@27930 -

compiler/x86/nx86mat.pas

@@ -44,11 +44,15 @@ interface
 {$endif SUPPORT_MMX}
       end;
 
+      tx86moddivnode = class(tcgmoddivnode)
+         procedure pass_generate_code;override;
+      end;
+
   implementation
 
     uses
       globtype,
-      systems,
+      systems,constexp,
       cutils,verbose,globals,
       symconst,symdef,
       aasmbase,aasmtai,aasmdata,defutil,
@@ -360,4 +364,114 @@ interface
       emit_reg_reg(A_PXOR,S_NO,hreg,location.register);
     end;
 {$endif SUPPORT_MMX}
+
+
+{*****************************************************************************
+                             TX86MODDIVNODE
+*****************************************************************************}
+
+    procedure tx86moddivnode.pass_generate_code;
+      var
+        hreg1,hreg2,rega,regd:Tregister;
+        power:longint;
+        op:Tasmop;
+        cgsize:TCgSize;
+        opsize:topsize;
+      begin
+        secondpass(left);
+        if codegenerror then
+          exit;
+        secondpass(right);
+        if codegenerror then
+          exit;
+
+        { put numerator in register }
+        cgsize:=def_cgsize(resultdef);
+        opsize:=TCGSize2OpSize[cgsize];
+        if not (cgsize in [OS_32,OS_S32,OS_64,OS_S64]) then
+          InternalError(2013102702);
+        rega:=newreg(R_INTREGISTER,RS_EAX,cgsize2subreg(R_INTREGISTER,cgsize));
+        regd:=newreg(R_INTREGISTER,RS_EDX,cgsize2subreg(R_INTREGISTER,cgsize));
+
+        location_reset(location,LOC_REGISTER,cgsize);
+        hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
+        hreg1:=left.location.register;
+
+        if (nodetype=divn) and (right.nodetype=ordconstn) and
+           ispowerof2(int64(tordconstnode(right).value),power) then
+          begin
+            { for signed numbers, the numerator must be adjusted before the
+              shift instruction, but not wih unsigned numbers! Otherwise,
+              "Cardinal($ffffffff) div 16" overflows! (JM) }
+            if is_signed(left.resultdef) Then
+              begin
+                  { use a sequence without jumps, saw this in
+                    comp.compilers (JM) }
+                  { no jumps, but more operations }
+                  hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
+                  emit_reg_reg(A_MOV,opsize,hreg1,hreg2);
+                  {If the left value is signed, hreg2=$ffffffff, otherwise 0.}
+                  emit_const_reg(A_SAR,opsize,63,hreg2);
+                  {If signed, hreg2=right value-1, otherwise 0.}
+                  { (don't use emit_const_reg, because if value>high(longint)
+                     then it must first be loaded into a register) }
+                  cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,cgsize,tordconstnode(right).value-1,hreg2);
+                  { add to the left value }
+                  emit_reg_reg(A_ADD,opsize,hreg2,hreg1);
+                  { do the shift }
+                  emit_const_reg(A_SAR,opsize,power,hreg1);
+              end
+            else
+              emit_const_reg(A_SHR,opsize,power,hreg1);
+            location.register:=hreg1;
+          end
+        else
+          begin
+            {Bring denominator to a register.}
+            cg.getcpuregister(current_asmdata.CurrAsmList,rega);
+            emit_reg_reg(A_MOV,opsize,hreg1,rega);
+            cg.getcpuregister(current_asmdata.CurrAsmList,regd);
+            {Sign extension depends on the left type.}
+            if is_signed(left.resultdef) then
+              case left.resultdef.size of
+{$ifdef x86_64}
+                8:
+                  emit_none(A_CQO,S_NO);
+{$endif x86_64}
+                4:
+                  emit_none(A_CDQ,S_NO);
+                else
+                  internalerror(2013102701);
+              end
+            else
+              emit_reg_reg(A_XOR,opsize,regd,regd);
+
+            {Division depends on the right type.}
+            if is_signed(right.resultdef) then
+              op:=A_IDIV
+            else
+              op:=A_DIV;
+
+            if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
+              emit_ref(op,opsize,right.location.reference)
+            else if right.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
+              emit_reg(op,opsize,right.location.register)
+            else
+              begin
+                hreg1:=cg.getintregister(current_asmdata.CurrAsmList,right.location.size);
+                hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,right.resultdef,right.location,hreg1);
+                emit_reg(op,opsize,hreg1);
+              end;
+
+            { Copy the result into a new register. Release R/EAX & R/EDX.}
+            cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
+            cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
+            location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
+            if nodetype=divn then
+              cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,rega,location.register)
+            else
+              cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register);
+          end;
+      end;
+
 end.

compiler/x86_64/nx64mat.pas

@@ -29,10 +29,6 @@ interface
       node,nmat,ncgmat,nx86mat;
 
     type
-      tx8664moddivnode = class(tmoddivnode)
-         procedure pass_generate_code;override;
-      end;
-
       tx8664shlshrnode = class(tshlshrnode)
          procedure pass_generate_code;override;
       end;
@@ -55,122 +51,6 @@ implementation
       cgbase,cgutils,cga,cgobj,hlcgobj,cgx86,
       ncgutil;
 
-{*****************************************************************************
-                             TX8664MODDIVNODE
-*****************************************************************************}
-
-    procedure tx8664moddivnode.pass_generate_code;
-      var
-        hreg1,hreg2,rega,regd:Tregister;
-        power:longint;
-        op:Tasmop;
-        cgsize:TCgSize;
-        opsize:topsize;
-      begin
-        secondpass(left);
-        if codegenerror then
-          exit;
-        secondpass(right);
-        if codegenerror then
-          exit;
-
-        { put numerator in register }
-        cgsize:=def_cgsize(resultdef);
-        opsize:=TCGSize2OpSize[cgsize];
-        case cgsize of
-          OS_S64,OS_64:
-            begin
-              rega:=NR_RAX;
-              regd:=NR_RDX;
-            end;
-          OS_S32,OS_32:
-            begin
-              rega:=NR_EAX;
-              regd:=NR_EDX;
-            end;
-          else
-            internalerror(2013102702);
-        end;
-
-        location_reset(location,LOC_REGISTER,cgsize);
-        hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
-        hreg1:=left.location.register;
-
-        if (nodetype=divn) and (right.nodetype=ordconstn) and
-           ispowerof2(int64(tordconstnode(right).value),power) then
-          begin
-            { for signed numbers, the numerator must be adjusted before the
-              shift instruction, but not wih unsigned numbers! Otherwise,
-              "Cardinal($ffffffff) div 16" overflows! (JM) }
-            if is_signed(left.resultdef) Then
-              begin
-                  { use a sequence without jumps, saw this in
-                    comp.compilers (JM) }
-                  { no jumps, but more operations }
-                  hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
-                  emit_reg_reg(A_MOV,opsize,hreg1,hreg2);
-                  {If the left value is signed, hreg2=$ffffffff, otherwise 0.}
-                  emit_const_reg(A_SAR,opsize,63,hreg2);
-                  {If signed, hreg2=right value-1, otherwise 0.}
-                  { (don't use emit_const_reg, because if value>high(longint)
-                     then it must first be loaded into a register) }
-                  cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,cgsize,tordconstnode(right).value-1,hreg2);
-                  { add to the left value }
-                  emit_reg_reg(A_ADD,opsize,hreg2,hreg1);
-                  { do the shift }
-                  emit_const_reg(A_SAR,opsize,power,hreg1);
-              end
-            else
-              emit_const_reg(A_SHR,opsize,power,hreg1);
-            location.register:=hreg1;
-          end
-        else
-          begin
-            {Bring denominator to a register.}
-            cg.getcpuregister(current_asmdata.CurrAsmList,rega);
-            emit_reg_reg(A_MOV,opsize,hreg1,rega);
-            cg.getcpuregister(current_asmdata.CurrAsmList,regd);
-            {Sign extension depends on the left type.}
-            if is_signed(left.resultdef) then
-              case left.resultdef.size of
-                8:
-                  emit_none(A_CQO,S_NO);
-                4:
-                  emit_none(A_CDQ,S_NO);
-                else
-                  internalerror(2013102701);
-              end
-            else
-              emit_reg_reg(A_XOR,opsize,regd,regd);
-
-            {Division depends on the right type.}
-            if is_signed(right.resultdef) then
-              op:=A_IDIV
-            else
-              op:=A_DIV;
-
-            if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
-              emit_ref(op,opsize,right.location.reference)
-            else if right.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
-              emit_reg(op,opsize,right.location.register)
-            else
-              begin
-                hreg1:=cg.getintregister(current_asmdata.CurrAsmList,right.location.size);
-                hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,right.resultdef,right.location,hreg1);
-                emit_reg(op,opsize,hreg1);
-              end;
-
-            { Copy the result into a new register. Release R/EAX & R/EDX.}
-            cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
-            cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
-            location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
-            if nodetype=divn then
-              cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,rega,location.register)
-            else
-              cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register);
-          end;
-      end;
-
 
 {*****************************************************************************
                              TX8664SHLRSHRNODE
@@ -241,7 +121,7 @@ implementation
 
 begin
    cunaryminusnode:=tx8664unaryminusnode;
-   cmoddivnode:=tx8664moddivnode;
+   cmoddivnode:=tx86moddivnode;
    cshlshrnode:=tx8664shlshrnode;
    cnotnode:=tx8664notnode;
 end.