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@@ -164,6 +164,7 @@ unit aoptx86;
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function DoArithCombineOpt(var p : tai) : Boolean;
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function DoMovCmpMemOpt(var p : tai; const hp1: tai) : Boolean;
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function DoSETccLblRETOpt(var p: tai; const hp_label: tai_label) : Boolean;
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+ function HandleSHRMerge(var p: tai; const PostPeephole: Boolean): Boolean;
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function PrePeepholeOptSxx(var p : tai) : boolean;
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function PrePeepholeOptIMUL(var p : tai) : boolean;
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@@ -7732,19 +7733,18 @@ unit aoptx86;
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end;
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end;
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- function TX86AsmOptimizer.OptPass1SHR(var p : tai) : boolean;
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+
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+ function TX86AsmOptimizer.HandleSHRMerge(var p: tai; const PostPeephole: Boolean): Boolean;
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var
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hp1, hp2: tai;
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- Shift: TCGInt;
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+ IdentityMask, Shift: TCGInt;
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LimitSize: Topsize;
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DoNotMerge: Boolean;
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begin
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- Result := False;
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-
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- { All these optimisations work on "shr const,%reg" }
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- if not MatchOpType(taicpu(p), top_const, top_reg) then
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- Exit;
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+ if not MatchInstruction(p, A_SHR, []) then
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+ InternalError(2025040301);
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+ Result := False;
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DoNotMerge := False;
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Shift := taicpu(p).oper[0]^.val;
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LimitSize := taicpu(p).opsize;
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@@ -7755,7 +7755,77 @@ unit aoptx86;
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Exit;
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case taicpu(hp1).opcode of
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- A_TEST, A_CMP, A_Jcc:
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+ A_AND:
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+ { Detect:
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+ shr x, %reg
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+ and y, %reg
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+
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+ If and y, %reg doesn't actually change the value of %reg (e.g. with
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+ "shrl $24,%reg; andl $255,%reg", remove the AND instruction.
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+
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+ (Post-peephole only)
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+ }
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+ if PostPeephole and
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+ (taicpu(hp1).opsize = taicpu(p).opsize) and
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+ MatchOpType(taicpu(hp1), top_const, top_reg) and
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+ (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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+ begin
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+ { Make sure the FLAGS register isn't in use }
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+ TransferUsedRegs(TmpUsedRegs);
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+ hp2 := p;
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+ repeat
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+ UpdateUsedRegs(TmpUsedRegs, tai(hp2.Next));
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+ until not GetNextInstruction(hp2, hp2) or (hp2 = hp1);
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+
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+ if not RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs) then
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+ begin
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+ { Generate the identity mask }
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+ case taicpu(p).opsize of
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+ S_B:
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+ IdentityMask := $FF shr Shift;
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+ S_W:
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+ IdentityMask := $FFFF shr Shift;
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+ S_L:
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+ IdentityMask := $FFFFFFFF shr Shift;
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+{$ifdef x86_64}
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+ S_Q:
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+ { We need to force the operands to be unsigned 64-bit
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+ integers otherwise the wrong value is generated }
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+ IdentityMask := TCGInt(QWord($FFFFFFFFFFFFFFFF) shr QWord(Shift));
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+{$endif x86_64}
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+ else
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+ InternalError(2022081501);
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+ end;
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+
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+ if (taicpu(hp1).oper[0]^.val and IdentityMask) = IdentityMask then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'Removed AND instruction since previous SHR makes this an identity operation (ShrAnd2Shr)', hp1);
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+ { All the possible 1 bits are covered, so we can remove the AND }
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+ hp2 := tai(hp1.Previous);
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+ RemoveInstruction(hp1);
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+
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+ { p wasn't actually changed, so don't set Result to True,
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+ but a change was nonetheless made elsewhere }
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+ Include(OptsToCheck, aoc_ForceNewIteration);
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+
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+ { Do another pass in case other AND or MOVZX instructions
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+ follow }
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+ hp1 := hp2;
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+ Continue;
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+ end;
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+
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+ end;
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+ end;
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+
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+ A_TEST, A_CMP:
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+ { Skip over relevant comparisons, but shift instructions must
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+ now not be merged since the original value is being read }
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+ begin
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+ DoNotMerge := True;
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+ Continue;
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+ end;
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+
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+ A_Jcc:
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{ Skip over conditional jumps and relevant comparisons }
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Continue;
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@@ -7769,7 +7839,21 @@ unit aoptx86;
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if IsShrMovZFoldable(taicpu(p).opsize, taicpu(hp1).opsize, Shift) then
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begin
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- if not SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg) then { Different register target }
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+ if SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg) then
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+ begin
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+ { If the MOVZX instruction reads and writes the same register,
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+ defer this to the post-peephole optimisation stage }
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+ if PostPeephole then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'Removed MOVZX instruction since previous SHR makes it unnecessary (ShrMovz2Shr)', hp1);
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+ { All the possible 1 bits are covered, so we can remove the MOVZX }
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+ hp2 := tai(hp1.Previous);
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+ RemoveInstruction(hp1);
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+
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+ hp1 := hp2;
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+ end;
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+ end
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+ else { Different register target }
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begin
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DebugMsg(SPeepholeOptimization + 'Converted MOVZX instruction to MOV since previous SHR makes zero-extension unnecessary (ShrMovz2ShrMov 1)', hp1);
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taicpu(hp1).opcode := A_MOV;
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@@ -7791,10 +7875,49 @@ unit aoptx86;
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Continue;
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end;
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- { NOTE: If the MOVZX instruction reads and writes the same
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- register, defer this to the post-peephole optimisation stage }
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Exit;
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+ end
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+ else if PostPeephole and
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+ (Shift > 0) and
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+ (taicpu(p).opsize = S_W) and
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+ (taicpu(hp1).opsize = S_WL) and
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+ (taicpu(hp1).oper[0]^.reg = NR_AX) and
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+ (taicpu(hp1).oper[1]^.reg = NR_EAX) then
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+ begin
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+ { Detect:
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+ shr x, %ax (x > 0)
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+ ...
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+ movzwl %ax,%eax
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+-
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+ Change movzwl %ax,%eax to cwtl (shorter encoding for movswl %ax,%eax)
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+
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+ But first, check to see if movzwl %ax,%eax can be removed...
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+ }
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+ hp2 := tai(hp1.Previous);
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+
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+ TransferUsedRegs(TmpUsedRegs);
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+ UpdateUsedRegsBetween(UsedRegs, p, hp1);
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+
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+ if PostPeepholeOptMovZX(hp1) then
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+ hp1 := hp2
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+ else
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'Converted movzwl %ax,%eax to cwtl (via ShrMovz2ShrCwtl)', hp1);
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+ taicpu(hp1).opcode := A_CWDE;
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+ taicpu(hp1).clearop(0);
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+ taicpu(hp1).clearop(1);
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+ taicpu(hp1).ops := 0;
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+ end;
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+
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+ RestoreUsedRegs(TmpUsedRegs);
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+ { Don't need to set aoc_ForceNewIteration if
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+ PostPeepholeOptMovZX returned True because it's the
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+ post-peephole stage }
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+
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end;
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+
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+ { Move onto the next instruction }
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+ Continue;
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end;
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A_SHL, A_SAL, A_SHR:
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if (taicpu(hp1).opsize <= LimitSize) and
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@@ -7842,11 +7965,36 @@ unit aoptx86;
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;
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end;
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+ { If the register isn't actually modified, move onto the next instruction,
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+ but set DoNotMerge to True since the register is being read }
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+ if (
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+ { Under -O2 and below, GetNextInstructionUsingReg only returns
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+ the next instruction, whether or not it contains the register }
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+ (cs_opt_level3 in current_settings.optimizerswitches) or
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+ RegReadByInstruction(taicpu(p).oper[1]^.reg, hp1)
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+ ) and not RegModifiedByInstruction(taicpu(p).oper[1]^.reg, hp1) then
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+ begin
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+ DoNotMerge := True;
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+ Continue;
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+ end;
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+
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Break;
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until False;
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end;
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+ function TX86AsmOptimizer.OptPass1SHR(var p : tai) : boolean;
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+ begin
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+ Result := False;
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+
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+ { All these optimisations work on "shr const,%reg" }
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+ if not MatchOpType(taicpu(p), top_const, top_reg) then
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+ Exit;
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+
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+ Result := HandleSHRMerge(p, False);
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+ end;
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+
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+
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function TX86AsmOptimizer.CheckMemoryWrite(var first_mov, second_mov: taicpu): Boolean;
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var
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CurrentRef: TReference;
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@@ -16576,10 +16724,7 @@ unit aoptx86;
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function TX86AsmOptimizer.PostPeepholeOptShr(var p : tai) : boolean;
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var
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- hp1, hp2: tai;
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- IdentityMask, Shift: TCGInt;
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- LimitSize: Topsize;
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- DoNotMerge: Boolean;
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+ hp1: tai;
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begin
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Result := False;
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@@ -16587,193 +16732,12 @@ unit aoptx86;
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if not MatchOpType(taicpu(p), top_const, top_reg) then
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Exit;
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- DoNotMerge := False;
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- Shift := taicpu(p).oper[0]^.val;
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- LimitSize := taicpu(p).opsize;
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-
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- hp1 := p;
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- repeat
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- if not GetNextInstructionUsingReg(hp1, hp1, taicpu(p).oper[1]^.reg) or (hp1.typ <> ait_instruction) then
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- Break;
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-
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- { Detect:
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- shr x, %reg
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- and y, %reg
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-
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- If and y, %reg doesn't actually change the value of %reg (e.g. with
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- "shrl $24,%reg; andl $255,%reg", remove the AND instruction.
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- }
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-
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- case taicpu(hp1).opcode of
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- A_AND:
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- if (taicpu(hp1).opsize = taicpu(p).opsize) and
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- MatchOpType(taicpu(hp1), top_const, top_reg) and
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- (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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- begin
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- { Make sure the FLAGS register isn't in use }
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- TransferUsedRegs(TmpUsedRegs);
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- hp2 := p;
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- repeat
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- UpdateUsedRegs(TmpUsedRegs, tai(hp2.Next));
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- until not GetNextInstruction(hp2, hp2) or (hp2 = hp1);
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-
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- if not RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs) then
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- begin
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- { Generate the identity mask }
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- case taicpu(p).opsize of
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- S_B:
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- IdentityMask := $FF shr Shift;
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- S_W:
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- IdentityMask := $FFFF shr Shift;
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- S_L:
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- IdentityMask := $FFFFFFFF shr Shift;
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-{$ifdef x86_64}
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- S_Q:
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- { We need to force the operands to be unsigned 64-bit
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- integers otherwise the wrong value is generated }
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- IdentityMask := TCGInt(QWord($FFFFFFFFFFFFFFFF) shr QWord(Shift));
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-{$endif x86_64}
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- else
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- InternalError(2022081501);
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- end;
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-
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- if (taicpu(hp1).oper[0]^.val and IdentityMask) = IdentityMask then
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- begin
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- DebugMsg(SPeepholeOptimization + 'Removed AND instruction since previous SHR makes this an identity operation (ShrAnd2Shr)', hp1);
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- { All the possible 1 bits are covered, so we can remove the AND }
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- hp2 := tai(hp1.Previous);
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- RemoveInstruction(hp1);
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-
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- { p wasn't actually changed, so don't set Result to True,
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- but a change was nonetheless made elsewhere }
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- Include(OptsToCheck, aoc_ForceNewIteration);
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-
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- { Do another pass in case other AND or MOVZX instructions
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- follow }
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- hp1 := hp2;
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- Continue;
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- end;
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-
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- end;
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- end;
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-
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- A_TEST, A_CMP, A_Jcc:
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- { Skip over conditional jumps and relevant comparisons }
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- Continue;
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-
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- A_MOVZX:
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- if MatchOpType(taicpu(hp1), top_reg, top_reg) and
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- SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(p).oper[1]^.reg) then
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- begin
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- { Since the original register is being read as is, subsequent
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- SHRs must not be merged at this point }
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- DoNotMerge := True;
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-
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- if IsShrMovZFoldable(taicpu(p).opsize, taicpu(hp1).opsize, Shift) then
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- begin
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- if SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg) then
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- begin
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- DebugMsg(SPeepholeOptimization + 'Removed MOVZX instruction since previous SHR makes it unnecessary (ShrMovz2Shr)', hp1);
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- { All the possible 1 bits are covered, so we can remove the AND }
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- hp2 := tai(hp1.Previous);
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- RemoveInstruction(hp1);
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-
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- hp1 := hp2;
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- end
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- else { Different register target }
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- begin
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- DebugMsg(SPeepholeOptimization + 'Converted MOVZX instruction to MOV since previous SHR makes zero-extension unnecessary (ShrMovz2ShrMov 2)', hp1);
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- taicpu(hp1).opcode := A_MOV;
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- setsubreg(taicpu(hp1).oper[0]^.reg, getsubreg(taicpu(hp1).oper[1]^.reg));
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- case taicpu(hp1).opsize of
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- S_BW:
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- taicpu(hp1).opsize := S_W;
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- S_BL, S_WL:
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- taicpu(hp1).opsize := S_L;
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- else
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- InternalError(2022081503);
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- end;
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- end;
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- end
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- else if (Shift > 0) and
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- (taicpu(p).opsize = S_W) and
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- (taicpu(hp1).opsize = S_WL) and
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- (taicpu(hp1).oper[0]^.reg = NR_AX) and
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- (taicpu(hp1).oper[1]^.reg = NR_EAX) then
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- begin
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- { Detect:
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- shr x, %ax (x > 0)
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- ...
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- movzwl %ax,%eax
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-
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- Change movzwl %ax,%eax to cwtl (shorter encoding for movswl %ax,%eax)
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- }
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- DebugMsg(SPeepholeOptimization + 'Converted movzwl %ax,%eax to cwtl (via ShrMovz2ShrCwtl)', hp1);
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- taicpu(hp1).opcode := A_CWDE;
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- taicpu(hp1).clearop(0);
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- taicpu(hp1).clearop(1);
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- taicpu(hp1).ops := 0;
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- end;
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-
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- { Move onto the next instruction }
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- Continue;
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- end;
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-
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- A_SHL, A_SAL, A_SHR:
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- if (taicpu(hp1).opsize <= LimitSize) and
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- MatchOpType(taicpu(hp1), top_const, top_reg) and
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- SuperRegistersEqual(taicpu(hp1).oper[1]^.reg, taicpu(p).oper[1]^.reg) then
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- begin
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- { Make sure the sizes don't exceed the register size limit
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- (measured by the shift value falling below the limit) }
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-
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- if taicpu(hp1).opsize < LimitSize then
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- LimitSize := taicpu(hp1).opsize;
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-
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- if taicpu(hp1).opcode = A_SHR then
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- Inc(Shift, taicpu(hp1).oper[0]^.val)
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- else
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- begin
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- Dec(Shift, taicpu(hp1).oper[0]^.val);
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- DoNotMerge := True;
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- end;
|
|
|
-
|
|
|
- if Shift < topsize2memsize[taicpu(p).opsize] - topsize2memsize[LimitSize] then
|
|
|
- Break;
|
|
|
-
|
|
|
- { Since we've established that the combined shift is within
|
|
|
- limits, we can actually combine the adjacent SHR
|
|
|
- instructions even if they're different sizes }
|
|
|
- if not DoNotMerge and (taicpu(hp1).opcode = A_SHR) then
|
|
|
- begin
|
|
|
- hp2 := tai(hp1.Previous);
|
|
|
- DebugMsg(SPeepholeOptimization + 'ShrShr2Shr 2', p);
|
|
|
- Inc(taicpu(p).oper[0]^.val, taicpu(hp1).oper[0]^.val);
|
|
|
- RemoveInstruction(hp1);
|
|
|
- hp1 := hp2;
|
|
|
- end;
|
|
|
-
|
|
|
- { Move onto the next instruction }
|
|
|
- Continue;
|
|
|
- end;
|
|
|
- else
|
|
|
- { If the register isn't actually modified, move onto the next instruction,
|
|
|
- but set DoNotMerge to True since the register is being read }
|
|
|
- if (
|
|
|
- { Under -O2 and below, GetNextInstructionUsingReg only returns
|
|
|
- the next instruction, whether or not it contains the register }
|
|
|
- (cs_opt_level3 in current_settings.optimizerswitches) or
|
|
|
- RegReadByInstruction(taicpu(p).oper[1]^.reg, hp1)
|
|
|
- ) and not RegModifiedByInstruction(taicpu(p).oper[1]^.reg, hp1) then
|
|
|
- begin
|
|
|
- DoNotMerge := True;
|
|
|
- Continue;
|
|
|
- end;
|
|
|
+ if HandleSHRMerge(p, True) then
|
|
|
+ begin
|
|
|
+ Result := True;
|
|
|
+ Exit;
|
|
|
end;
|
|
|
|
|
|
- Break;
|
|
|
- until False;
|
|
|
-
|
|
|
{ Detect the following (looking backwards):
|
|
|
shr %cl,%reg
|
|
|
shr x, %reg
|
J. Gareth "Curious Kit" Moreton