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@@ -129,7 +129,7 @@ type
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function fixref(list: taasmoutput; var ref: treference; const size : TCgsize): boolean;
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function load_got_symbol(list : taasmoutput; symbol : string) : tregister;
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-
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+
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{ returns whether a reference can be used immediately in a powerpc }
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{ instruction }
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function issimpleref(const ref: treference): boolean;
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@@ -143,7 +143,7 @@ type
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procedure a_jmp(list: taasmoutput; op: tasmop;
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c: tasmcondflag; crval: longint; l: tasmlabel);
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- { returns the lowest numbered FP register in use, and the number of used FP registers
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+ { returns the lowest numbered FP register in use, and the number of used FP registers
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for the current procedure }
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procedure calcFirstUsedFPR(out firstfpr : TSuperRegister; out fprcount : aint);
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{ returns the lowest numbered GP register in use, and the number of used GP registers
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@@ -158,9 +158,9 @@ type
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control code generation. If prependDot is true, a single dot character is prepended to
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the string, if addNOP is true a single NOP instruction is added after the call, and
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if includeCall is true, the method is marked as having a call, not if false. This
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- option is particularly useful to prevent generation of a larger stack frame for the
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+ option is particularly useful to prevent generation of a larger stack frame for the
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register save and restore helper functions. }
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- procedure a_call_name_direct(list: taasmoutput; s: string; prependDot : boolean;
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+ procedure a_call_name_direct(list: taasmoutput; s: string; prependDot : boolean;
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addNOP : boolean; includeCall : boolean = true);
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{ emits code to store the given value a into the TOC (if not already in there), and load it from there
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@@ -192,10 +192,10 @@ begin
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end;
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-{ helper function which calculate "magic" values for replacement of unsigned
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+{ helper function which calculate "magic" values for replacement of unsigned
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division by constant operation by multiplication. See the PowerPC compiler
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developer manual for more information }
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-procedure getmagic_unsignedN(const N : byte; const d : aWord;
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+procedure getmagic_unsignedN(const N : byte; const d : aWord;
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out magic_m : aWord; out magic_add : boolean; out magic_shift : byte);
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var
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p : aInt;
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@@ -204,7 +204,7 @@ begin
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assert(d > 0);
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two_N_minus_1 := aWord(1) shl (N-1);
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-
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+
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magic_add := false;
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nc := - 1 - (-d) mod d;
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p := N-1; { initialize p }
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@@ -227,7 +227,7 @@ begin
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q2 := 2*q2 + 1; { update q2 }
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r2 := 2*r2 + 1 - d; { update r2 }
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end else begin
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- if (q2 >= two_N_minus_1) then
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+ if (q2 >= two_N_minus_1) then
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magic_add := true;
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q2 := 2*q2; { update q2 }
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r2 := 2*r2 + 1; { update r2 }
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@@ -238,16 +238,16 @@ begin
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magic_shift := p - N; { resulting shift }
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end;
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-{ helper function which calculate "magic" values for replacement of signed
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+{ helper function which calculate "magic" values for replacement of signed
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division by constant operation by multiplication. See the PowerPC compiler
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developer manual for more information }
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-procedure getmagic_signedN(const N : byte; const d : aInt;
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+procedure getmagic_signedN(const N : byte; const d : aInt;
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out magic_m : aInt; out magic_s : aInt);
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var
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p : aInt;
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ad, anc, delta, q1, r1, q2, r2, t : aWord;
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two_N_minus_1 : aWord;
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-
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+
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begin
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assert((d < -1) or (d > 1));
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@@ -261,7 +261,7 @@ begin
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r1 := two_N_minus_1 - q1*anc; { initialize r1 = rem(2p,abs(nc)) }
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q2 := two_N_minus_1 div ad; { initialize q2 = 2p/abs(d) }
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r2 := two_N_minus_1 - q2*ad; { initialize r2 = rem(2p,abs(d)) }
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- repeat
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+ repeat
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inc(p);
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q1 := 2*q1; { update q1 = 2p/abs(nc) }
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r1 := 2*r1; { update r1 = rem(2p/abs(nc)) }
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@@ -293,7 +293,7 @@ var
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hl : aInt;
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begin
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neg := false;
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- { also try to find negative power of two's by negating if the
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+ { also try to find negative power of two's by negating if the
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value is negative. low(aInt) is special because it can not be
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negated. Simply return the appropriate values for it }
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if (value < 0) then begin
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@@ -327,7 +327,7 @@ end;
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function getInstructionLength(a : aint) : longint;
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function get32bitlength(a : longint; var length : longint) : boolean; inline;
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- var
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+ var
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is_half_signed : byte;
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begin
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{ if the lower 16 bits are zero, do a single LIS }
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@@ -355,8 +355,8 @@ begin
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extendssign := get32bitlength(lo(a), result);
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if (extendssign) and (hi(a) = 0) then
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inc(result)
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- else if (not
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- ((extendssign and (longint(hi(a)) = -1)) or
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+ else if (not
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+ ((extendssign and (longint(hi(a)) = -1)) or
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((not extendssign) and (hi(a)=0)))
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) then begin
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get32bitlength(hi(a), result);
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@@ -439,17 +439,17 @@ begin
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list.concat(tai_comment.create(strpnew('a_param_ref with OS_NO, sizeleft ' + inttostr(sizeleft))));
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{$ENDIF extdebug}
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- { load non-integral sized memory location into register. This
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+ { load non-integral sized memory location into register. This
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memory location be 1-sizeleft byte sized.
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Always assume that this memory area is properly aligned, eg. start
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loading the larger quantities for "odd" quantities first }
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case sizeleft of
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1,2,4,8 :
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a_load_ref_reg(list, int_cgsize(sizeleft), location^.size, tmpref,
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- location^.register);
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+ location^.register);
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3 : begin
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- a_reg_alloc(list, NR_R12);
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- a_load_ref_reg(list, OS_16, location^.size, tmpref,
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+ a_reg_alloc(list, NR_R12);
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+ a_load_ref_reg(list, OS_16, location^.size, tmpref,
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NR_R12);
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inc(tmpref.offset, tcgsize2size[OS_16]);
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a_load_ref_reg(list, OS_8, location^.size, tmpref,
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@@ -470,7 +470,7 @@ begin
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a_load_ref_reg(list, OS_32, location^.size, tmpref, NR_R12);
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inc(tmpref.offset, tcgsize2size[OS_32]);
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a_load_ref_reg(list, OS_16, location^.size, tmpref, location^.register);
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- list.concat(taicpu.op_reg_reg_const_const(A_RLDIMI, location^.register, NR_R12, 16, 16));
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+ list.concat(taicpu.op_reg_reg_const_const(A_RLDIMI, location^.register, NR_R12, 16, 16));
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a_reg_dealloc(list, NR_R12);
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end;
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7 : begin
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@@ -493,10 +493,10 @@ begin
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{ the block is > 8 bytes, so we have to store any bytes not
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a multiple of the register size beginning with the MSB }
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adjusttail := true;
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- end;
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+ end;
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if (adjusttail) and (sizeleft < tcgsize2size[OS_INT]) then
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- a_op_const_reg(list, OP_SHL, OS_INT,
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- (tcgsize2size[OS_INT] - sizeleft) * tcgsize2size[OS_INT],
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+ a_op_const_reg(list, OP_SHL, OS_INT,
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+ (tcgsize2size[OS_INT] - sizeleft) * tcgsize2size[OS_INT],
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location^.register);
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end;
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@@ -515,7 +515,7 @@ begin
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else
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internalerror(2002072801);
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end;
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- LOC_VOID:
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+ LOC_VOID:
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{ nothing to do }
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;
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else
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@@ -579,7 +579,7 @@ procedure tcgppc.a_call_reg(list: taasmoutput; reg: tregister);
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var
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tmpref: treference;
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begin
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- if (not (cs_littlesize in aktglobalswitches)) then begin
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+ if (not (cs_opt_size in aktoptimizerswitches)) then begin
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{ load actual function entry (reg contains the reference to the function descriptor)
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into R0 }
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reference_reset_base(tmpref, reg, 0);
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@@ -627,7 +627,7 @@ procedure tcgppc.a_load_const_reg(list: taasmoutput; size: TCGSize; a: aint;
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sign extension was performed) }
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function load32bitconstant(list : taasmoutput; size : TCGSize; a : longint;
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reg : TRegister) : boolean;
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- var
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+ var
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is_half_signed : byte;
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begin
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{ if the lower 16 bits are zero, do a single LIS }
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@@ -673,21 +673,21 @@ procedure tcgppc.a_load_const_reg(list: taasmoutput; size: TCGSize; a: aint;
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if (lo(a) = 0) and (hi(a) <> 0) then begin
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{ load only upper 32 bits, and shift }
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load32bitconstant(list, size, hi(a), reg);
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- list.concat(taicpu.op_reg_reg_const(A_SLDI, reg, reg, 32));
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+ list.concat(taicpu.op_reg_reg_const(A_SLDI, reg, reg, 32));
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end else begin
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{ load lower 32 bits }
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extendssign := load32bitconstant(list, size, lo(a), reg);
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if (extendssign) and (hi(a) = 0) then
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- { if upper 32 bits are zero, but loading the lower 32 bit resulted in automatic
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+ { if upper 32 bits are zero, but loading the lower 32 bit resulted in automatic
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sign extension, clear those bits }
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a_load_reg_reg(list, OS_32, OS_64, reg, reg)
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- else if (not
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- ((extendssign and (longint(hi(a)) = -1)) or
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+ else if (not
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+ ((extendssign and (longint(hi(a)) = -1)) or
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((not extendssign) and (hi(a)=0)))
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) then begin
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{ only load the upper 32 bits, if the automatic sign extension is not okay,
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- that is, _not_ if
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- - loading the lower 32 bits resulted in -1 in the upper 32 bits, and the upper
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+ that is, _not_ if
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+ - loading the lower 32 bits resulted in -1 in the upper 32 bits, and the upper
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32 bits should contain -1
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- loading the lower 32 bits resulted in 0 in the upper 32 bits, and the upper
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32 bits should contain 0 }
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@@ -710,9 +710,9 @@ begin
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{$ENDIF EXTDEBUG}
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if not (size in [OS_8, OS_S8, OS_16, OS_S16, OS_32, OS_S32, OS_64, OS_S64]) then
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internalerror(2002090902);
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- { if PIC or basic optimizations are enabled, and the number of instructions which would be
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+ { if PIC or basic optimizations are enabled, and the number of instructions which would be
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required to load the value is greater than 2, store (and later load) the value from there }
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- if (false) {(((cs_fastoptimize in aktglobalswitches) or (cs_create_pic in aktmoduleswitches)) and
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+ if (false) {(((cs_opt_peephole in aktoptimizerswitches in aktglobalswitches) or (cs_create_pic in aktmoduleswitches)) and
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(getInstructionLength(a) > 2))} then
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loadConstantPIC(list, size, a, reg)
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else
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@@ -827,7 +827,7 @@ begin
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rg[R_INTREGISTER].add_move_instruction(instr);
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end;
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-procedure tcgppc.a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize;
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+procedure tcgppc.a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize;
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reg1, reg2: tregister);
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var
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instr: taicpu;
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@@ -837,7 +837,7 @@ begin
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rg[R_FPUREGISTER].add_move_instruction(instr);
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end;
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-procedure tcgppc.a_loadfpu_ref_reg(list: taasmoutput; size: tcgsize;
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+procedure tcgppc.a_loadfpu_ref_reg(list: taasmoutput; size: tcgsize;
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const ref: treference; reg: tregister);
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const
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FpuLoadInstr: array[OS_F32..OS_F64, boolean, boolean] of TAsmOp =
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@@ -924,7 +924,7 @@ var
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begin
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{ optimization logical and with immediate: only use "andi." for 16 bit
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ands, otherwise use register method. Doing this for 32 bit constants
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- would not give any advantage to the register method (via useReg := true),
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+ would not give any advantage to the register method (via useReg := true),
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requiring a scratch register and three instructions. }
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usereg := false;
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if (aword(a) > high(word)) then
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@@ -944,7 +944,7 @@ var
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u_add : boolean;
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power : byte;
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isNegPower : boolean;
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-
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+
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divreg : tregister;
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begin
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if (a = 0) then begin
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@@ -982,13 +982,13 @@ var
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cg.a_op_reg_reg_reg(exprasmlist, OP_SUB, OS_INT, src, dst, dst);
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end;
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{ shift shift places to the right (arithmetic) }
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- cg.a_op_const_reg_reg(exprasmlist, OP_SAR, OS_INT, shift, dst, dst);
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+ cg.a_op_const_reg_reg(exprasmlist, OP_SAR, OS_INT, shift, dst, dst);
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{ extract and add sign bit }
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if (a >= 0) then begin
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cg.a_op_const_reg_reg(exprasmlist, OP_SHR, OS_INT, 63, src, divreg);
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end else begin
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cg.a_op_const_reg_reg(exprasmlist, OP_SHR, OS_INT, 63, dst, divreg);
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- end;
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+ end;
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cg.a_op_reg_reg_reg(exprasmlist, OP_ADD, OS_INT, dst, divreg, dst);
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end else begin
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getmagic_unsignedN(sizeof(aWord)*8, a, u_magic, u_add, u_shift);
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@@ -1020,17 +1020,17 @@ begin
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exit;
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end;
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{ This case includes some peephole optimizations for the various operations,
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- (e.g. AND, OR, XOR, ..) - can't this be done at some higher level,
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+ (e.g. AND, OR, XOR, ..) - can't this be done at some higher level,
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independent of architecture? }
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{ assume that we do not need a scratch register for the operation }
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useReg := false;
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case (op) of
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OP_DIV, OP_IDIV:
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- if (cs_optimize in aktglobalswitches) then
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+ if (cs_opt_level1 in aktoptimizerswitches) then
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do_constant_div(list, size, a, src, dst, op = OP_IDIV)
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else
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- usereg := true;
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+ usereg := true;
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OP_IMUL, OP_MUL:
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{ idea: factorize constant multiplicands and use adds/shifts with few factors;
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however, even a 64 bit multiply is already quite fast on PPC64 }
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@@ -1079,11 +1079,11 @@ begin
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do_lo_hi(A_XORI, A_XORIS);
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OP_SHL, OP_SHR, OP_SAR:
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begin
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- if (size in [OS_64, OS_S64]) then
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+ if (size in [OS_64, OS_S64]) then
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shift := 6
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else
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shift := 5;
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-
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+
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shiftmask := (1 shl shift)-1;
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if (a and shiftmask) <> 0 then
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list.concat(taicpu.op_reg_reg_const(
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@@ -1136,7 +1136,7 @@ end;
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{*************** compare instructructions ****************}
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-procedure tcgppc.a_cmp_const_reg_label(list: taasmoutput; size: tcgsize;
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+procedure tcgppc.a_cmp_const_reg_label(list: taasmoutput; size: tcgsize;
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cmp_op: topcmp; a: aint; reg: tregister; l: tasmlabel);
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var
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scratch_register: TRegister;
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@@ -1167,7 +1167,7 @@ begin
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a_jmp(list, A_BC, TOpCmp2AsmCond[cmp_op], 0, l);
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end;
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-procedure tcgppc.a_cmp_reg_reg_label(list: taasmoutput; size: tcgsize;
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+procedure tcgppc.a_cmp_reg_reg_label(list: taasmoutput; size: tcgsize;
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cmp_op: topcmp; reg1, reg2: tregister; l: tasmlabel);
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var
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op: tasmop;
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@@ -1261,7 +1261,7 @@ end;
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procedure tcgppc.g_save_standard_registers(list: Taasmoutput);
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begin
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- { this work is done in g_proc_entry; additionally it is not safe
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+ { this work is done in g_proc_entry; additionally it is not safe
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to use it because it is called at some weird time }
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end;
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@@ -1301,15 +1301,15 @@ begin
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end;
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end;
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-{ Generates the entry code of a procedure/function.
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-
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+{ Generates the entry code of a procedure/function.
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+
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This procedure may be called before, as well as after g_return_from_proc
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- is called. localsize is the sum of the size necessary for local variables
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- and the maximum possible combined size of ALL the parameters of a procedure
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- called by the current one
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+ is called. localsize is the sum of the size necessary for local variables
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+ and the maximum possible combined size of ALL the parameters of a procedure
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+ called by the current one
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IMPORTANT: registers are not to be allocated through the register
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- allocator here, because the register colouring has already occured !!
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+ allocator here, because the register colouring has already occured !!
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}
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procedure tcgppc.g_proc_entry(list: taasmoutput; localsize: longint;
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nostackframe: boolean);
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@@ -1329,7 +1329,7 @@ var
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{ there are two ways to do this: manually, by generating a few "std" instructions,
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or via the restore helper functions. The latter are selected by the -Og switch,
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i.e. "optimize for size" }
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- if (cs_littlesize in aktglobalswitches) then begin
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+ if (cs_opt_size in aktoptimizerswitches) then begin
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mayNeedLRStore := false;
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if ((fprcount > 0) and (gprcount > 0)) then begin
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a_op_const_reg_reg(list, OP_SUB, OS_INT, 8 * fprcount, NR_R1, NR_R12);
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@@ -1381,9 +1381,9 @@ begin
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gprcount, fprcount);
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{ determine whether we need to save the link register }
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- needslinkreg :=
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- ((not (po_assembler in current_procinfo.procdef.procoptions)) and (pi_do_call in current_procinfo.flags)) or
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- ((cs_littlesize in aktglobalswitches) and ((fprcount > 0) or (gprcount > 0))) or
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+ needslinkreg :=
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+ ((not (po_assembler in current_procinfo.procdef.procoptions)) and (pi_do_call in current_procinfo.flags)) or
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+ ((cs_opt_size in aktoptimizerswitches) and ((fprcount > 0) or (gprcount > 0))) or
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([cs_lineinfo, cs_debuginfo] * aktmoduleswitches <> []);
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a_reg_alloc(list, NR_STACK_POINTER_REG);
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@@ -1412,7 +1412,7 @@ begin
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{ Use R0 for loading the constant (which is definitely > 32k when entering
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this branch).
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- Inlined at this position because it must not use temp registers because
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+ Inlined at this position because it must not use temp registers because
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register allocations have already been done }
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{ Code template:
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lis r0,ofs@highest
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@@ -1437,10 +1437,10 @@ begin
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a_reg_dealloc(list, NR_R0);
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end;
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-{ Generates the exit code for a method.
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+{ Generates the exit code for a method.
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This procedure may be called before, as well as after g_stackframe_entry
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- is called.
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+ is called.
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IMPORTANT: registers are not to be allocated through the register
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allocator here, because the register colouring has already occured !!
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@@ -1464,7 +1464,7 @@ var
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{ there are two ways to do this: manually, by generating a few "ld" instructions,
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or via the restore helper functions. The latter are selected by the -Og switch,
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i.e. "optimize for size" }
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- if (cs_littlesize in aktglobalswitches) then begin
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+ if (cs_opt_size in aktoptimizerswitches) then begin
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needsExitCode := false;
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if ((fprcount > 0) and (gprcount > 0)) then begin
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a_op_const_reg_reg(list, OP_SUB, OS_INT, 8 * fprcount, NR_R1, NR_R12);
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@@ -1519,9 +1519,9 @@ begin
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calcFirstUsedGPR(firstreggpr, gprcount);
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{ determine whether we need to restore the link register }
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- needslinkreg :=
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+ needslinkreg :=
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((not (po_assembler in current_procinfo.procdef.procoptions)) and (pi_do_call in current_procinfo.flags)) or
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- ((cs_littlesize in aktglobalswitches) and ((fprcount > 0) or (gprcount > 0))) or
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+ ((cs_opt_size in aktoptimizerswitches) and ((fprcount > 0) or (gprcount > 0))) or
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([cs_lineinfo, cs_debuginfo] * aktmoduleswitches <> []);
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{ calculate stack frame }
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@@ -1662,7 +1662,7 @@ begin
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internalerror(2002072704);
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list.concat(tai_comment.create(strpnew('g_concatcopy1 ' + inttostr(len) + ' bytes left ')));
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{$ENDIF extdebug}
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- { if the references are equal, exit, there is no need to copy anything }
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+ { if the references are equal, exit, there is no need to copy anything }
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if (references_equal(source, dest)) then
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exit;
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@@ -1671,7 +1671,7 @@ begin
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copy at all times.
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NOTE: maybe use some scratch registers to pair load/store instructions
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}
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-
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+
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if (len <= maxmoveunit) then begin
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src := source; dst := dest;
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{$IFDEF extdebug}
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@@ -1679,18 +1679,18 @@ begin
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{$ENDIF extdebug}
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while (len <> 0) do begin
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if (len = 8) then begin
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- a_load_ref_ref(list, OS_64, OS_64, src, dst);
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+ a_load_ref_ref(list, OS_64, OS_64, src, dst);
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dec(len, 8);
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end else if (len >= 4) then begin
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- a_load_ref_ref(list, OS_32, OS_32, src, dst);
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+ a_load_ref_ref(list, OS_32, OS_32, src, dst);
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inc(src.offset, 4); inc(dst.offset, 4);
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dec(len, 4);
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end else if (len >= 2) then begin
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- a_load_ref_ref(list, OS_16, OS_16, src, dst);
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+ a_load_ref_ref(list, OS_16, OS_16, src, dst);
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inc(src.offset, 2); inc(dst.offset, 2);
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dec(len, 2);
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end else begin
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- a_load_ref_ref(list, OS_8, OS_8, src, dst);
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+ a_load_ref_ref(list, OS_8, OS_8, src, dst);
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inc(src.offset, 1); inc(dst.offset, 1);
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dec(len, 1);
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end;
|
|
@@ -1729,9 +1729,9 @@ begin
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{ generate a loop }
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if count > 4 then begin
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- { the offsets are zero after the a_loadaddress_ref_reg and just
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- have to be set to 8. I put an Inc there so debugging may be
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- easier (should offset be different from zero here, it will be
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+ { the offsets are zero after the a_loadaddress_ref_reg and just
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+ have to be set to 8. I put an Inc there so debugging may be
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+ easier (should offset be different from zero here, it will be
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easy to notice in the generated assembler }
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|
inc(dst.offset, 8);
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inc(src.offset, 8);
|
|
@@ -1947,7 +1947,7 @@ end;
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|
|
function tcgppc.fixref(list: taasmoutput; var ref: treference; const size : TCgsize): boolean;
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|
|
var
|
|
|
- tmpreg: tregister;
|
|
|
+ tmpreg: tregister;
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|
|
name : string;
|
|
|
begin
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|
|
result := false;
|
|
@@ -1968,7 +1968,7 @@ begin
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|
|
a_op_reg_reg_reg(list, OP_ADD, OS_ADDR, ref.base, tmpreg, tmpreg);
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|
|
ref.base := tmpreg;
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|
|
end;
|
|
|
- ref.symbol := nil;
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|
+ ref.symbol := nil;
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|
|
{$IFDEF EXTDEBUG}
|
|
|
list.concat(tai_comment.create(strpnew('fixref-pic ' + ref2string(ref))));
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|
|
{$ENDIF EXTDEBUG}
|
|
@@ -2016,7 +2016,7 @@ begin
|
|
|
list.concat(taicpu.op_reg_ref(op, reg, ref));
|
|
|
exit;
|
|
|
end;
|
|
|
-
|
|
|
+
|
|
|
{ for some instructions we need to check that the offset is divisible by at
|
|
|
least four. If not, add the bytes which are "off" to the base register and
|
|
|
adjust the offset accordingly }
|
|
@@ -2089,7 +2089,7 @@ begin
|
|
|
tmpref.base := ref.base;
|
|
|
tmpref.index := tmpreg2;
|
|
|
case op of
|
|
|
- { the code generator doesn't generate update instructions anyway, so
|
|
|
+ { the code generator doesn't generate update instructions anyway, so
|
|
|
error out on those instructions }
|
|
|
A_LBZ : op := A_LBZX;
|
|
|
A_LHZ : op := A_LHZX;
|
|
@@ -2153,7 +2153,7 @@ begin
|
|
|
list.concat(p)
|
|
|
end;
|
|
|
|
|
|
-function tcgppc.hasLargeOffset(const ref : TReference) : Boolean;
|
|
|
+function tcgppc.hasLargeOffset(const ref : TReference) : Boolean; {$ifdef ver2_0}inline;{$endif}
|
|
|
begin
|
|
|
{ this rather strange calculation is required because offsets of TReferences are unsigned }
|
|
|
result := aword(ref.offset-low(smallint)) > high(smallint)-low(smallint);
|
|
@@ -2175,7 +2175,7 @@ begin
|
|
|
asmlist[al_picdata].concat(tai_directive.create(asd_toc_entry, symname + '[TC], ' + inttostr(a)));
|
|
|
end;
|
|
|
reference_reset_symbol(ref,l,0);
|
|
|
- ref.base := NR_R2;
|
|
|
+ ref.base := NR_R2;
|
|
|
ref.refaddr := addr_pic;
|
|
|
|
|
|
{$IFDEF EXTDEBUG}
|