* also improve the code, generated for signed division by 2 on i8086, when

  optimize cpu target is 486+, by replacing the sequence
    sar reg, 15
    and reg, 1
  with:
    shr reg, 15

git-svn-id: trunk@36807 -

compiler/i8086/n8086mat.pas

@@ -136,10 +136,18 @@ implementation
                         { no jumps, but more operations }
                         hreg2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
                         emit_reg_reg(A_MOV,S_W,hreg1,hreg2);
-                        {If the left value is negative, hreg2=$ffff, otherwise 0.}
-                        cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SAR,OS_16,15,hreg2);
-                        {If negative, hreg2=right value-1, otherwise 0.}
-                        emit_const_reg(A_AND,S_W,tordconstnode(right).value.svalue-1,hreg2);
+                        if tordconstnode(right).value=2 then
+                          begin
+                            {If the left value is negative, hreg2=(right value-1)=1, otherwise 0.}
+                            cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,OS_16,15,hreg2);
+                          end
+                        else
+                          begin
+                            {If the left value is negative, hreg2=$ffff, otherwise 0.}
+                            cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SAR,OS_16,15,hreg2);
+                            {If negative, hreg2=right value-1, otherwise 0.}
+                            emit_const_reg(A_AND,S_W,tordconstnode(right).value.svalue-1,hreg2);
+                          end;
                         { add to the left value }
                         emit_reg_reg(A_ADD,S_W,hreg2,hreg1);
                         { do the shift }