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* changed record typecast into shift to avoid q3 becoming not
regable in FPC_MUL_INT64

git-svn-id: trunk@3183 -

Jonas Maebe 19 years ago
parent
commit
bd27a09918
1 changed files with 1 additions and 1 deletions
  1. 1 1
      rtl/inc/int64.inc

+ 1 - 1
rtl/inc/int64.inc

@@ -348,7 +348,7 @@
               ((q1>q3) or (q2>q3) or
                 { the bit 63 can be only set if we have $80000000 00000000 }
                 { and sign is true                                         }
-                ((tqwordrec(q3).high and dword($80000000))<>0) and
+                (q3 shr 63<>0) and
                  ((q3<>(qword(1) shl 63)) or not(sign))
                 ) then
                 HandleErrorFrame(215,get_frame);