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@@ -157,6 +157,28 @@ unit cgcpu;
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A_NONE
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);
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+ { opcode with extend bits table lookup, used by 64bit cg }
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+ topcg2tasmopx: Array[topcg] of tasmop =
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+ (
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+ A_NONE,
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+ A_NONE,
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+ A_ADDX,
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+ A_NONE,
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+ A_NONE,
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+ A_NONE,
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+ A_NONE,
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+ A_NONE,
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+ A_NEGX,
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+ A_NONE,
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+ A_NONE,
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+ A_NONE,
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+ A_NONE,
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+ A_NONE,
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+ A_SUBX,
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+ A_NONE,
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+ A_NONE,
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+ A_NONE
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+ );
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TOpCmp2AsmCond: Array[topcmp] of TAsmCond =
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(
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@@ -1669,9 +1691,9 @@ unit cgcpu;
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begin
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localsize := current_procinfo.calc_stackframe_size;
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list.concat(taicpu.op_reg(A_UNLK,S_NO,NR_FRAME_POINTER_REG));
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- parasize := parasize - target_info.first_parm_offset; { i'm still not 100% confident that this is
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- correct here, but at least it looks less
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- hacky, and makes some sense (KB) }
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+ parasize := parasize - target_info.first_parm_offset; { i'm still not 100% confident that this is
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+ correct here, but at least it looks less
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+ hacky, and makes some sense (KB) }
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if (parasize<>0) then
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begin
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{ only 68020+ supports RTD, so this needs another code path
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@@ -1985,156 +2007,127 @@ unit cgcpu;
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{****************************************************************************}
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{ TCG64F68K }
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{****************************************************************************}
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- procedure tcg64f68k.a_op64_reg_reg(list : TAsmList;op:TOpCG;size: tcgsize; regsrc,regdst : tregister64);
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- var
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- hreg1, hreg2 : tregister;
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- opcode : tasmop;
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- instr : taicpu;
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- begin
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-// writeln('a_op64_reg_reg');
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- opcode := topcg2tasmop[op];
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- case op of
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- OP_ADD :
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- begin
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- { if one of these three registers is an address
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- register, we'll really get into problems!
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- }
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- if isaddressregister(regdst.reglo) or
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- isaddressregister(regdst.reghi) or
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- isaddressregister(regsrc.reghi) then
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- internalerror(20020817);
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- list.concat(taicpu.op_reg_reg(A_ADD,S_L,regsrc.reglo,regdst.reglo));
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- list.concat(taicpu.op_reg_reg(A_ADDX,S_L,regsrc.reghi,regdst.reghi));
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- end;
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- OP_AND,OP_OR :
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- begin
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- { at least one of the registers must be a data register }
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- if (isaddressregister(regdst.reglo) and
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- isaddressregister(regsrc.reglo)) or
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- (isaddressregister(regsrc.reghi) and
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- isaddressregister(regdst.reghi))
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- then
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- internalerror(20020817);
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- cg.a_op_reg_reg(list,op,OS_32,regsrc.reglo,regdst.reglo);
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- cg.a_op_reg_reg(list,op,OS_32,regsrc.reghi,regdst.reghi);
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- end;
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- { this is handled in 1st pass for 32-bit cpu's (helper call) }
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- OP_IDIV,OP_DIV,
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- OP_IMUL,OP_MUL: internalerror(2002081701);
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- { this is also handled in 1st pass for 32-bit cpu's (helper call) }
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- OP_SAR,OP_SHL,OP_SHR: internalerror(2002081702);
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- OP_SUB:
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- begin
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- { if one of these three registers is an address
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- register, we'll really get into problems!
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- }
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- if isaddressregister(regdst.reglo) or
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- isaddressregister(regdst.reghi) or
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- isaddressregister(regsrc.reghi) then
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- internalerror(20020817);
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- list.concat(taicpu.op_reg_reg(A_SUB,S_L,regsrc.reglo,regdst.reglo));
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- list.concat(taicpu.op_reg_reg(A_SUBX,S_L,regsrc.reghi,regdst.reghi));
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- end;
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- OP_XOR:
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- begin
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- if isaddressregister(regdst.reglo) or
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- isaddressregister(regsrc.reglo) or
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- isaddressregister(regsrc.reghi) or
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- isaddressregister(regdst.reghi) then
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- internalerror(20020817);
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- list.concat(taicpu.op_reg_reg(A_EOR,S_L,regsrc.reglo,regdst.reglo));
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- list.concat(taicpu.op_reg_reg(A_EOR,S_L,regsrc.reghi,regdst.reghi));
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- end;
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- OP_NEG:
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- begin
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- if isaddressregister(regdst.reglo) or
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- isaddressregister(regdst.reghi) then
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- internalerror(2012110402);
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- instr:=taicpu.op_reg_reg(A_MOVE,S_L,regsrc.reglo,regdst.reglo);
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- cg.add_move_instruction(instr);
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- list.concat(instr);
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- instr:=taicpu.op_reg_reg(A_MOVE,S_L,regsrc.reghi,regdst.reghi);
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- cg.add_move_instruction(instr);
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- list.concat(instr);
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- list.concat(taicpu.op_reg(A_NEG,S_L,regdst.reglo));
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- list.concat(taicpu.op_reg(A_NEGX,S_L,regdst.reghi));
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- end;
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- OP_NOT:
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- begin
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- if isaddressregister(regdst.reglo) or
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- isaddressregister(regdst.reghi) then
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- internalerror(2012110401);
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- instr:=taicpu.op_reg_reg(A_MOVE,S_L,regsrc.reglo,regdst.reglo);
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- cg.add_move_instruction(instr);
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- list.concat(instr);
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- instr:=taicpu.op_reg_reg(A_MOVE,S_L,regsrc.reghi,regdst.reghi);
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- cg.add_move_instruction(instr);
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- list.concat(instr);
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- list.concat(taicpu.op_reg(A_NOT,S_L,regdst.reglo));
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- list.concat(taicpu.op_reg(A_NOT,S_L,regdst.reghi));
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- end;
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- end; { end case }
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- end;
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+ procedure tcg64f68k.a_op64_reg_reg(list : TAsmList;op:TOpCG;size: tcgsize; regsrc,regdst : tregister64);
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+ var
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+ hreg1, hreg2 : tregister;
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+ opcode : tasmop;
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+ xopcode : tasmop;
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+ instr : taicpu;
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+ begin
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+ opcode := topcg2tasmop[op];
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+ xopcode := topcg2tasmopx[op];
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+
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+ case op of
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+ OP_ADD,OP_SUB:
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+ begin
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+ { if one of these three registers is an address
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+ register, we'll really get into problems! }
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+ if isaddressregister(regdst.reglo) or
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+ isaddressregister(regdst.reghi) or
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+ isaddressregister(regsrc.reghi) then
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+ internalerror(2014030101);
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+ list.concat(taicpu.op_reg_reg(opcode,S_L,regsrc.reglo,regdst.reglo));
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+ list.concat(taicpu.op_reg_reg(xopcode,S_L,regsrc.reghi,regdst.reghi));
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+ end;
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+ OP_AND,OP_OR:
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+ begin
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+ { at least one of the registers must be a data register }
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+ if (isaddressregister(regdst.reglo) and
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+ isaddressregister(regsrc.reglo)) or
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+ (isaddressregister(regsrc.reghi) and
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+ isaddressregister(regdst.reghi)) then
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+ internalerror(2014030102);
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+ cg.a_op_reg_reg(list,op,OS_32,regsrc.reglo,regdst.reglo);
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+ cg.a_op_reg_reg(list,op,OS_32,regsrc.reghi,regdst.reghi);
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+ end;
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+ { this is handled in 1st pass for 32-bit cpu's (helper call) }
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+ OP_IDIV,OP_DIV,
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+ OP_IMUL,OP_MUL:
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+ internalerror(2002081701);
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+ { this is also handled in 1st pass for 32-bit cpu's (helper call) }
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+ OP_SAR,OP_SHL,OP_SHR:
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+ internalerror(2002081702);
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+ OP_XOR:
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+ begin
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+ if isaddressregister(regdst.reglo) or
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+ isaddressregister(regsrc.reglo) or
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+ isaddressregister(regsrc.reghi) or
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+ isaddressregister(regdst.reghi) then
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+ internalerror(2014030103);
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+ cg.a_op_reg_reg(list,op,OS_32,regsrc.reglo,regdst.reglo);
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+ cg.a_op_reg_reg(list,op,OS_32,regsrc.reghi,regdst.reghi);
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+ end;
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+ OP_NEG,OP_NOT:
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+ begin
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+ if isaddressregister(regdst.reglo) or
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+ isaddressregister(regdst.reghi) then
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+ internalerror(2014030104);
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+ instr:=taicpu.op_reg_reg(A_MOVE,S_L,regsrc.reglo,regdst.reglo);
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+ cg.add_move_instruction(instr);
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+ list.concat(instr);
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+ instr:=taicpu.op_reg_reg(A_MOVE,S_L,regsrc.reghi,regdst.reghi);
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+ cg.add_move_instruction(instr);
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+ list.concat(instr);
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+ if (op = OP_NOT) then
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+ xopcode:=opcode;
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+ list.concat(taicpu.op_reg(opcode,S_L,regdst.reglo));
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+ list.concat(taicpu.op_reg(xopcode,S_L,regdst.reghi));
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+ end;
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+ end; { end case }
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+ end;
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- procedure tcg64f68k.a_op64_const_reg(list : TAsmList;op:TOpCG;size: tcgsize; value : int64;regdst : tregister64);
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- var
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- lowvalue : cardinal;
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- highvalue : cardinal;
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- hreg : tregister;
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- begin
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-// writeln('a_op64_const_reg');
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- { is it optimized out ? }
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-// if cg.optimize64_op_const_reg(list,op,value,reg) then
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-// exit;
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-
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- lowvalue := cardinal(value);
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- highvalue:= value shr 32;
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-
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- { the destination registers must be data registers }
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- if isaddressregister(regdst.reglo) or
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- isaddressregister(regdst.reghi) then
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- internalerror(20020817);
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- case op of
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- OP_ADD :
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- begin
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- hreg:=cg.getintregister(list,OS_INT);
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- list.concat(taicpu.op_const_reg(A_MOVE,S_L,highvalue,hreg));
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- list.concat(taicpu.op_const_reg(A_ADD,S_L,lowvalue,regdst.reglo));
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- list.concat(taicpu.op_reg_reg(A_ADDX,S_L,hreg,regdst.reghi));
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- end;
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- OP_AND :
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- begin
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- list.concat(taicpu.op_const_reg(A_AND,S_L,lowvalue,regdst.reglo));
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- list.concat(taicpu.op_const_reg(A_AND,S_L,highvalue,regdst.reghi));
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- end;
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- OP_OR :
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- begin
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- list.concat(taicpu.op_const_reg(A_OR,S_L,lowvalue,regdst.reglo));
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- list.concat(taicpu.op_const_reg(A_OR,S_L,highvalue,regdst.reghi));
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- end;
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- { this is handled in 1st pass for 32-bit cpus (helper call) }
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- OP_IDIV,OP_DIV,
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- OP_IMUL,OP_MUL: internalerror(2002081701);
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- { this is also handled in 1st pass for 32-bit cpus (helper call) }
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- OP_SAR,OP_SHL,OP_SHR: internalerror(2002081702);
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- OP_SUB:
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- begin
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- hreg:=cg.getintregister(list,OS_INT);
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- list.concat(taicpu.op_const_reg(A_MOVE,S_L,highvalue,hreg));
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- list.concat(taicpu.op_const_reg(A_SUB,S_L,lowvalue,regdst.reglo));
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- list.concat(taicpu.op_reg_reg(A_SUBX,S_L,hreg,regdst.reghi));
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- end;
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- OP_XOR:
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- begin
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- list.concat(taicpu.op_const_reg(A_EOR,S_L,lowvalue,regdst.reglo));
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- list.concat(taicpu.op_const_reg(A_EOR,S_L,highvalue,regdst.reghi));
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- end;
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- { these should have been handled already by earlier passes }
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- OP_NOT, OP_NEG:
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- internalerror(2012110403);
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- end; { end case }
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- end;
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+ procedure tcg64f68k.a_op64_const_reg(list : TAsmList;op:TOpCG;size: tcgsize; value : int64;regdst : tregister64);
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+ var
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+ lowvalue : cardinal;
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+ highvalue : cardinal;
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+ opcode : tasmop;
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+ xopcode : tasmop;
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+ hreg : tregister;
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+ begin
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+ { is it optimized out ? }
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+ { optimize64_op_const_reg doesn't seem to be used in any cg64f32 right now. why? (KB) }
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+ { if cg.optimize64_op_const_reg(list,op,value,reg) then
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+ exit; }
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+
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+ lowvalue := cardinal(value);
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+ highvalue := value shr 32;
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+
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+ opcode := topcg2tasmop[op];
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+ xopcode := topcg2tasmopx[op];
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+
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+ { the destination registers must be data registers }
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+ if isaddressregister(regdst.reglo) or
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+ isaddressregister(regdst.reghi) then
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+ internalerror(2014030105);
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+ case op of
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+ OP_ADD,OP_SUB:
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+ begin
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+ hreg:=cg.getintregister(list,OS_INT);
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+ { cg.a_load_const_reg provides optimized loading to register for special cases }
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+ cg.a_load_const_reg(list,OS_S32,longint(highvalue),hreg);
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+ { don't use cg.a_op_const_reg() here, because a possible optimized
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+ ADDQ/SUBQ wouldn't set the eXtend bit }
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+ list.concat(taicpu.op_const_reg(opcode,S_L,lowvalue,regdst.reglo));
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+ list.concat(taicpu.op_reg_reg(xopcode,S_L,hreg,regdst.reghi));
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+ end;
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+ OP_AND,OP_OR,OP_XOR:
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+ begin
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+ cg.a_op_const_reg(list,op,OS_S32,longint(lowvalue),regdst.reglo);
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+ cg.a_op_const_reg(list,op,OS_S32,longint(highvalue),regdst.reghi);
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+ end;
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+ { this is handled in 1st pass for 32-bit cpus (helper call) }
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+ OP_IDIV,OP_DIV,
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+ OP_IMUL,OP_MUL:
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+ internalerror(2002081701);
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+ { this is also handled in 1st pass for 32-bit cpus (helper call) }
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+ OP_SAR,OP_SHL,OP_SHR:
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+ internalerror(2002081702);
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+ { these should have been handled already by earlier passes }
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+ OP_NOT,OP_NEG:
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+ internalerror(2012110403);
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+ end; { end case }
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+ end;
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procedure create_codegen;
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Károly Balogh