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@@ -377,6 +377,10 @@ interface
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op:Tasmop;
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cgsize:TCgSize;
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opsize:topsize;
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+ e, sm: aint;
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+ d,m: aword;
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+ m_add: boolean;
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+ s: byte;
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begin
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secondpass(left);
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if codegenerror then
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@@ -397,33 +401,106 @@ interface
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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hreg1:=left.location.register;
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- if (nodetype=divn) and (right.nodetype=ordconstn) and
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- ispowerof2(int64(tordconstnode(right).value),power) then
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+ if (nodetype=divn) and (right.nodetype=ordconstn) then
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begin
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- { for signed numbers, the numerator must be adjusted before the
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- shift instruction, but not wih unsigned numbers! Otherwise,
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- "Cardinal($ffffffff) div 16" overflows! (JM) }
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- if is_signed(left.resultdef) Then
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+ if ispowerof2(int64(tordconstnode(right).value),power) then
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begin
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- { use a sequence without jumps, saw this in
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- comp.compilers (JM) }
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- { no jumps, but more operations }
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- hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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- emit_reg_reg(A_MOV,opsize,hreg1,hreg2);
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- {If the left value is signed, hreg2=$ffffffff, otherwise 0.}
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- emit_const_reg(A_SAR,opsize,63,hreg2);
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- {If signed, hreg2=right value-1, otherwise 0.}
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- { (don't use emit_const_reg, because if value>high(longint)
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- then it must first be loaded into a register) }
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- cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,cgsize,tordconstnode(right).value-1,hreg2);
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- { add to the left value }
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- emit_reg_reg(A_ADD,opsize,hreg2,hreg1);
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- { do the shift }
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- emit_const_reg(A_SAR,opsize,power,hreg1);
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+ { for signed numbers, the numerator must be adjusted before the
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+ shift instruction, but not wih unsigned numbers! Otherwise,
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+ "Cardinal($ffffffff) div 16" overflows! (JM) }
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+ if is_signed(left.resultdef) Then
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+ begin
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+ { use a sequence without jumps, saw this in
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+ comp.compilers (JM) }
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+ { no jumps, but more operations }
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+ hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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+ emit_reg_reg(A_MOV,opsize,hreg1,hreg2);
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+ {If the left value is signed, hreg2=$ffffffff, otherwise 0.}
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+ emit_const_reg(A_SAR,opsize,63,hreg2);
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+ {If signed, hreg2=right value-1, otherwise 0.}
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+ { (don't use emit_const_reg, because if value>high(longint)
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+ then it must first be loaded into a register) }
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+ cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,cgsize,tordconstnode(right).value-1,hreg2);
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+ { add to the left value }
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+ emit_reg_reg(A_ADD,opsize,hreg2,hreg1);
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+ { do the shift }
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+ emit_const_reg(A_SAR,opsize,power,hreg1);
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+ end
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+ else
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+ emit_const_reg(A_SHR,opsize,power,hreg1);
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+ location.register:=hreg1;
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end
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else
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- emit_const_reg(A_SHR,opsize,power,hreg1);
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- location.register:=hreg1;
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+ begin
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+ if is_signed(left.resultdef) then
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+ begin
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+ e:=tordconstnode(right).value.svalue;
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+ calc_divconst_magic_signed(resultdef.size*8,e,sm,s);
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+ cg.getcpuregister(current_asmdata.CurrAsmList,rega);
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+ emit_const_reg(A_MOV,opsize,sm,rega);
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+ cg.getcpuregister(current_asmdata.CurrAsmList,regd);
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+ emit_reg(A_IMUL,opsize,hreg1);
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+ { only the high half of result is used }
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+ cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
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+ { add or subtract dividend }
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+ if (e>0) and (sm<0) then
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+ emit_reg_reg(A_ADD,opsize,hreg1,regd)
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+ else if (e<0) and (sm>0) then
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+ emit_reg_reg(A_SUB,opsize,hreg1,regd);
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+ { shift if necessary }
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+ if (s<>0) then
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+ emit_const_reg(A_SAR,opsize,s,regd);
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+ { extract and add the sign bit }
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+ if (e<0) then
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+ emit_reg_reg(A_MOV,opsize,regd,hreg1);
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+ { if e>=0, hreg1 still contains dividend }
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+ emit_const_reg(A_SHR,opsize,left.resultdef.size*8-1,hreg1);
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+ emit_reg_reg(A_ADD,opsize,hreg1,regd);
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+ cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
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+ location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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+ cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register)
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+ end
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+ else
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+ begin
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+ d:=tordconstnode(right).value.svalue;
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+ if d>=aword(1) shl (left.resultdef.size*8-1) then
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+ begin
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+ if (cgsize in [OS_64,OS_S64]) then
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+ begin
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+ hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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+ emit_const_reg(A_MOV,opsize,aint(d),hreg2);
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+ emit_reg_reg(A_CMP,opsize,hreg2,hreg1);
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+ end
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+ else
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+ emit_const_reg(A_CMP,opsize,aint(d),hreg1);
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+ location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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+ emit_const_reg(A_MOV,opsize,0,location.register);
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+ emit_const_reg(A_SBB,opsize,-1,location.register);
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+ end
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+ else
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+ begin
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+ calc_divconst_magic_unsigned(resultdef.size*8,d,m,m_add,s);
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+ cg.getcpuregister(current_asmdata.CurrAsmList,rega);
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+ emit_const_reg(A_MOV,opsize,aint(m),rega);
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+ cg.getcpuregister(current_asmdata.CurrAsmList,regd);
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+ emit_reg(A_MUL,opsize,hreg1);
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+ cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
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+ if m_add then
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+ begin
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+ { addition can overflow, shift first bit considering carry,
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+ then shift remaining bits in regular way. }
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+ emit_reg_reg(A_ADD,opsize,hreg1,regd);
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+ emit_const_reg(A_RCR,opsize,1,regd);
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+ dec(s);
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+ end;
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+ if s<>0 then
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+ emit_const_reg(A_SHR,opsize,aint(s),regd);
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+ cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
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+ location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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+ cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register)
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+ end;
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+ end;
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+ end;
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end
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else
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begin
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sergei