git-svn-id: branches/z80@44532 -
@@ -754,10 +754,8 @@ implementation
{$endif AVR}
if getregtype(r)<>R_INTREGISTER then
internalerror(2017091101);
-{$ifndef Z80}
if getsubreg(r)<>R_SUBWHOLE then
internalerror(2017091102);
-{$endif Z80}
result:=TRegister(longint(r)+1);
end;
{$endif cpu8bitalu or cpu16bitalu}
@@ -137,7 +137,7 @@ unit cgcpu;
begin
inherited init_register_allocators;
rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
- [RS_BC,RS_DE,RS_HL],first_int_imreg,[]);
+ [RS_A,RS_B,RS_C,RS_D,RS_E,RS_H,RS_L],first_int_imreg,[]);
@@ -89,7 +89,7 @@ unit cpubase;
{$i rz80sup.inc}
{ No Subregisters }
- R_SUBWHOLE = R_SUBW;
+ R_SUBWHOLE = R_SUBL;
{ Available Registers }
{$i rz80con.inc}
@@ -6,29 +6,45 @@
;
NO,$00000000,INVALID,0,0
-A,$01010000,a,1,1
+; Main registers
+B,$01010000,b,1,1
C,$01010001,c,2,2
-B,$01020001,b,3,3
-BC,$01030001,bc,4,4
-E,$01010002,e,5,5
-D,$01020002,d,6,6
-DE,$01030002,de,7,7
-L,$01010003,l,8,8
-H,$01020003,h,9,9
-HL,$01030003,hl,10,10
-IX,$01030004,ix,11,11
-IY,$01030005,iy,12,12
-A_,$01010006,a'',13,13
-C_,$01010007,c'',14,14
-B_,$01020008,b'',15,15
-E_,$01010009,e'',16,16
-D_,$0102000a,d'',17,17
-L_,$0101000b,l'',18,18
-H_,$0102000c,h'',19,19
-
-SP,$05000000,sp,20,20
-PC,$05000001,pc,21,21
-R,$050000002,r,22,22
-F,$05000003,f,23,23
-F_,$05000004,f'',24,24
-I,$05000005,i,25,25
+D,$01010002,d,3,3
+E,$01010003,e,4,4
+H,$01010004,h,5,5
+L,$01010005,l,6,6
+A,$01010007,a,7,7
+
+; Register pairs
+BC,$01030001,bc,8,8
+DE,$01030003,de,9,9
+HL,$01030005,hl,10,10
+AF,$01030007,af,11,11
+; Index registers
+IX,$01030008,ix,11,11
+IY,$01030009,iy,12,12
+; Alternate registers
+B_,$05010000,b'',13,13
+C_,$05010001,c'',14,14
+D_,$05010002,d'',15,15
+E_,$05010003,e'',16,16
+H_,$05010004,h'',17,17
+L_,$05010005,l'',18,18
+A_,$05010007,a'',19,19
+; Stack pointer
+SP,$05030008,sp,20,20
+; Flags
+F,$05010009,f,23,23
+F_,$0501000a,f'',24,24
+; Program counter
+PC,$0503000b,pc,21,21
+; Other registers
+I,$0501000c,i,25,25
+R,$0501000d,r,22,22