* SPARC: simplified and fixed a_load_const_reg method, was generating redundant instructions for constants with non-zero bits 10..12.

git-svn-id: trunk@26318 -

compiler/sparc/cgcpu.pas

@@ -415,15 +415,13 @@ implementation
           instructions which would cause problems with the delay slot (FK) }
         if (a=0) then
           list.concat(taicpu.op_reg(A_CLR,reg))
-        { sethi allows to set the upper 22 bit, so we'll take full advantage of it }
-        else if (aint(a) and aint($1fff))=0 then
-          list.concat(taicpu.op_const_reg(A_SETHI,aint(a) shr 10,reg))
         else if (a>=simm13lo) and (a<=simm13hi) then
           list.concat(taicpu.op_const_reg(A_MOV,a,reg))
         else
           begin
             list.concat(taicpu.op_const_reg(A_SETHI,aint(a) shr 10,reg));
-            list.concat(taicpu.op_reg_const_reg(A_OR,reg,aint(a) and aint($3ff),reg));
+            if (aint(a) and aint($3ff))<>0 then
+              list.concat(taicpu.op_reg_const_reg(A_OR,reg,aint(a) and aint($3ff),reg));
           end;
       end;