Browse Source

Generate better code in Tthumb2cgarm.g_flags2reg

The old code generated a strange IT-sequence:

IT EQ
MOVEQ r0, #1
IT NE
MOVNE r0, #1

Now we generate:

ITE EQ
MOVEQ r0, #1
MOVNE r0, #1

IT stands for IfThen, ITE for IfThenElse it has a couple of other forms
where the instruction gets extended to handle more of the following
instructions. So we have ITEE, ITETE etc, up to 4 instructions can be
handled.

git-svn-id: trunk@21996 -
masta 13 years ago
parent
commit
c16871e129
1 changed files with 3 additions and 7 deletions
  1. 3 7
      compiler/arm/cgcpu.pas

+ 3 - 7
compiler/arm/cgcpu.pas

@@ -3384,13 +3384,9 @@ unit cgcpu;
     procedure Tthumb2cgarm.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
     procedure Tthumb2cgarm.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
       var item: taicpu;
       var item: taicpu;
       begin
       begin
-        item := setcondition(taicpu.op_reg_const(A_MOV,reg,1),flags_to_cond(f));
-        list.concat(item);
-        list.insertbefore(taicpu.op_cond(A_IT, flags_to_cond(f)), item);
-
-        item := setcondition(taicpu.op_reg_const(A_MOV,reg,0),inverse_cond(flags_to_cond(f)));
-        list.concat(item);
-        list.insertbefore(taicpu.op_cond(A_IT, inverse_cond(flags_to_cond(f))), item);
+        list.concat(taicpu.op_cond(A_ITE, flags_to_cond(f)));
+        list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,1),flags_to_cond(f)));
+        list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,0),inverse_cond(flags_to_cond(f))));
       end;
       end;