* integer registers on sparc(64) do not have an explicit size anymore, simplifies compiler code sharing between sparc32 and sparc64

+ %icc and %xcc register for sparc64

git-svn-id: trunk@36548 -

compiler/sparc/rspcon.inc

@@ -1,37 +1,37 @@
 { don't edit, this file is generated from spreg.dat }
 NR_NO = tregister($00000000);
-NR_G0 = tregister($01040000);
-NR_G1 = tregister($01040001);
-NR_G2 = tregister($01040002);
-NR_G3 = tregister($01040003);
-NR_G4 = tregister($01040004);
-NR_G5 = tregister($01040005);
-NR_G6 = tregister($01040006);
-NR_G7 = tregister($01040007);
-NR_O0 = tregister($01040008);
-NR_O1 = tregister($01040009);
-NR_O2 = tregister($0104000a);
-NR_O3 = tregister($0104000b);
-NR_O4 = tregister($0104000c);
-NR_O5 = tregister($0104000d);
-NR_O6 = tregister($0104000e);
-NR_O7 = tregister($0104000f);
-NR_L0 = tregister($01040010);
-NR_L1 = tregister($01040011);
-NR_L2 = tregister($01040012);
-NR_L3 = tregister($01040013);
-NR_L4 = tregister($01040014);
-NR_L5 = tregister($01040015);
-NR_L6 = tregister($01040016);
-NR_L7 = tregister($01040017);
-NR_I0 = tregister($01040018);
-NR_I1 = tregister($01040019);
-NR_I2 = tregister($0104001a);
-NR_I3 = tregister($0104001b);
-NR_I4 = tregister($0104001c);
-NR_I5 = tregister($0104001d);
-NR_I6 = tregister($0104001e);
-NR_I7 = tregister($0104001f);
+NR_G0 = tregister($01000000);
+NR_G1 = tregister($01000001);
+NR_G2 = tregister($01000002);
+NR_G3 = tregister($01000003);
+NR_G4 = tregister($01000004);
+NR_G5 = tregister($01000005);
+NR_G6 = tregister($01000006);
+NR_G7 = tregister($01000007);
+NR_O0 = tregister($01000008);
+NR_O1 = tregister($01000009);
+NR_O2 = tregister($0100000a);
+NR_O3 = tregister($0100000b);
+NR_O4 = tregister($0100000c);
+NR_O5 = tregister($0100000d);
+NR_O6 = tregister($0100000e);
+NR_O7 = tregister($0100000f);
+NR_L0 = tregister($01000010);
+NR_L1 = tregister($01000011);
+NR_L2 = tregister($01000012);
+NR_L3 = tregister($01000013);
+NR_L4 = tregister($01000014);
+NR_L5 = tregister($01000015);
+NR_L6 = tregister($01000016);
+NR_L7 = tregister($01000017);
+NR_I0 = tregister($01000018);
+NR_I1 = tregister($01000019);
+NR_I2 = tregister($0100001a);
+NR_I3 = tregister($0100001b);
+NR_I4 = tregister($0100001c);
+NR_I5 = tregister($0100001d);
+NR_I6 = tregister($0100001e);
+NR_I7 = tregister($0100001f);
 NR_FP = tregister($0104001e);
 NR_SP = tregister($0104000e);
 NR_F0 = tregister($02060000);

compiler/sparc/rsprni.inc

@@ -15,7 +15,6 @@
 13,
 14,
 15,
-34,
 16,
 17,
 18,
@@ -32,8 +31,9 @@
 29,
 30,
 31,
-33,
 32,
+34,
+33,
 35,
 36,
 37,

compiler/sparc64/rsp64con.inc

@@ -1,37 +1,37 @@
 { don't edit, this file is generated from spreg.dat }
 NR_NO = tregister($00000000);
-NR_G0 = tregister($01040000);
-NR_G1 = tregister($01040001);
-NR_G2 = tregister($01040002);
-NR_G3 = tregister($01040003);
-NR_G4 = tregister($01040004);
-NR_G5 = tregister($01040005);
-NR_G6 = tregister($01040006);
-NR_G7 = tregister($01040007);
-NR_O0 = tregister($01040008);
-NR_O1 = tregister($01040009);
-NR_O2 = tregister($0104000a);
-NR_O3 = tregister($0104000b);
-NR_O4 = tregister($0104000c);
-NR_O5 = tregister($0104000d);
-NR_O6 = tregister($0104000e);
-NR_O7 = tregister($0104000f);
-NR_L0 = tregister($01040010);
-NR_L1 = tregister($01040011);
-NR_L2 = tregister($01040012);
-NR_L3 = tregister($01040013);
-NR_L4 = tregister($01040014);
-NR_L5 = tregister($01040015);
-NR_L6 = tregister($01040016);
-NR_L7 = tregister($01040017);
-NR_I0 = tregister($01040018);
-NR_I1 = tregister($01040019);
-NR_I2 = tregister($0104001a);
-NR_I3 = tregister($0104001b);
-NR_I4 = tregister($0104001c);
-NR_I5 = tregister($0104001d);
-NR_I6 = tregister($0104001e);
-NR_I7 = tregister($0104001f);
+NR_G0 = tregister($01000000);
+NR_G1 = tregister($01000001);
+NR_G2 = tregister($01000002);
+NR_G3 = tregister($01000003);
+NR_G4 = tregister($01000004);
+NR_G5 = tregister($01000005);
+NR_G6 = tregister($01000006);
+NR_G7 = tregister($01000007);
+NR_O0 = tregister($01000008);
+NR_O1 = tregister($01000009);
+NR_O2 = tregister($0100000a);
+NR_O3 = tregister($0100000b);
+NR_O4 = tregister($0100000c);
+NR_O5 = tregister($0100000d);
+NR_O6 = tregister($0100000e);
+NR_O7 = tregister($0100000f);
+NR_L0 = tregister($01000010);
+NR_L1 = tregister($01000011);
+NR_L2 = tregister($01000012);
+NR_L3 = tregister($01000013);
+NR_L4 = tregister($01000014);
+NR_L5 = tregister($01000015);
+NR_L6 = tregister($01000016);
+NR_L7 = tregister($01000017);
+NR_I0 = tregister($01000018);
+NR_I1 = tregister($01000019);
+NR_I2 = tregister($0100001a);
+NR_I3 = tregister($0100001b);
+NR_I4 = tregister($0100001c);
+NR_I5 = tregister($0100001d);
+NR_I6 = tregister($0100001e);
+NR_I7 = tregister($0100001f);
 NR_FP = tregister($0104001e);
 NR_SP = tregister($0104000e);
 NR_F0 = tregister($02060000);
@@ -138,6 +138,8 @@ NR_PSR = tregister($05000004);
 NR_TBR = tregister($05000005);
 NR_WIM = tregister($05000006);
 NR_Y = tregister($05000007);
+NR_ICC = tregister($05000008);
+NR_XCC = tregister($05000009);
 NR_ASR0 = tregister($04000000);
 NR_ASR1 = tregister($04000001);
 NR_ASR2 = tregister($04000002);

compiler/sparc64/rsp64dwrf.inc

@@ -138,6 +138,8 @@
 67,
 66,
 64,
+63,
+62,
 32,
 32,
 32,

compiler/sparc64/rsp64nor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from spreg.dat }
-171
+173

compiler/sparc64/rsp64num.inc

@@ -138,6 +138,8 @@ NR_PSR,
 NR_TBR,
 NR_WIM,
 NR_Y,
+NR_ICC,
+NR_XCC,
 NR_ASR0,
 NR_ASR1,
 NR_ASR2,

compiler/sparc64/rsp64rni.inc

@@ -15,7 +15,6 @@
 13,
 14,
 15,
-34,
 16,
 17,
 18,
@@ -32,8 +31,9 @@
 29,
 30,
 31,
-33,
 32,
+34,
+33,
 35,
 36,
 37,
@@ -130,8 +130,6 @@
 128,
 129,
 130,
-139,
-140,
 141,
 142,
 143,
@@ -162,6 +160,8 @@
 168,
 169,
 170,
+171,
+172,
 131,
 132,
 133,
@@ -169,4 +169,6 @@
 135,
 136,
 137,
-138
+138,
+139,
+140

compiler/sparc64/rsp64sri.inc

@@ -1,8 +1,6 @@
 { don't edit, this file is generated from spreg.dat }
-139,
-140,
-149,
-150,
+141,
+142,
 151,
 152,
 153,
@@ -11,9 +9,9 @@
 156,
 157,
 158,
-141,
 159,
 160,
+143,
 161,
 162,
 163,
@@ -22,15 +20,17 @@
 166,
 167,
 168,
-142,
 169,
 170,
-143,
 144,
+171,
+172,
 145,
 146,
 147,
 148,
+149,
+150,
 99,
 100,
 109,
@@ -148,6 +148,7 @@
 30,
 31,
 32,
+139,
 17,
 18,
 19,
@@ -168,5 +169,6 @@
 34,
 136,
 137,
+140,
 138,
 0

compiler/sparc64/rsp64stab.inc

@@ -138,6 +138,8 @@
 67,
 66,
 64,
+63,
+62,
 32,
 32,
 32,

compiler/sparc64/rsp64std.inc

@@ -138,6 +138,8 @@
 '%tbr',
 '%wim',
 '%y',
+'%icc',
+'%xcc',
 '%asr0',
 '%asr1',
 '%asr2',

compiler/sparc64/rsp64sup.inc

@@ -138,6 +138,8 @@ RS_PSR = $04;
 RS_TBR = $05;
 RS_WIM = $06;
 RS_Y = $07;
+RS_ICC = $08;
+RS_XCC = $09;
 RS_ASR0 = $00;
 RS_ASR1 = $01;
 RS_ASR2 = $02;

compiler/sparcgen/cpubase.pas

@@ -64,7 +64,7 @@ uses
       {$i rspsup.inc}
 
       { No Subregisters }
-      R_SUBWHOLE = R_SUBD;
+      R_SUBWHOLE = R_SUBNONE;
 
       { Available Registers }
       {$i rspcon.inc}
@@ -103,7 +103,7 @@ uses
       {$i rsp64sup.inc}
 
       { No Subregisters }
-      R_SUBWHOLE = R_SUBQ;
+      R_SUBWHOLE = R_SUBNONE;
 
       { Available Registers }
       {$i rsp64con.inc}
@@ -429,9 +429,11 @@ implementation
             end;
           else
             begin
+{$ifdef SPARC32}
               if s in [OS_64,OS_S64] then
                 cgsize2subreg:=R_SUBQ
               else
+{$endif SPARC32}
                 cgsize2subreg:=R_SUBWHOLE;
             end;
         end;

compiler/sparcgen/spreg.dat

@@ -6,38 +6,38 @@
 ;
 NO,$00,$00,$00,INVALID,-1,-1
 ; Integer registers
-G0,$01,$04,$00,%g0,0,0
-G1,$01,$04,$01,%g1,1,1
-G2,$01,$04,$02,%g2,2,2
-G3,$01,$04,$03,%g3,3,3
-G4,$01,$04,$04,%g4,4,4
-G5,$01,$04,$05,%g5,5,5
-G6,$01,$04,$06,%g6,6,6
-G7,$01,$04,$07,%g7,7,7
-O0,$01,$04,$08,%o0,8,8
-O1,$01,$04,$09,%o1,9,9
-O2,$01,$04,$0a,%o2,10,10
-O3,$01,$04,$0b,%o3,11,11
-O4,$01,$04,$0c,%o4,12,12
-O5,$01,$04,$0d,%o5,13,13
-O6,$01,$04,$0e,%o6,14,14
-O7,$01,$04,$0f,%o7,15,15
-L0,$01,$04,$10,%l0,16,16
-L1,$01,$04,$11,%l1,17,17
-L2,$01,$04,$12,%l2,18,18
-L3,$01,$04,$13,%l3,19,19
-L4,$01,$04,$14,%l4,20,20
-L5,$01,$04,$15,%l5,21,21
-L6,$01,$04,$16,%l6,22,22
-L7,$01,$04,$17,%l7,23,23
-I0,$01,$04,$18,%i0,24,24
-I1,$01,$04,$19,%i1,25,25
-I2,$01,$04,$1a,%i2,26,26
-I3,$01,$04,$1b,%i3,27,27
-I4,$01,$04,$1c,%i4,28,28
-I5,$01,$04,$1d,%i5,29,29
-I6,$01,$04,$1e,%i6,30,30
-I7,$01,$04,$1f,%i7,31,31
+G0,$01,$00,$00,%g0,0,0
+G1,$01,$00,$01,%g1,1,1
+G2,$01,$00,$02,%g2,2,2
+G3,$01,$00,$03,%g3,3,3
+G4,$01,$00,$04,%g4,4,4
+G5,$01,$00,$05,%g5,5,5
+G6,$01,$00,$06,%g6,6,6
+G7,$01,$00,$07,%g7,7,7
+O0,$01,$00,$08,%o0,8,8
+O1,$01,$00,$09,%o1,9,9
+O2,$01,$00,$0a,%o2,10,10
+O3,$01,$00,$0b,%o3,11,11
+O4,$01,$00,$0c,%o4,12,12
+O5,$01,$00,$0d,%o5,13,13
+O6,$01,$00,$0e,%o6,14,14
+O7,$01,$00,$0f,%o7,15,15
+L0,$01,$00,$10,%l0,16,16
+L1,$01,$00,$11,%l1,17,17
+L2,$01,$00,$12,%l2,18,18
+L3,$01,$00,$13,%l3,19,19
+L4,$01,$00,$14,%l4,20,20
+L5,$01,$00,$15,%l5,21,21
+L6,$01,$00,$16,%l6,22,22
+L7,$01,$00,$17,%l7,23,23
+I0,$01,$00,$18,%i0,24,24
+I1,$01,$00,$19,%i1,25,25
+I2,$01,$00,$1a,%i2,26,26
+I3,$01,$00,$1b,%i3,27,27
+I4,$01,$00,$1c,%i4,28,28
+I5,$01,$00,$1d,%i5,29,29
+I6,$01,$00,$1e,%i6,30,30
+I7,$01,$00,$1f,%i7,31,31
 ; Aliases for stackpointer (%o6) and framepointer (%i6)
 FP,$01,$04,$1e,%fp,30,30
 SP,$01,$04,$0e,%sp,14,14
@@ -152,6 +152,8 @@ PSR,$05,$00,$04,%psr,65,65
 TBR,$05,$00,$05,%tbr,67,67
 WIM,$05,$00,$06,%wim,66,66
 Y,$05,$00,$07,%y,64,64
+ICC,$05,$00,$08,%icc,63,63,SPARC64
+XCC,$05,$00,$09,%xcc,62,62,SPARC64
 
 ; Ancillary State Registers
 ASR0,$04,$00,$00,%asr0,32,32