+ support for nop, msr and mrs instructions

git-svn-id: trunk@12609 -

compiler/arm/armatt.inc

@@ -47,11 +47,14 @@
 'mcr',
 'mla',
 'mov',
+'mrs',
+'msr',
 'mnf',
 'muf',
 'mul',
 'mvf',
 'mvn',
+'nop',
 'orr',
 'rdf',
 'rfs',

compiler/arm/armatts.inc

@@ -174,5 +174,8 @@ attsufNONE,
 attsufNONE,
 attsufNONE,
 attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
 attsufNONE
 );

compiler/arm/armins.dat

@@ -246,13 +246,13 @@ reg32,reg32,reg32,reg32  \x15\x00\x20\x90               ARM7
 ; [MRC]
 ; reg32,reg32         \321\301\1\x13\110                  ARM7
 
-; [MRScc]
-; reg32,reg32         \x10\x01\x0F                        ARM7
+[MRScc]
+reg32,reg32         \x10\x01\x0F                        ARM7
 
-; [MSRcc]
-; reg32,reg32         \x11\x01\x29\xF0                    ARM7
-; regf,reg32          \x12\x01\x28\xF0                    ARM7
-; regf,imm            \x13\x03\x28\xF0                    ARM7
+[MSRcc]
+reg32,reg32         \x11\x01\x29\xF0                    ARM7
+regf,reg32          \x12\x01\x28\xF0                    ARM7
+regf,imm            \x13\x03\x28\xF0                    ARM7
 
 [MNFcc]
 
@@ -271,6 +271,8 @@ fpureg,immfpu              \xF2                      FPA
 ; reg32,reg32,imm     \xA\x1\xE0                     ARM7
 ; reg32,imm           \xB\x3\xE0                     ARM7
 
+[NOP]
+
 [ORRcc]
 reg32,reg32,reg32        \4\x1\x80                     ARM7
 reg32,reg32,reg32,reg32  \5\x1\x80                     ARM7

compiler/arm/armnop.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armins.dat }
-102;
+106;

compiler/arm/armop.inc

@@ -47,11 +47,14 @@ A_LOG,
 A_MCR,
 A_MLA,
 A_MOV,
+A_MRS,
+A_MSR,
 A_MNF,
 A_MUF,
 A_MUL,
 A_MVF,
 A_MVN,
+A_NOP,
 A_ORR,
 A_RDF,
 A_RFS,

compiler/arm/armtab.inc

@@ -399,6 +399,34 @@
     code    : #21#0#32#144;
     flags   : if_arm7
   ),
+  (
+    opcode  : A_MRS;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #16#1#15;
+    flags   : if_arm7
+  ),
+  (
+    opcode  : A_MSR;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #17#1#41#240;
+    flags   : if_arm7
+  ),
+  (
+    opcode  : A_MSR;
+    ops     : 2;
+    optypes : (ot_regf,ot_reg32,ot_none,ot_none);
+    code    : #18#1#40#240;
+    flags   : if_arm7
+  ),
+  (
+    opcode  : A_MSR;
+    ops     : 2;
+    optypes : (ot_regf,ot_immediate,ot_none,ot_none);
+    code    : #19#3#40#240;
+    flags   : if_arm7
+  ),
   (
     opcode  : A_MUL;
     ops     : 3;