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@@ -55,7 +55,7 @@ implementation
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cgbase,cgobj,temp_gen,pass_1,pass_2,
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ncon,
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cpubase,
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- cga,tgcpu,nppcutil,cgcpu;
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+ cga,tgcpu,nppcutil,cgcpu,cg64f32;
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{*****************************************************************************
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TPPCMODDIVNODE
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@@ -118,7 +118,7 @@ implementation
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{ n = -13, (0xFFFF_FFF3), and k = 2, after executing the srawi }
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{ instruction, q = -4 (0xFFFF_FFFC) and CA = 1. After executing }
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{ the addze instruction, q = -3, the correct quotient. }
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- cg.a_op_reg_reg_reg(OP_SAR,power,numerator,resultreg);
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+ cg.a_op_const_reg_reg(list,OP_SAR,OS_32,aword(power),numerator,resultreg);
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exprasmlist.concat(taicpu.op_reg_reg(A_ADDZE,resultreg,resultreg));
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end
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else
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@@ -137,7 +137,8 @@ implementation
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end;
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{ needs overflow checking, (-maxlongint-1) div (-1) overflows! }
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- { (JM) }
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+ { And on PPC, the only way to catch a div-by-0 is by checking }
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+ { the overflow flag (JM) }
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op := divops[is_signed(right.resulttype.def),
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cs_check_overflow in aktlocalswitches];
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exprasmlist(taicpu.op_reg_reg_reg(op,resultreg,numerator,
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@@ -163,9 +164,11 @@ implementation
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procedure tppcshlshrnode.pass_2;
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var
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- resultreg, hregister1,hregister2,hregister3,
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+ resultreg, hregister1,hregister2,
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hregisterhigh,hregisterlow : tregister;
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op : topcg;
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+ asmop1, asmop2: tasmop;
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+ shiftval: aword;
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saved : boolean;
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begin
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@@ -177,7 +180,135 @@ implementation
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if is_64bitint(left.resulttype.def) then
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begin
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- { see green book appendix E, still needs to be implemented }
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+ case left.location.loc of
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+ LOC_REGISTER, LOC_CREGISTER:
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+ begin
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+ hregisterhigh := left.location.registerhigh;
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+ hregisterlow := left.location.registerlow;
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+ if left.location.loc = LOC_REGISTER then
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+ begin
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+ location.registerhigh := hregisterhigh;
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+ location.registerlow := hregisterlow
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+ end
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+ else
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+ begin
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+ location.registerhigh := getregisterint;
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+ location.registerlow := getregisterint;
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+ end;
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+ end;
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+ LOC_REFERENCE,LOC_MEM:
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+ begin
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+ { !!!!!!!! not good, registers are release too soon this way !!!! (JM) }
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+ del_reference(left.location.reference);
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+ hregisterhigh := getregisterint;
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+ location.registerhigh := hregisterhigh;
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+ hregisterlow := getregisterint;
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+ location.registerlow := hregisterlow;
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+ tcg64f32(cg).a_load64_ref_reg(list,left.location.reference,
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+ hregisterlow,hregisterhigh);
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+ end;
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+ end;
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+ if (right.nodetype = ordconstn) then
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+ begin
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+ if tordconstnode(right).value > 31 then
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+ begin
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+ if nodetype = shln then
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+ begin
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+ if (value and 31) <> 0 then
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+ cg.a_op_const_reg_reg(exprasmlist,OP_SHL,OS_32,value and 31,
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+ hregisterlow,location.registerhigh)
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+ cg.a_load_const_reg(exprasmlist,OS_32,0,location.registerlow);
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+ end
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+ else
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+ begin
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+ if (value and 31) <> 0 then
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+ cg.a_op_const_reg_reg(exprasmlist,OP_SHR,OS_32,value and 31,
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+ hregisterhigh,location.registerlow);
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+ cg.a_load_const_reg(exprasmlist,OS_32,0,location.registerhigh);
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+ end;
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+ end
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+ else
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+ begin
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+ shiftval := aword(tordconstnode(right).value;
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+ if nodetype = shln then
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+ begin
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+ exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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+ A_RLWINM,location.registerhigh,hregisterhigh,shiftval,
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+ 0,31-shiftval));
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+ exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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+ A_RLWIMI,location.registerhigh,hregisterlow,shiftval,
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+ 32-shiftval,31));
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+ exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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+ A_RLWINM,location.registerlow,hregisterlow,shiftval,
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+ 0,31-shiftval));
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+ end
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+ else
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+ begin
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+ exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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+ A_RLWINM,location.registerlow,hregisterlow,32-shiftval,
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+ shiftval,31));
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+ exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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+ A_RLWIMI,location.registerlow,hregisterhigh,32-shiftval,
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+ 0,shiftval-1));
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+ exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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+ A_RLWINM,location.registerhigh,hregisterhigh,32-shiftval,
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+ shiftval,31));
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+ end;
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+ end;
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+ end
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+ else
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+ { no constant shiftcount }
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+ begin
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+ case right.location.loc of
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+ LOC_REGISTER,LOC_CREGISTER:
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+ begin
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+ hregister1 := right.location.register;
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+ end;
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+ LOC_REFERENCE,LOC_MEM:
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+ begin
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+ hregister1 := get_scratch_reg(exprasmlist);
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+ cg.a_load_ref_reg(exprasmlist,OS_S32,
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+ right.location.reference,hregister1);
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+ end;
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+ end;
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+ if nodetype = shln then
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+ begin
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+ asmop1 := A_SLW;
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+ asmop2 := A_SRW;
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+ end
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+ else
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+ begin
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+ asmop1 := A_SRW;
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+ asmop2 := A_SLW;
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+ resultreg := location.registerhigh;
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+ location.registerhigh := location.registerlow;
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+ location.registerlow := resultreg;
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+ end;
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+
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+ getexplicitregisterint(R_0);
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+ exprasmlist.concat(taicpu.op_reg_reg_const(A_SUBFIC,
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+ R_0,hregister1,32));
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+ exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,
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+ location.registerhigh,hregisterhigh,hregister1));
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+ exprasmlist.concat(taicpu.op_reg_reg_reg(asmop2,
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+ R_0,hregisterlow,R_0));
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+ exprasmlist.concat(taicpu.op_reg_reg_reg(A_OR,
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+ location.registerhigh,location.registerhigh,R_0));
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+ exprasmlist.concat(taicpu.op_reg_reg_const(A_SUBI,
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+ R_0,hregister1,32));
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+ exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,
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+ R_0,hregisterlow,R_0));
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+ exprasmlist.concat(taicpu.op_reg_reg_reg(A_OR,
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+ location.registerhigh,location.registerhigh,R_0));
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+ exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,
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+ location.registerlow,hregisterlow,hregister1));
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+ ungetregister(R_0);
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+
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+ if right.location.loc in [LOC_MEM,LOC_REFERENCE] then
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+ free_scratch_reg(exprasmlist,hregister1)
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+ else
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+ ungetregister(hregister1);
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+ end
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end
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else
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begin
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@@ -480,7 +611,10 @@ begin
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end.
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{
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$Log$
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- Revision 1.1 2001-12-29 15:28:58 jonas
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+ Revision 1.2 2002-01-03 14:57:52 jonas
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+ * completed (not compilale yet though)
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+
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+ Revision 1.1 2001/12/29 15:28:58 jonas
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* powerpc/cgcpu.pas compiles :)
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* several powerpc-related fixes
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* cpuasm unit is now based on common tainst unit
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Jonas Maebe