+ Xtensa: patch by Christo Crause to add optional MAC16 registers, resolves #37130

git-svn-id: trunk@45679 -

.gitattributes

@@ -18329,6 +18329,7 @@ tests/webtbs/tw37095.pp svneol=native#text/plain
 tests/webtbs/tw37095d/uw37095.pp svneol=native#text/plain
 tests/webtbs/tw37099.pp svneol=native#text/pascal
 tests/webtbs/tw37107.pp svneol=native#text/pascal
+tests/webtbs/tw37130.pp svneol=native#text/pascal
 tests/webtbs/tw37136.pp svneol=native#text/pascal
 tests/webtbs/tw37154.pp svneol=native#text/pascal
 tests/webtbs/tw3719.pp svneol=native#text/plain

compiler/cgbase.pas

@@ -212,7 +212,13 @@ interface
         { used on llvm, every temp gets its own "base register" }
         R_TEMPREGISTER,    { = 7 }
         { used on llvm for tracking metadata (every unique metadata has its own base register) }
-        R_METADATAREGISTER { = 8 }
+        R_METADATAREGISTER,{ = 8 }
+        { optional MAC16 (16 bit multiply-accumulate) registers on Xtensa }
+        R_MAC16REGISTER    { = 9 }
+
+        { do not add more than 16 elements (ifdef by cpu type if needed)
+          so we can store this in one nibble and pack TRegister
+          if the supreg width should be extended }
       );
 
       { Sub registers }

compiler/x86/aasmcpu.pas

@@ -2474,9 +2474,9 @@ implementation
           (0, 1, 2, 3, 6, 7, 5, 4);
         maxsupreg: array[tregistertype] of tsuperregister=
 {$ifdef x86_64}
-          (0, 16, 9, 8, 32, 32, 8, 0, 0);
+          (0, 16, 9, 8, 32, 32, 8, 0, 0, 0);
 {$else x86_64}
-          (0,  8, 9, 8,  8, 32, 8, 0, 0);
+          (0,  8, 9, 8,  8, 32, 8, 0, 0, 0);
 {$endif x86_64}
       var
         rs: tsuperregister;

compiler/xtensa/rxtensacon.inc

@@ -48,3 +48,7 @@ NR_B12 = tregister($0500000c);
 NR_B13 = tregister($0500000d);
 NR_B14 = tregister($0500000e);
 NR_B15 = tregister($0500000f);
+NR_M0 = tregister($09000000);
+NR_M1 = tregister($09000001);
+NR_M2 = tregister($09000002);
+NR_M3 = tregister($09000003);

compiler/xtensa/rxtensadwa.inc

@@ -47,4 +47,8 @@
 12,
 13,
 14,
-15
+15,
+0,
+1,
+2,
+3

compiler/xtensa/rxtensanor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from xtensareg.dat }
-49
+53

compiler/xtensa/rxtensanum.inc

@@ -47,4 +47,8 @@ tregister($0500000b),
 tregister($0500000c),
 tregister($0500000d),
 tregister($0500000e),
-tregister($0500000f)
+tregister($0500000f),
+tregister($09000000),
+tregister($09000001),
+tregister($09000002),
+tregister($09000003)

compiler/xtensa/rxtensarni.inc

@@ -47,4 +47,8 @@
 45,
 46,
 47,
-48
+48,
+49,
+50,
+51,
+52

compiler/xtensa/rxtensasri.inc

@@ -47,4 +47,8 @@
 23,
 24,
 25,
-26
+26,
+49,
+50,
+51,
+52

compiler/xtensa/rxtensasta.inc

@@ -47,4 +47,8 @@
 12,
 13,
 14,
-15
+15,
+0,
+1,
+2,
+3

compiler/xtensa/rxtensastd.inc

@@ -47,4 +47,8 @@
 'b12',
 'b13',
 'b14',
-'b15'
+'b15',
+'m0',
+'m1',
+'m2',
+'m3'

compiler/xtensa/rxtensasup.inc

@@ -48,3 +48,7 @@ RS_B12 = $0c;
 RS_B13 = $0d;
 RS_B14 = $0e;
 RS_B15 = $0f;
+RS_M0 = $00;
+RS_M1 = $01;
+RS_M2 = $02;
+RS_M3 = $03;

compiler/xtensa/xtensareg.dat

@@ -59,3 +59,9 @@ B13,$05,$00,$0d,b13,13,13
 B14,$05,$00,$0e,b14,14,14
 B15,$05,$00,$0f,b15,15,15
 
+; MAC16 registers
+M0,$09,$00,$00,m0,0,0
+M1,$09,$00,$01,m1,1,1
+M2,$09,$00,$02,m2,2,2
+M3,$09,$00,$03,m3,3,3
+

tests/webtbs/tw37130.pp

@@ -0,0 +1,26 @@
+{ %cpu=xtensa }
+{ %norun }
+unit mac16test;
+
+interface
+
+procedure testMAC16;
+
+implementation
+
+procedure testMAC16; assembler;
+asm
+  mula.aa.ll a3, a4
+  mula.ad.ll a3, m2                // my in [m2, m3]
+  mula.da.ll m1, a3                // mx in [m0, m1]
+  mula.dd.ll m1, m3                // mx in [m0, m1], my in [m2, m3]
+  mula.da.ll.lddec m1, a5, m3, a6  // mw in [m0..m3], mx in [m0, m1], my in [m2, m3]
+  mula.dd.ll.ldinc m3, a5, m0, m2  // mw in [m0..m3], mx in [m0, m1], my in [m2, m3]
+  muls.aa.hh a4, a5
+  muls.ad.hl a4, m2                // my in [m2, m3]
+  muls.da.lh m0, a4                // mx in [m0, m1]
+  muls.dd.hl m0, m2                // mx in [m0, m1], my in [m2, m3]
+end;
+
+end.
+