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@@ -480,10 +480,22 @@ unit cgx86;
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var
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op: tasmop;
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s: topsize;
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+ eq:boolean;
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begin
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- sizes2load(fromsize,reg2opsize[reg2.enum],op,s);
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- if (rg.makeregsize(reg1,OS_INT).enum = rg.makeregsize(reg2,OS_INT).enum) then
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+ if (reg1.enum=R_INTREGISTER) and (reg2.enum=R_INTREGISTER) then
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+ begin
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+ sizes2load(fromsize,subreg2opsize[reg2.number and $ff],op,s);
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+ eq:=(reg1.number shr 8)=(reg2.number shr 8);
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+ end
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+ else if (reg1.enum<lastreg) and (reg2.enum<lastreg) then
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+ begin
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+ sizes2load(fromsize,reg2opsize[reg2.enum],op,s);
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+ eq:=(rg.makeregsize(reg1,OS_INT).enum = rg.makeregsize(reg2,OS_INT).enum);
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+ end
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+ else
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+ internalerror(200301081);
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+ if eq then
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begin
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{ "mov reg1, reg1" doesn't make sense }
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if op = A_MOV then
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@@ -787,6 +799,7 @@ unit cgx86;
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internalerror(200301081);
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if dst.enum>lastreg then
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internalerror(200301081);
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+ r.enum:=R_INTREGISTER;
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dstsize := tcgsize2opsize[size];
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dst := rg.makeregsize(dst,size);
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case op of
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@@ -820,23 +833,22 @@ unit cgx86;
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begin
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{ is ecx still free (it's also free if it was allocated }
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{ to dst, since we've moved dst somewhere else already) }
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+ r.number:=NR_ECX;
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if not((dst.enum = R_ECX) or
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((R_ECX in rg.unusedregsint) and
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{ this will always be true, it's just here to }
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{ allocate ecx }
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(rg.getexplicitregisterint(list,R_ECX).enum = R_ECX))) then
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begin
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- r.enum:=R_ECX;
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list.concat(taicpu.op_reg(A_PUSH,S_L,r));
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popecx := true;
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end;
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- r.enum:=R_ECX;
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a_load_reg_reg(list,OS_32,OS_32,rg.makeregsize(src,OS_32),r);
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end
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else
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src.enum := R_CL;
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{ do the shift }
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- r.enum:=R_CL;
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+ r.number:=NR_CL;
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if tmpreg.enum = R_NO then
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list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],dstsize,
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r,dst))
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@@ -845,11 +857,11 @@ unit cgx86;
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list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],S_L,
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r,tmpreg));
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{ move result back to the destination }
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- r.enum:=R_ECX;
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+ r.number:=NR_ECX;
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a_load_reg_reg(list,OS_32,OS_32,tmpreg,r);
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free_scratch_reg(list,tmpreg);
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end;
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- r.enum:=R_ECX;
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+ r.number:=NR_ECX;
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if popecx then
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list.concat(taicpu.op_reg(A_POP,S_L,r))
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else if not (dst.enum in [R_ECX,R_CX,R_CL]) then
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@@ -1133,7 +1145,8 @@ unit cgx86;
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var r:Tregister;
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begin
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- r.enum:=R_ECX;
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+ r.enum:=R_INTREGISTER;
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+ r.number:=NR_ECX;
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if not(R_ECX in rg.unusedregsint) then
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begin
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list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
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@@ -1147,13 +1160,14 @@ unit cgx86;
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((len<=8) or
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(not(cs_littlesize in aktglobalswitches ) and (len<=12))) then
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begin
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+ r.enum:=R_INTREGISTER;
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helpsize:=len shr 2;
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rg.getexplicitregisterint(list,R_EDI);
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dstref:=dest;
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srcref:=source;
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for i:=1 to helpsize do
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begin
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- r.enum:=R_EDI;
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+ r.number:=NR_EDI;
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a_load_ref_reg(list,OS_32,srcref,r);
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If (len = 4) and delsource then
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reference_release(list,source);
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@@ -1164,7 +1178,7 @@ unit cgx86;
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end;
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if len>1 then
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begin
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- r.enum:=R_DI;
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+ r.number:=NR_DI;
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a_load_ref_reg(list,OS_16,srcref,r);
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If (len = 2) and delsource then
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reference_release(list,source);
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@@ -1175,6 +1189,9 @@ unit cgx86;
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end;
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r.enum:=R_EDI;
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rg.ungetregisterint(list,r);
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+ r.enum:=R_INTREGISTER;
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+ reg8.enum:=R_INTREGISTER;
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+ reg32.enum:=R_INTREGISTER;
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if len>0 then
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begin
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{ and now look for an 8 bit register }
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@@ -1190,25 +1207,25 @@ unit cgx86;
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{ one is always not index or base }
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if (dest.base.enum<>R_EAX) and (dest.index.enum<>R_EAX) then
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begin
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- reg8.enum:=R_AL;
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- reg32.enum:=R_EAX;
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+ reg8.number:=NR_AL;
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+ reg32.number:=NR_EAX;
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end
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else if (dest.base.enum<>R_EBX) and (dest.index.enum<>R_EBX) then
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begin
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- reg8.enum:=R_BL;
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- reg32.enum:=R_EBX;
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+ reg8.number:=NR_BL;
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+ reg32.number:=NR_EBX;
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end
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else if (dest.base.enum<>R_ECX) and (dest.index.enum<>R_ECX) then
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begin
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- reg8.enum:=R_CL;
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- reg32.enum:=R_ECX;
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+ reg8.number:=NR_CL;
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+ reg32.number:=NR_ECX;
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end;
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end;
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if swap then
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{ was earlier XCHG, of course nonsense }
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begin
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rg.getexplicitregisterint(list,R_EDI);
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- r.enum:=R_EDI;
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+ r.number:=NR_EDI;
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a_load_reg_reg(list,OS_32,OS_32,reg32,r);
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end;
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a_load_ref_reg(list,OS_8,srcref,reg8);
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@@ -1217,21 +1234,31 @@ unit cgx86;
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a_load_reg_ref(list,OS_8,reg8,dstref);
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if swap then
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begin
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- r.enum:=R_EDI;
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+ r.number:=NR_EDI;
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a_load_reg_reg(list,OS_32,OS_32,r,reg32);
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+ r.enum:=R_EDI;
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rg.ungetregisterint(list,r);
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end
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else
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- rg.ungetregister(list,reg8);
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+ begin
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+ if reg8.number=NR_AL then
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+ reg8.enum:=R_AL
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+ else if reg8.number=NR_BL then
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+ reg8.enum:=R_BL
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+ else if reg8.number=NR_CL then
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+ reg8.enum:=R_CL;
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+ rg.ungetregister(list,reg8);
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+ end;
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end;
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end
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else
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begin
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- r.enum:=R_EDI;
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+ r.enum:=R_INTREGISTER;
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+ r.number:=NR_EDI;
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rg.getexplicitregisterint(list,R_EDI);
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a_loadaddr_ref_reg(list,dest,r);
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- r.enum:=R_ESI;
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- list.concat(tai_regalloc.Alloc(r));
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+ r.number:=NR_ESI;
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+ list.concat(tai_regalloc.alloc(r));
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if loadref then
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a_load_ref_reg(list,OS_ADDR,source,r)
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else
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@@ -1243,7 +1270,7 @@ unit cgx86;
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list.concat(Taicpu.Op_none(A_CLD,S_NO));
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ecxpushed:=false;
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- r.enum:=R_ECX;
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+ r.number:=NR_ECX;
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if cs_littlesize in aktglobalswitches then
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begin
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maybepushecx;
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@@ -1273,13 +1300,19 @@ unit cgx86;
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end;
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r.enum:=R_EDI;
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rg.ungetregisterint(list,r);
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- r.enum:=R_ESI;
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- list.concat(tai_regalloc.DeAlloc(r));
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- r.enum:=R_ECX;
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+ r.enum:=R_INTREGISTER;
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+ r.number:=NR_ESI;
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+ list.concat(tai_regalloc.dealloc(r));
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if ecxpushed then
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- list.concat(Taicpu.Op_reg(A_POP,S_L,r))
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+ begin
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+ r.number:=NR_ECX;
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+ list.concat(Taicpu.Op_reg(A_POP,S_L,r))
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+ end
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else
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- rg.ungetregisterint(list,r);
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+ begin
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+ r.enum:=R_ECX;
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+ rg.ungetregisterint(list,r);
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+ end;
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{ loading SELF-reference again }
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g_maybe_loadself(list);
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@@ -1295,7 +1328,8 @@ unit cgx86;
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var r:Tregister;
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begin
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- r.enum:=R_EAX;
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+ r.enum:=R_INTREGISTER;
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+ r.number:=NR_EAX;
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list.concat(Taicpu.op_reg(A_PUSH,S_L,r));
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end;
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@@ -1310,7 +1344,8 @@ unit cgx86;
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var r:Tregister;
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begin
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- r.enum:=R_EAX;
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+ r.enum:=R_INTREGISTER;
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+ r.number:=NR_EAX;
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list.concat(Taicpu.op_reg(A_POP,S_L,r));
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end;
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@@ -1469,27 +1504,27 @@ unit cgx86;
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begin
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r.enum:=R_INTREGISTER;
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- r.enum:=R_GS;
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+ r.number:=NR_GS;
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{ .... also the segment registers }
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list.concat(Taicpu.Op_reg(A_PUSH,S_W,r));
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- r.enum:=R_FS;
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+ r.number:=NR_FS;
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list.concat(Taicpu.Op_reg(A_PUSH,S_W,r));
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- r.enum:=R_ES;
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+ r.number:=NR_ES;
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list.concat(Taicpu.Op_reg(A_PUSH,S_W,r));
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- r.enum:=R_DS;
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+ r.number:=NR_DS;
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list.concat(Taicpu.Op_reg(A_PUSH,S_W,r));
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{ save the registers of an interrupt procedure }
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- r.enum:=R_EDI;
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+ r.number:=NR_EDI;
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list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
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- r.enum:=R_ESI;
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+ r.number:=NR_ESI;
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list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
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- r.enum:=R_EDX;
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+ r.number:=NR_EDX;
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list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
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- r.enum:=R_ECX;
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+ r.number:=NR_ECX;
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list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
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- r.enum:=R_EBX;
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+ r.number:=NR_EBX;
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list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
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- r.enum:=R_EAX;
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+ r.number:=NR_EAX;
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list.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
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end;
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@@ -1687,7 +1722,8 @@ unit cgx86;
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var r:Tregister;
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begin
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- r.enum:=R_EDI;
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+ r.enum:=R_INTREGISTER;
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+ r.number:=NR_EDI;
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if is_class(procinfo._class) then
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begin
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if (cs_implicit_exceptions in aktmoduleswitches) then
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@@ -1874,7 +1910,11 @@ unit cgx86;
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end.
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{
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$Log$
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- Revision 1.28 2003-01-09 20:41:00 daniel
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+ Revision 1.29 2003-01-13 14:54:34 daniel
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+ * Further work to convert codegenerator register convention;
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+ internalerror bug fixed.
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+
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+ Revision 1.28 2003/01/09 20:41:00 daniel
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* Converted some code in cgx86.pas to new register numbering
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Revision 1.27 2003/01/08 18:43:58 daniel
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daniel