Add a lot of instruction table entries and missing instructions for support of most ARM32 mode instructions from ARMv4 up ARMv7A.

Add some VFP registers.
Rebuilt tables.
Added a lot of VFPv3 and Advanced SIMD(not supported yet) oppostfixes.
Implemented code in aasmcpu to generate binary code from the instructions. Only ARM32 supported so far.

git-svn-id: branches/laksen/armiw@29246 -

compiler/arm/aasmcpu.pas

@@ -102,14 +102,17 @@ uses
       OT_AM4       = $00040000;
       { co proc. ld/st operations }
       OT_AM5       = $00080000;
-      OT_AMMASK    = $000f0000;
+      { exclusive ld/st operations }
+      OT_AM6       = $00100000;
+      OT_AMMASK    = $001f0000;
       { IT instruction }
-      OT_CONDITION = $00100000;
+      OT_CONDITION = $00200000;
 
       OT_MEMORYAM2 = OT_MEMORY or OT_AM2;
       OT_MEMORYAM3 = OT_MEMORY or OT_AM3;
       OT_MEMORYAM4 = OT_MEMORY or OT_AM4;
       OT_MEMORYAM5 = OT_MEMORY or OT_AM5;
+      OT_MEMORYAM6 = OT_MEMORY or OT_AM6;
 
       OT_FPUREG    = $01000000;  { floating point stack registers  }
       OT_REG_SMASK = $00070000;  { special register operands: these may be treated differently  }
@@ -128,9 +131,32 @@ uses
       IF_NONE   = $00000000;
 
       IF_ARMMASK    = $000F0000;
-      IF_ARM7       = $00070000;
-      IF_FPMASK     = $00F00000;
-      IF_FPA        = $00100000;
+      IF_ARM32      = $00010000;
+      IF_THUMB      = $00020000;
+      IF_THUMB32    = $00040000;
+
+      IF_ARMvMASK   = $0FF00000;
+      IF_ARMv4      = $00100000;
+      IF_ARMv4T     = $00200000;
+      IF_ARMv5      = $00300000;
+      IF_ARMv5T     = $00400000;
+      IF_ARMv5TE    = $00500000;
+      IF_ARMv5TEJ   = $00600000;
+      IF_ARMv6      = $00700000;
+      IF_ARMv6K     = $00800000;
+      IF_ARMv6T2    = $00900000;
+      IF_ARMv6Z     = $00A00000;
+      IF_ARMv6M     = $00B00000;
+      IF_ARMv7      = $00C00000;
+      IF_ARMv7A     = $00D00000;
+      IF_ARMv7R     = $00E00000;
+      IF_ARMv7M     = $00F00000;
+      IF_ARMv7EM    = $01000000;
+
+      IF_FPMASK     = $F0000000;
+      IF_FPA        = $10000000;
+      IF_VFPv2      = $20000000;
+      IF_VFPv3      = $40000000;
 
       { if the instruction can change in a second pass }
       IF_PASS2  = longint($80000000);
@@ -142,7 +168,7 @@ uses
       tinsentry = record
         opcode  : tasmop;
         ops     : byte;
-        optypes : array[0..3] of longint;
+        optypes : array[0..5] of longint;
         code    : array[0..maxinfolen] of char;
         flags   : longint;
       end;
@@ -614,9 +640,10 @@ implementation
         result:=(
                   ((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
                   ((opcode=A_MVF) and (regtype = R_FPUREGISTER)) or
-                  ((opcode in [A_FCPYS, A_FCPYD]) and (regtype = R_MMREGISTER))
+                  ((opcode in [A_FCPYS, A_FCPYD]) and (regtype = R_MMREGISTER)) or
+                  ((opcode in [A_VMOV]) and (regtype = R_MMREGISTER) and (oppostfix in [PF_F32,PF_F64]))
                 ) and
-                (oppostfix in [PF_None,PF_D]) and
+                ((oppostfix in [PF_None,PF_D]) or (opcode = A_VMOV)) and
                 (condition=C_None) and
                 (ops=2) and
                 (oper[0]^.typ=top_reg) and
@@ -626,8 +653,6 @@ implementation
 
 
     function spilling_create_load(const ref:treference;r:tregister):Taicpu;
-      var
-        op: tasmop;
       begin
         case getregtype(r) of
           R_INTREGISTER :
@@ -638,19 +663,7 @@ implementation
             }
             result:=taicpu.op_reg_const_ref(A_LFM,r,1,ref);
           R_MMREGISTER :
-            begin
-              case getsubreg(r) of
-                R_SUBFD:
-                  op:=A_FLDD;
-                R_SUBFS:
-                  op:=A_FLDS;
-                R_SUBNONE:
-                  op:=A_VLDR;
-                else
-                  internalerror(2009112905);
-              end;
-              result:=taicpu.op_reg_ref(op,r,ref);
-            end;
+            result:=taicpu.op_reg_ref(A_VLDR,r,ref);
           else
             internalerror(200401041);
         end;
@@ -658,8 +671,6 @@ implementation
 
 
     function spilling_create_store(r:tregister; const ref:treference):Taicpu;
-      var
-        op: tasmop;
       begin
         case getregtype(r) of
           R_INTREGISTER :
@@ -670,19 +681,7 @@ implementation
             }
             result:=taicpu.op_reg_const_ref(A_SFM,r,1,ref);
           R_MMREGISTER :
-            begin
-              case getsubreg(r) of
-                R_SUBFD:
-                  op:=A_FSTD;
-                R_SUBFS:
-                  op:=A_FSTS;
-                R_SUBNONE:
-                  op:=A_VSTR;
-                else
-                  internalerror(2009112904);
-              end;
-              result:=taicpu.op_reg_ref(op,r,ref);
-            end;
+            result:=taicpu.op_reg_ref(A_VSTR,r,ref);
           else
             internalerror(200401041);
         end;
@@ -786,10 +785,21 @@ implementation
       end;
 
 
+    var
+      IF_ArmInsVersion: longword;
+
+
     procedure BuildInsTabCache;
       var
         i : longint;
       begin
+        if GenerateThumb2Code then
+          IF_ArmInsVersion:=IF_THUMB32
+        else if GenerateThumbCode then
+          IF_ArmInsVersion:=IF_THUMB
+        else
+          IF_ArmInsVersion:=IF_ARM32;
+
         new(instabcache);
         FillChar(instabcache^,sizeof(tinstabcache),$ff);
         i:=0;
@@ -1366,6 +1376,48 @@ implementation
           end;
       end;
 
+    procedure fix_invalid_imms(list: TAsmList);
+      var
+        curtai: tai;
+        sh: byte;
+      begin
+        curtai:=tai(list.First);
+        while assigned(curtai) do
+          begin
+            case curtai.typ of
+              ait_instruction:
+                begin
+                  if (taicpu(curtai).opcode in [A_AND,A_BIC]) and
+                     (taicpu(curtai).ops=3) and
+                     (taicpu(curtai).oper[2]^.typ=top_const) and
+                     (not is_shifter_const(taicpu(curtai).oper[2]^.val,sh)) and
+                     is_shifter_const((not taicpu(curtai).oper[2]^.val) and $FFFFFFFF,sh) then
+                    begin
+                      case taicpu(curtai).opcode of
+                        A_AND: taicpu(curtai).opcode:=A_BIC;
+                        A_BIC: taicpu(curtai).opcode:=A_AND;
+                      end;
+                      taicpu(curtai).oper[2]^.val:=(not taicpu(curtai).oper[2]^.val) and $FFFFFFFF;
+                    end
+                  else if (taicpu(curtai).opcode in [A_SUB,A_ADD]) and
+                     (taicpu(curtai).ops=3) and
+                     (taicpu(curtai).oper[2]^.typ=top_const) and
+                     (not is_shifter_const(taicpu(curtai).oper[2]^.val,sh)) and
+                     is_shifter_const(-taicpu(curtai).oper[2]^.val,sh) then
+                    begin
+                      case taicpu(curtai).opcode of
+                        A_ADD: taicpu(curtai).opcode:=A_SUB;
+                        A_SUB: taicpu(curtai).opcode:=A_ADD;
+                      end;
+                      taicpu(curtai).oper[2]^.val:=-taicpu(curtai).oper[2]^.val;
+                    end;
+                end;
+            end;
+
+            curtai:=tai(curtai.Next);
+          end;
+      end;
+
     procedure finalizearmcode(list, listtoinsert: TAsmList);
       begin
         { Do Thumb-2 16bit -> 32bit transformations }
@@ -1375,6 +1427,8 @@ implementation
             foldITInstructions(list);
           end;
 
+        fix_invalid_imms(list);
+
         insertpcrelativedata(list, listtoinsert);
       end;
 
@@ -1569,6 +1623,9 @@ implementation
                else
                  if (ot and OT_FPUREG)=OT_FPUREG then
                   s:=s+'fpureg'
+               else
+                 if (ot and OT_REGF)=OT_REGF then
+                  s:=s+'creg'
                else
                 if (ot and OT_REGISTER)=OT_REGISTER then
                  begin
@@ -1593,9 +1650,17 @@ implementation
                    s:=s+'mem';
                    addsize:=true;
                    if (ot and OT_AM2)<>0 then
+                     s:=s+' am2 '
+                   else if (ot and OT_AM6)<>0 then
                      s:=s+' am2 ';
                  end
                else
+                 if (ot and OT_SHIFTEROP)=OT_SHIFTEROP then
+                  begin
+                    s:=s+'shifterop';
+                    addsize:=false;
+                  end
+                else
                  s:=s+'???';
                { size }
                if addsize then
@@ -1670,7 +1735,12 @@ implementation
         current_filepos:=fileinfo;
 
         { tranlate LDR+postfix to complete opcode }
-        if (opcode=A_LDR) and (oppostfix<>PF_None) then
+        if (opcode=A_LDR) and (oppostfix=PF_D) then
+          begin
+            opcode:=A_LDRD;
+            oppostfix:=PF_None;
+          end
+        else if (opcode=A_LDR) and (oppostfix<>PF_None) then
           begin
             if (oppostfix in [low(ldr2op)..high(ldr2op)]) then
               opcode:=ldr2op[oppostfix]
@@ -1681,6 +1751,11 @@ implementation
             { postfix has been added to opcode }
             oppostfix:=PF_None;
           end
+        else if (opcode=A_STR) and (oppostfix=PF_D) then
+          begin
+            opcode:=A_STRD;
+            oppostfix:=PF_None;
+          end
         else if (opcode=A_STR) and (oppostfix<>PF_None) then
           begin
             if (oppostfix in [low(str2op)..high(str2op)]) then
@@ -1766,6 +1841,10 @@ implementation
                       ot:=OT_REG32 or OT_SHIFTEROP;
                     R_FPUREGISTER:
                       ot:=OT_FPUREG;
+                    R_MMREGISTER:
+                      ot:=OT_VREG;
+                    R_SPECIALREGISTER:
+                      ot:=OT_REGF;
                     else
                       internalerror(2005090901);
                   end;
@@ -1797,6 +1876,16 @@ implementation
 
                       { determine possible address modes }
                       if (ref^.base<>NR_NO) and
+                        (opcode in [A_LDREX,A_LDREXB,A_LDREXH,A_LDREXD,
+                                    A_STREX,A_STREXB,A_STREXH,A_STREXD]) and
+                        (
+                          (ref^.addressmode=AM_OFFSET) and
+                          (ref^.index=NR_NO) and
+                          (ref^.shiftmode=SM_None) and
+                          (ref^.offset=0)
+                        ) then
+                        ot:=ot or OT_AM6
+                      else if (ref^.base<>NR_NO) and
                         (
                           (
                             (ref^.index=NR_NO) and
@@ -1811,14 +1900,14 @@ implementation
                           (
                             (ref^.index<>NR_NO) and
                             (ref^.shiftmode<>SM_None) and
-                            (ref^.shiftimm<=31) and
+                            (ref^.shiftimm<=32) and
                             (ref^.offset=0)
                           )
                         ) then
                         ot:=ot or OT_AM2;
 
                       if (ref^.index<>NR_NO) and
-                        (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
+                        (oppostfix in [PF_None,PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
                         (
                           (ref^.base=NR_NO) and
                           (ref^.shiftmode=SM_None) and
@@ -1867,8 +1956,13 @@ implementation
                 begin
                   ot:=OT_SHIFTEROP;
                 end;
+              top_conditioncode:
+                begin
+                  ot:=OT_CONDITION;
+                end;
               else
-                internalerror(200402261);
+                begin writeln(typ);
+                internalerror(200402261); end;
             end;
           end;
       end;
@@ -1900,7 +1994,6 @@ implementation
         {siz : array[0..3] of longint;}
       begin
         Matches:=100;
-        writeln(getstring,'---');
 
         { Check the opcode and operands }
         if (p^.opcode<>opcode) or (p^.ops<>ops) then
@@ -1942,7 +2035,7 @@ implementation
         { update condition flags
           or floating point single }
       if (oppostfix=PF_S) and
-        not(p^.code[0] in [#$04]) then
+        not(p^.code[0] in [#$04..#$0B,#$14..#$16,#$29,#$30]) then
         begin
           Matches:=0;
           exit;
@@ -1962,7 +2055,9 @@ implementation
           // ldr,str,ldrb,strb
           #$17,
           // stm,ldm
-          #$26
+          #$26,
+          // vldm/vstm
+          #$44
         ]) then
         begin
           Matches:=0;
@@ -2105,6 +2200,7 @@ implementation
            inc(i);
            insentry:=@instab[i];
          end;
+        if (ops=3) and (opcode=a_sub) then writeln(oppostfix,',',oper[2]^.val);
         Message1(asmw_e_invalid_opcode_and_operands,GetString);
         { No instruction found, set insentry to nil and inssize to -1 }
         insentry:=nil;
@@ -2113,1013 +2209,1435 @@ implementation
 
 
     procedure taicpu.gencode(objdata:TObjData);
+      const
+        CondVal : array[TAsmCond] of byte=(
+         $E, $0, $1, $2, $3, $4, $5, $6, $7, $8, $9, $A,
+         $B, $C, $D, $E, 0);
       var
-        bytes : dword;
+        bytes, rd, rm, rn, d, m, n : dword;
+        bytelen : longint;
+        dp_operation : boolean;
         i_field : byte;
+        currsym : TObjSymbol;
+        offset : longint;
+        refoper : poper;
+        msb : longint;
+        r: byte;
 
       procedure setshifterop(op : byte);
+        var
+          r : byte;
+          imm : dword;
         begin
           case oper[op]^.typ of
             top_const:
               begin
                 i_field:=1;
-                bytes:=bytes or dword(oper[op]^.val and $fff);
+                if oper[op]^.val and $ff=oper[op]^.val then
+                  bytes:=bytes or dword(oper[op]^.val)
+                else
+                  begin
+                    { calc rotate and adjust imm }
+                    r:=0;
+                    imm:=dword(oper[op]^.val);
+                    repeat
+                      imm:=RolDWord(imm, 2);
+                      inc(r)
+                    until (imm and $ff)=imm;
+                    bytes:=bytes or (r shl 8) or imm;
+                  end;
               end;
             top_reg:
               begin
                 i_field:=0;
-                bytes:=bytes or (getsupreg(oper[op]^.reg) shl 16);
+                bytes:=bytes or getsupreg(oper[op]^.reg);
 
                 { does a real shifter op follow? }
-                if (op+1<=op) and (oper[op+1]^.typ=top_shifterop) then
-                  begin
-                  end;
+                if (op+1<opercnt) and (oper[op+1]^.typ=top_shifterop) then
+                  with oper[op+1]^.shifterop^ do
+                    begin
+                      bytes:=bytes or (shiftimm shl 7);
+                      if shiftmode<>SM_RRX then
+                        bytes:=bytes or (ord(shiftmode) - ord(SM_LSL)) shl 5
+                      else
+                        bytes:=bytes or (3 shl 5);
+                      if getregtype(rs) <> R_INVALIDREGISTER then
+                        begin
+                          bytes:=bytes or (1 shl 4);
+                          bytes:=bytes or (getsupreg(rs) shl 8);
+                        end
+                    end;
               end;
           else
             internalerror(2005091103);
           end;
         end;
 
+      function MakeRegList(reglist: tcpuregisterset): word;
+        var
+          i, w: word;
+        begin
+          result:=0;
+          w:=1;
+          for i:=RS_R0 to RS_R15 do
+            begin
+              if i in reglist then
+                result:=result or w;
+              w:=w shl 1
+            end;
+        end;
+
+      function getcoproc(reg: tregister): byte;
+        begin
+          if reg=NR_p15 then
+            result:=15
+          else
+            begin
+              Message1(asmw_e_invalid_opcode_and_operands,'Invalid coprocessor port');
+              result:=0;
+            end;
+        end;
+
+      function getcoprocreg(reg: tregister): byte;
+        begin
+          result:=getsupreg(reg)-getsupreg(NR_CR0);
+        end;
+
+      function getmmreg(reg: tregister): byte;
+        begin
+          case reg of
+            NR_D0: result:=0;
+            NR_D1: result:=1;
+            NR_D2: result:=2;
+            NR_D3: result:=3;
+            NR_D4: result:=4;
+            NR_D5: result:=5;
+            NR_D6: result:=6;
+            NR_D7: result:=7;
+            NR_D8: result:=8;
+            NR_D9: result:=9;
+            NR_D10: result:=10;
+            NR_D11: result:=11;
+            NR_D12: result:=12;
+            NR_D13: result:=13;
+            NR_D14: result:=14;
+            NR_D15: result:=15;
+            NR_D16: result:=16;
+            NR_D17: result:=17;
+            NR_D18: result:=18;
+            NR_D19: result:=19;
+            NR_D20: result:=20;
+            NR_D21: result:=21;
+            NR_D22: result:=22;
+            NR_D23: result:=23;
+            NR_D24: result:=24;
+            NR_D25: result:=25;
+            NR_D26: result:=26;
+            NR_D27: result:=27;
+            NR_D28: result:=28;
+            NR_D29: result:=29;
+            NR_D30: result:=30;
+            NR_D31: result:=31;
+
+            NR_S0: result:=0;
+            NR_S1: result:=1;
+            NR_S2: result:=2;
+            NR_S3: result:=3;
+            NR_S4: result:=4;
+            NR_S5: result:=5;
+            NR_S6: result:=6;
+            NR_S7: result:=7;
+            NR_S8: result:=8;
+            NR_S9: result:=9;
+            NR_S10: result:=10;
+            NR_S11: result:=11;
+            NR_S12: result:=12;
+            NR_S13: result:=13;
+            NR_S14: result:=14;
+            NR_S15: result:=15;
+            NR_S16: result:=16;
+            NR_S17: result:=17;
+            NR_S18: result:=18;
+            NR_S19: result:=19;
+            NR_S20: result:=20;
+            NR_S21: result:=21;
+            NR_S22: result:=22;
+            NR_S23: result:=23;
+            NR_S24: result:=24;
+            NR_S25: result:=25;
+            NR_S26: result:=26;
+            NR_S27: result:=27;
+            NR_S28: result:=28;
+            NR_S29: result:=29;
+            NR_S30: result:=30;
+            NR_S31: result:=31;
+          else
+            result:=0;
+          end;
+        end;
+
       begin
         bytes:=$0;
+        bytelen:=4;
         i_field:=0;
         { evaluate and set condition code }
+        bytes:=bytes or (CondVal[condition] shl 28);
 
         { condition code allowed? }
 
         { setup rest of the instruction }
         case insentry^.code[0] of
-          #$08:
+          #$01: // B/BL
             begin
               { set instruction code }
-              bytes:=bytes or (ord(insentry^.code[1]) shl 26);
-              bytes:=bytes or (ord(insentry^.code[2]) shl 21);
-
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              { set offset }
+              if oper[0]^.typ=top_const then
+                bytes:=bytes or ((oper[0]^.val shr 2) and $ffffff)
+              else
+                begin
+                  currsym:=objdata.symbolref(oper[0]^.ref^.symbol);
+                  if (currsym.bind<>AB_LOCAL) and (currsym.objsection<>objdata.CurrObjSec) then
+                    objdata.writereloc(oper[0]^.ref^.offset,0,currsym,RELOC_RELATIVE_24)
+                  else
+                    bytes:=bytes or (((currsym.offset-insoffset-8) shr 2) and $ffffff);
+                end;
+            end;
+          #$02:
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              { set code }
+              bytes:=bytes or (oper[0]^.val and $FFFFFF);
+            end;
+          #$03:
+            begin // BLX/BX
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+
+              bytes:=bytes or getsupreg(oper[0]^.reg);
+            end;
+          #$04..#$07: // SUB
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              { set destination }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+              { set Rn }
+              bytes:=bytes or (getsupreg(oper[1]^.reg) shl 16);
+              { create shifter op }
+              setshifterop(2);
+              { set I field }
+              bytes:=bytes or (i_field shl 25);
+              { set S if necessary }
+              if oppostfix=PF_S then
+                bytes:=bytes or (1 shl 20);
+            end;
+          #$08,#$0A,#$0B: // MOV
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
               { set destination }
               bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
-
               { create shifter op }
               setshifterop(1);
-
-              { set i field }
+              { set I field }
               bytes:=bytes or (i_field shl 25);
-
-              { set s if necessary }
+              { set S if necessary }
               if oppostfix=PF_S then
                 bytes:=bytes or (1 shl 20);
             end;
-          #$ff:
-            internalerror(2005091101);
-          else
-            internalerror(2005091102);
-        end;
-        { we're finished, write code }
-        objdata.writebytes(bytes,sizeof(bytes));
-      end;
-
-
-{$ifdef dummy}
-(*
-static void gencode (long segment, long offset, int bits,
-                     insn *ins, char *codes, long insn_end)
-{
-    int has_S_code;             /* S - setflag */
-    int has_B_code;             /* B - setflag */
-    int has_T_code;             /* T - setflag */
-    int has_W_code;             /* ! => W flag */
-    int has_F_code;             /* ^ => S flag */
-    int keep;
-    unsigned char c;
-    unsigned char bytes[4];
-    long          data, size;
-    static int cc_code[] =      /* bit pattern of cc */
-  {                             /* order as enum in  */
-    0x0E, 0x03, 0x02, 0x00,     /* nasm.h            */
-    0x0A, 0x0C, 0x08, 0x0D,
-    0x09, 0x0B, 0x04, 0x01,
-    0x05, 0x07, 0x06,
-  };
-
-
-#ifdef DEBUG
-static char *CC[] =
-  {                                    /* condition code names */
-    "AL", "CC", "CS", "EQ",
-    "GE", "GT", "HI", "LE",
-    "LS", "LT", "MI", "NE",
-    "PL", "VC", "VS", "",
-    "S"
-};
-
-
-    has_S_code = (ins->condition & C_SSETFLAG);
-    has_B_code = (ins->condition & C_BSETFLAG);
-    has_T_code = (ins->condition & C_TSETFLAG);
-    has_W_code = (ins->condition & C_EXSETFLAG);
-    has_F_code = (ins->condition & C_FSETFLAG);
-    ins->condition = (ins->condition & 0x0F);
-
-
-    if (rt_debug)
-      {
-    printf ("gencode: instruction: %s%s", insn_names[ins->opcode],
-            CC[ins->condition & 0x0F]);
-    if (has_S_code)
-      printf ("S");
-    if (has_B_code)
-      printf ("B");
-    if (has_T_code)
-      printf ("T");
-    if (has_W_code)
-      printf ("!");
-    if (has_F_code)
-      printf ("^");
-
-    printf ("\n");
-
-    c = *codes;
-
-    printf ("   (%d)  decode - '0x%02X'\n", ins->operands, c);
-
-
-    bytes[0] = 0xB;
-    bytes[1] = 0xE;
-    bytes[2] = 0xE;
-    bytes[3] = 0xF;
-      }
-
-    // First condition code in upper nibble
-    if (ins->condition < C_NONE)
-      {
-        c = cc_code[ins->condition] << 4;
-      }
-    else
-      {
-        c = cc_code[C_AL] << 4; // is often ALWAYS but not always
-      }
-
-
-    switch (keep = *codes)
-      {
-        case 1:
-          // B, BL
-          ++codes;
-          c |= *codes++;
-          bytes[0] = c;
-
-          if (ins->oprs[0].segment != segment)
-            {
-              // fais une relocation
-              c = 1;
-              data = 0; // Let the linker locate ??
-            }
-          else
-            {
-              c = 0;
-              data = ins->oprs[0].offset - (offset + 8);
-
-              if (data % 4)
-                {
-                  errfunc (ERR_NONFATAL, "offset not aligned on 4 bytes");
-                }
-            }
-
-          if (data >= 0x1000)
-            {
-              errfunc (ERR_NONFATAL, "too long offset");
-            }
-
-          data = data >> 2;
-          bytes[1] = (data >> 16) & 0xFF;
-          bytes[2] = (data >> 8)  & 0xFF;
-          bytes[3] = (data )      & 0xFF;
-
-          if (c == 1)
-            {
-//            out (offset, segment, &bytes[0], OUT_RAWDATA+1, NO_SEG, NO_SEG);
-              out (offset, segment, &bytes[0], OUT_REL3ADR+4, ins->oprs[0].segment, NO_SEG);
-            }
-          else
-            {
-              out (offset, segment, &bytes[0], OUT_RAWDATA+4, NO_SEG, NO_SEG);
-            }
-          return;
-
-        case 2:
-          // SWI
-          ++codes;
-          c |= *codes++;
-          bytes[0] = c;
-          data = ins->oprs[0].offset;
-          bytes[1] = (data >> 16) & 0xFF;
-          bytes[2] = (data >> 8) & 0xFF;
-          bytes[3] = (data) & 0xFF;
-          out (offset, segment, &bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
-          return;
-        case 3:
-          // BX
-          ++codes;
-          c |= *codes++;
-          bytes[0] = c;
-          bytes[1] = *codes++;
-          bytes[2] = *codes++;
-          bytes[3] = *codes++;
-          c = regval (&ins->oprs[0],1);
-          if (c == 15)  // PC
-            {
-              errfunc (ERR_WARNING, "'BX' with R15 has undefined behaviour");
-            }
-          else if (c > 15)
-            {
-              errfunc (ERR_NONFATAL, "Illegal register specified for 'BX'");
-            }
-
-          bytes[3] |= (c & 0x0F);
-          out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
-          return;
-
-        case 4:         // AND Rd,Rn,Rm
-        case 5:         // AND Rd,Rn,Rm,<shift>Rs
-        case 6:         // AND Rd,Rn,Rm,<shift>imm
-        case 7:         // AND Rd,Rn,<shift>imm
-          ++codes;
-#ifdef DEBUG
-          if (rt_debug)
-            {
-              printf ("         decode - '0x%02X'\n", keep);
-              printf ("           code - '0x%02X'\n", (unsigned char) ( *codes));
-            }
-#endif
-          bytes[0] = c | *codes;
-          ++codes;
-
-          bytes[1] = *codes;
-          if (has_S_code)
-            bytes[1] |= 0x10;
-          c = regval (&ins->oprs[1],1);
-          // Rn in low nibble
-          bytes[1] |= c;
-
-          // Rd in high nibble
-          bytes[2] = regval (&ins->oprs[0],1) << 4;
-
-          if (keep != 7)
-            {
-              // Rm in low nibble
-              bytes[3] = regval (&ins->oprs[2],1);
-            }
-
-          // Shifts if any
-          if (keep == 5 || keep == 6)
-            {
-              // Shift in bytes 2 and 3
-              if (keep == 5)
-                {
-                  // Rs
-                  c = regval (&ins->oprs[3],1);
-                  bytes[2] |= c;
-
-                  c = 0x10;             // Set bit 4 in byte[3]
-                }
-              if (keep == 6)
-                {
-                  c = (ins->oprs[3].offset) & 0x1F;
-
-                  // #imm
-                  bytes[2] |= c >> 1;
-                  if (c & 0x01)
-                    {
-                      bytes[3] |= 0x80;
-                    }
-                  c = 0;                // Clr bit 4 in byte[3]
-                }
-              // <shift>
-              c |= shiftval (&ins->oprs[3]) << 5;
-
-              bytes[3] |= c;
-            }
-
-          // reg,reg,imm
-          if (keep == 7)
-            {
-              int shimm;
-
-              shimm = imm_shift (ins->oprs[2].offset);
-
-              if (shimm == -1)
-                {
-                  errfunc (ERR_NONFATAL, "cannot create that constant");
-                }
-              bytes[3] = shimm & 0xFF;
-              bytes[2] |= (shimm & 0xF00) >> 8;
-            }
-
-          out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
-          return;
-
-        case 8:         // MOV Rd,Rm
-        case 9:         // MOV Rd,Rm,<shift>Rs
-        case 0xA:       // MOV Rd,Rm,<shift>imm
-        case 0xB:       // MOV Rd,<shift>imm
-          ++codes;
-#ifdef DEBUG
-          if (rt_debug)
-            {
-              printf ("         decode - '0x%02X'\n", keep);
-              printf ("           code - '0x%02X'\n", (unsigned char) ( *codes));
-            }
-#endif
-          bytes[0] = c | *codes;
-          ++codes;
-
-          bytes[1] = *codes;
-          if (has_S_code)
-            bytes[1] |= 0x10;
-
-          // Rd in high nibble
-          bytes[2] = regval (&ins->oprs[0],1) << 4;
-
-          if (keep != 0x0B)
-            {
-              // Rm in low nibble
-              bytes[3] = regval (&ins->oprs[1],1);
-            }
-
-          // Shifts if any
-          if (keep == 0x09 || keep == 0x0A)
-            {
-              // Shift in bytes 2 and 3
-              if (keep == 0x09)
-                {
-                  // Rs
-                  c = regval (&ins->oprs[2],1);
-                  bytes[2] |= c;
-
-                  c = 0x10;             // Set bit 4 in byte[3]
-                }
-              if (keep == 0x0A)
-                {
-                  c = (ins->oprs[2].offset) & 0x1F;
-
-                  // #imm
-                  bytes[2] |= c >> 1;
-                  if (c & 0x01)
-                    {
-                      bytes[3] |= 0x80;
-                    }
-                  c = 0;                // Clr bit 4 in byte[3]
-                }
-              // <shift>
-              c |= shiftval (&ins->oprs[2]) << 5;
-
-              bytes[3] |= c;
-            }
+          #$0C,#$0E,#$0F: // CMP
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              { set destination }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 16);
+              { create shifter op }
+              setshifterop(1);
+              { set I field }
+              bytes:=bytes or (i_field shl 25);
+              { always set S bit }
+              bytes:=bytes or (1 shl 20);
+            end;
+          #$14: // MUL/MLA r1,r2,r3
+            begin
+              { set instruction code }
+              bytes:=bytes or ord(insentry^.code[1]) shl 24;
+              bytes:=bytes or ord(insentry^.code[2]) shl 16;
+              bytes:=bytes or ord(insentry^.code[3]);
+              { set regs }
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 16;
+              bytes:=bytes or getsupreg(oper[1]^.reg);
+              bytes:=bytes or getsupreg(oper[2]^.reg) shl 8;
+            end;
+          #$15: // MUL/MLA r1,r2,r3,r4
+            begin
+              { set instruction code }
+              bytes:=bytes or ord(insentry^.code[1]) shl 24;
+              bytes:=bytes or ord(insentry^.code[2]) shl 16;
+              bytes:=bytes or ord(insentry^.code[3]) shl 4;
+              { set regs }
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 16;
+              bytes:=bytes or getsupreg(oper[1]^.reg);
+              bytes:=bytes or getsupreg(oper[2]^.reg) shl 8;
+              if ops>3 then
+                bytes:=bytes or getsupreg(oper[3]^.reg) shl 12
+              else
+                bytes:=bytes or ($F shl 12);
 
-          // reg,imm
-          if (keep == 0x0B)
-            {
-              int shimm;
+              if oppostfix in [PF_R,PF_X] then
+                bytes:=bytes or (1 shl 5);
+            end;
+          #$16: // MULL r1,r2,r3,r4
+            begin
+              { set instruction code }
+              bytes:=bytes or ord(insentry^.code[1]) shl 24;
+              bytes:=bytes or ord(insentry^.code[2]) shl 16;
+              bytes:=bytes or ord(insentry^.code[3]) shl 4;
+              { set regs }
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+              bytes:=bytes or getsupreg(oper[1]^.reg) shl 16;
+              bytes:=bytes or getsupreg(oper[2]^.reg);
+              if ops=4 then
+                begin
+                  if oper[3]^.typ=top_shifterop then
+                    begin
+                      if opcode in [A_PKHBT,A_PKHTB] then
+                        begin
+                          if ((opcode=A_PKHTB) and
+                              (oper[3]^.shifterop^.shiftmode <> SM_ASR)) or
+                            ((opcode=A_PKHBT) and
+                             (oper[3]^.shifterop^.shiftmode <> SM_LSL)) or
+                            (oper[3]^.shifterop^.rs<>NR_NO) then
+                            Message1(asmw_e_invalid_opcode_and_operands,GetString);
+
+                          bytes:=bytes or ((oper[3]^.shifterop^.shiftimm and $1F) shl 7);
+                        end
+                      else
+                        begin
+                          if (oper[3]^.shifterop^.shiftmode<>sm_ror) or
+                            (oper[3]^.shifterop^.rs<>NR_NO) or
+                            (not (oper[3]^.shifterop^.shiftimm in [0,8,16,24])) then
+                            Message1(asmw_e_invalid_opcode_and_operands,GetString);
 
-              shimm = imm_shift (ins->oprs[1].offset);
+                          bytes:=bytes or (((oper[3]^.shifterop^.shiftimm shr 3) and $3) shl 10);
+                        end;
+                    end
+                  else
+                    bytes:=bytes or getsupreg(oper[3]^.reg) shl 8;
+                end;
 
-              if (shimm == -1)
-                {
-                  errfunc (ERR_NONFATAL, "cannot create that constant");
-                }
-              bytes[3] = shimm & 0xFF;
-              bytes[2] |= (shimm & 0xF00) >> 8;
-            }
+              if PF_S=oppostfix then
+                bytes:=bytes or (1 shl 20);
+              if PF_X=oppostfix then
+                bytes:=bytes or (1 shl 5);
+            end;
+          #$17: // LDR/STR
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              { set Rn and Rd }
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+              bytes:=bytes or getsupreg(oper[1]^.ref^.base) shl 16;
+              if getregtype(oper[1]^.ref^.index)=R_INVALIDREGISTER then
+                begin
+                  { set offset }
+                  offset:=0;
+                  currsym:=objdata.symbolref(oper[1]^.ref^.symbol);
+                  if assigned(currsym) then
+                    offset:=currsym.offset-insoffset-8;
+                  offset:=offset+oper[1]^.ref^.offset;
+                  if offset>=0 then
+                    begin
+                      { set U flag }
+                      bytes:=bytes or (1 shl 23);
+                      bytes:=bytes or offset
+                    end
+                  else
+                    begin
+                      offset:=-offset;
+                      bytes:=bytes or offset
+                    end;
+                end
+              else
+                begin
+                  { set U flag }
+                  if oper[1]^.ref^.signindex>=0 then
+                    bytes:=bytes or (1 shl 23);
+                  { set I flag }
+                  bytes:=bytes or (1 shl 25);
+                  bytes:=bytes or getsupreg(oper[1]^.ref^.index);
+                  { set shift }
+                  with oper[1]^.ref^ do
+                    if shiftmode<>SM_None then
+                      begin
+                        bytes:=bytes or (shiftimm shl 7);
+                        if shiftmode<>SM_RRX then
+                          bytes:=bytes or (ord(shiftmode) - ord(SM_LSL)) shl 5
+                        else
+                          bytes:=bytes or (3 shl 5);
+                      end
+                end;
+              { set W bit }
+              if oper[1]^.ref^.addressmode=AM_PREINDEXED then
+                bytes:=bytes or (1 shl 21);
+              { set P bit if necessary }
+              if oper[1]^.ref^.addressmode<>AM_POSTINDEXED then
+                bytes:=bytes or (1 shl 24);
+            end;
+          #$18: // LDREX/STREX
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set Rn and Rd }
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+              if (ops=3) then
+                begin
+                  if opcode<>A_LDREXD then
+                    bytes:=bytes or getsupreg(oper[1]^.reg);
 
-          out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
-          return;
+                  bytes:=bytes or (getsupreg(oper[2]^.ref^.base) shl 16);
+                end
+              else if (ops=4) then // STREXD
+                begin
+                  if opcode<>A_LDREXD then
+                    bytes:=bytes or getsupreg(oper[1]^.reg);
 
+                  bytes:=bytes or (getsupreg(oper[3]^.ref^.base) shl 16);
+                end
+              else
+                bytes:=bytes or (getsupreg(oper[1]^.ref^.base) shl 16);
+            end;
+          #$19: // LDRD/STRD
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set Rn and Rd }
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+
+              refoper:=oper[1];
+              if ops=3 then
+                refoper:=oper[2];
+
+              bytes:=bytes or getsupreg(refoper^.ref^.base) shl 16;
+              if getregtype(refoper^.ref^.index)=R_INVALIDREGISTER then
+                begin
+                  bytes:=bytes or (1 shl 22);
+                  { set offset }
+                  offset:=0;
+                  currsym:=objdata.symbolref(refoper^.ref^.symbol);
+                  if assigned(currsym) then
+                    offset:=currsym.offset-insoffset-8;
+                  offset:=offset+refoper^.ref^.offset;
+                  if offset>=0 then
+                    begin
+                      { set U flag }
+                      bytes:=bytes or (1 shl 23);
+                      bytes:=bytes or (offset and $F);
+                      bytes:=bytes or ((offset and $F0) shl 4);
+                    end
+                  else
+                    begin
+                      offset:=-offset;
+                      bytes:=bytes or (offset and $F);
+                      bytes:=bytes or ((offset and $F0) shl 4);
+                    end;
+                end
+              else
+                begin
+                  { set U flag }
+                  if refoper^.ref^.signindex>=0 then
+                    bytes:=bytes or (1 shl 23);
+                  bytes:=bytes or getsupreg(refoper^.ref^.index);
+                end;
+              { set W bit }
+              if refoper^.ref^.addressmode=AM_PREINDEXED then
+                bytes:=bytes or (1 shl 21);
+              { set P bit if necessary }
+              if refoper^.ref^.addressmode<>AM_POSTINDEXED then
+                bytes:=bytes or (1 shl 24);
+            end;
+          #$1A: // QADD/QSUB
+            begin
+              { set instruction code }
+              bytes:=bytes or ord(insentry^.code[1]) shl 24;
+              bytes:=bytes or ord(insentry^.code[2]) shl 16;
+              bytes:=bytes or ord(insentry^.code[3]) shl 4;
+              { set regs }
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+              bytes:=bytes or getsupreg(oper[1]^.reg) shl 0;
+              bytes:=bytes or getsupreg(oper[2]^.reg) shl 16;
+            end;
+          #$1B:
+            begin
+              { set instruction code }
+              bytes:=bytes or ord(insentry^.code[1]) shl 24;
+              bytes:=bytes or ord(insentry^.code[2]) shl 16;
+              bytes:=bytes or ord(insentry^.code[3]) shl 4;
+              { set regs }
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+              bytes:=bytes or getsupreg(oper[1]^.reg);
+              if ops=3 then
+                begin
+                  if (oper[2]^.shifterop^.shiftmode<>sm_ror) or
+                    (oper[2]^.shifterop^.rs<>NR_NO) or
+                    (not (oper[2]^.shifterop^.shiftimm in [0,8,16,24])) then
+                    Message1(asmw_e_invalid_opcode_and_operands,GetString);
 
-        case 0xC:       // CMP Rn,Rm
-        case 0xD:       // CMP Rn,Rm,<shift>Rs
-        case 0xE:       // CMP Rn,Rm,<shift>imm
-        case 0xF:       // CMP Rn,<shift>imm
-          ++codes;
+                  bytes:=bytes or (((oper[2]^.shifterop^.shiftimm shr 3) and $3) shl 10);
+                end;
+            end;
+          #$1C: // MCR/MRC
+            begin
+              { set instruction code }
+              bytes:=bytes or ord(insentry^.code[1]) shl 24;
+              bytes:=bytes or ord(insentry^.code[2]) shl 16;
+              bytes:=bytes or ord(insentry^.code[3]) shl 4;
+              { set regs and operands }
+              bytes:=bytes or getcoproc(oper[0]^.reg) shl 8;
+              bytes:=bytes or ((oper[1]^.val and $7) shl 21);
+              bytes:=bytes or getsupreg(oper[2]^.reg) shl 12;
+              bytes:=bytes or getcoprocreg(oper[3]^.reg) shl 16;
+              bytes:=bytes or getcoprocreg(oper[4]^.reg);
+              if ops > 5 then
+                bytes:=bytes or ((oper[5]^.val and $7) shl 5);
+            end;
+          #$1D: // MCRR/MRRC
+            begin
+              { set instruction code }
+              bytes:=bytes or ord(insentry^.code[1]) shl 24;
+              bytes:=bytes or ord(insentry^.code[2]) shl 16;
+              bytes:=bytes or ord(insentry^.code[3]) shl 4;
+              { set regs and operands }
+              bytes:=bytes or getcoproc(oper[0]^.reg) shl 8;
+              bytes:=bytes or ((oper[1]^.val and $7) shl 4);
+              bytes:=bytes or getsupreg(oper[2]^.reg) shl 12;
+              bytes:=bytes or getsupreg(oper[3]^.reg) shl 16;
+              bytes:=bytes or getcoprocreg(oper[4]^.reg);
+            end;
+          #$22: // LDRH/STRH
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 16);
+              bytes:=bytes or ord(insentry^.code[2]);
+              { src/dest register (Rd) }
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+              { base register (Rn) }
+              bytes:=bytes or getsupreg(oper[1]^.ref^.base) shl 16;
+              if getregtype(oper[1]^.ref^.index)=R_INVALIDREGISTER then
+                begin
+                  bytes:=bytes or (1 shl 22); // with immediate offset
+                  if oper[1]^.ref^.offset < 0 then
+                    begin
+                      bytes:=bytes or ((-oper[1]^.ref^.offset) and $f0 shl 4);
+                      bytes:=bytes or ((-oper[1]^.ref^.offset) and $f);
+                    end
+                  else
+                    begin
+                      { set U bit }
+                      bytes:=bytes or (1 shl 23);
+                      bytes:=bytes or (oper[1]^.ref^.offset and $f0 shl 4);
+                      bytes:=bytes or (oper[1]^.ref^.offset and $f);
+                    end;
+                end
+              else
+                begin
+                  { set U flag }
+                  bytes:=bytes or (1 shl 23);
+                  bytes:=bytes or getsupreg(oper[1]^.ref^.index);
+                end;
+              { set P bit if necessary }
+              if oper[1]^.ref^.addressmode<>AM_POSTINDEXED then
+                bytes:=bytes or (1 shl 24);
+            end;
+          #$25: // PLD/PLI
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set Rn and Rd }
+              bytes:=bytes or getsupreg(oper[0]^.ref^.base) shl 16;
+              if getregtype(oper[0]^.ref^.index)=R_INVALIDREGISTER then
+                begin
+                  { set offset }
+                  offset:=0;
+                  currsym:=objdata.symbolref(oper[0]^.ref^.symbol);
+                  if assigned(currsym) then
+                    offset:=currsym.offset-insoffset-8;
+                  offset:=offset+oper[0]^.ref^.offset;
+                  if offset>=0 then
+                    begin
+                      { set U flag }
+                      bytes:=bytes or (1 shl 23);
+                      bytes:=bytes or offset
+                    end
+                  else
+                    begin
+                      offset:=-offset;
+                      bytes:=bytes or offset
+                    end;
+                end
+              else
+                begin
+                  { set U flag }
+                  if oper[0]^.ref^.signindex>=0 then
+                    bytes:=bytes or (1 shl 23);
+                  bytes:=bytes or getsupreg(oper[0]^.ref^.index);
+                  { set shift }
+                  with oper[0]^.ref^ do
+                    if shiftmode<>SM_None then
+                      begin
+                        bytes:=bytes or (shiftimm shl 7);
+                        if shiftmode<>SM_RRX then
+                          bytes:=bytes or (ord(shiftmode) - ord(SM_LSL)) shl 5
+                        else
+                          bytes:=bytes or (3 shl 5);
+                      end
+                end;
+            end;
+          #$26: // LDM/STM
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 20);
 
-          bytes[0] = c | *codes++;
-
-          bytes[1] = *codes;
-
-          // Implicit S code
-          bytes[1] |= 0x10;
-
-          c = regval (&ins->oprs[0],1);
-          // Rn in low nibble
-          bytes[1] |= c;
-
-          // No destination
-          bytes[2] = 0;
-
-          if (keep != 0x0B)
-            {
-              // Rm in low nibble
-              bytes[3] = regval (&ins->oprs[1],1);
-            }
-
-          // Shifts if any
-          if (keep == 0x0D || keep == 0x0E)
-            {
-              // Shift in bytes 2 and 3
-              if (keep == 0x0D)
-                {
-                  // Rs
-                  c = regval (&ins->oprs[2],1);
-                  bytes[2] |= c;
-
-                  c = 0x10;             // Set bit 4 in byte[3]
-                }
-              if (keep == 0x0E)
-                {
-                  c = (ins->oprs[2].offset) & 0x1F;
-
-                  // #imm
-                  bytes[2] |= c >> 1;
-                  if (c & 0x01)
-                    {
-                      bytes[3] |= 0x80;
-                    }
-                  c = 0;                // Clr bit 4 in byte[3]
-                }
-              // <shift>
-              c |= shiftval (&ins->oprs[2]) << 5;
-
-              bytes[3] |= c;
-            }
-
-          // reg,imm
-          if (keep == 0x0F)
-            {
-              int shimm;
-
-              shimm = imm_shift (ins->oprs[1].offset);
-
-              if (shimm == -1)
-                {
-                  errfunc (ERR_NONFATAL, "cannot create that constant");
-                }
-              bytes[3] = shimm & 0xFF;
-              bytes[2] |= (shimm & 0xF00) >> 8;
-            }
-
-          out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
-          return;
-
-        case 0x10:      // MRS Rd,<psr>
-          ++codes;
-
-          bytes[0] = c | *codes++;
-
-          bytes[1] = *codes++;
-
-          // Rd
-          c = regval (&ins->oprs[0],1);
-
-          bytes[2] = c << 4;
-
-          bytes[3] = 0;
-
-          c = ins->oprs[1].basereg;
-
-          if (c == R_CPSR || c == R_SPSR)
-            {
-              if (c == R_SPSR)
-                {
-                  bytes[1] |= 0x40;
-                }
-            }
-          else
-            {
-              errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
-            }
-
-          out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
-
-          return;
-
-        case 0x11:      // MSR <psr>,Rm
-        case 0x12:      // MSR <psrf>,Rm
-        case 0x13:      // MSR <psrf>,#expression
-          ++codes;
-
-          bytes[0] = c | *codes++;
-
-          bytes[1] = *codes++;
-
-          bytes[2] = *codes;
-
-
-          if (keep == 0x11 || keep == 0x12)
-            {
-              // Rm
-              c = regval (&ins->oprs[1],1);
-
-              bytes[3] = c;
-            }
-          else
-            {
-              int shimm;
-
-              shimm = imm_shift (ins->oprs[1].offset);
-
-              if (shimm == -1)
-                {
-                  errfunc (ERR_NONFATAL, "cannot create that constant");
-                }
-              bytes[3] = shimm & 0xFF;
-              bytes[2] |= (shimm & 0xF00) >> 8;
-            }
-
-          c = ins->oprs[0].basereg;
-
-          if ( keep == 0x11)
-            {
-              if ( c == R_CPSR || c == R_SPSR)
-                {
-                if ( c== R_SPSR)
-                  {
-                    bytes[1] |= 0x40;
-                  }
-                }
-            else
-              {
-                errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
-              }
-            }
-          else
-            {
-              if ( c == R_CPSR_FLG || c == R_SPSR_FLG)
-                {
-                  if ( c== R_SPSR_FLG)
-                    {
-                      bytes[1] |= 0x40;
-                    }
-                }
+              if ops>1 then
+                begin
+                  if oper[0]^.typ=top_ref then
+                    begin
+                      { set W bit }
+                      if oper[0]^.ref^.addressmode=AM_PREINDEXED then
+                        bytes:=bytes or (1 shl 21);
+                      { set Rn }
+                      bytes:=bytes or (getsupreg(oper[0]^.ref^.index) shl 16);
+                    end
+                  else { typ=top_reg }
+                    begin
+                      { set Rn }
+                      bytes:=bytes or (getsupreg(oper[0]^.reg) shl 16);
+                    end;
+                  { reglist }
+                  bytes:=bytes or MakeRegList(oper[1]^.regset^);
+                end
               else
-                {
-                  errfunc (ERR_NONFATAL, "CPSR_flg or SPSR_flg expected");
-                }
-            }
-          break;
-
-        case 0x14:      // MUL  Rd,Rm,Rs
-        case 0x15:      // MULA Rd,Rm,Rs,Rn
-          ++codes;
-
-          bytes[0] = c | *codes++;
-
-          bytes[1] = *codes++;
-
-          bytes[3] = *codes;
-
-          // Rd
-          bytes[1] |= regval (&ins->oprs[0],1);
-          if (has_S_code)
-            bytes[1] |= 0x10;
-
-          // Rm
-          bytes[3] |= regval (&ins->oprs[1],1);
+                begin
+                  { push/pop }
+                  { Set W and Rn to SP }
+                  if opcode=A_PUSH then
+                    bytes:=bytes or (1 shl 21);
+                  bytes:=bytes or ($D shl 16);
+                  { reglist }
+                  bytes:=bytes or MakeRegList(oper[0]^.regset^);
+                end;
+              { set P bit }
+              if (opcode=A_LDM) and (oppostfix in [PF_ED,PF_EA,PF_IB,PF_DB])
+              or (opcode=A_STM) and (oppostfix in [PF_FA,PF_FD,PF_IB,PF_DB])
+              or (opcode=A_PUSH) then
+                bytes:=bytes or (1 shl 24);
+              { set U bit }
+              if (opcode=A_LDM) and (oppostfix in [PF_None,PF_ED,PF_FD,PF_IB,PF_IA])
+              or (opcode=A_STM) and (oppostfix in [PF_None,PF_FA,PF_EA,PF_IB,PF_IA])
+              or (opcode=A_POP) then
+                bytes:=bytes or (1 shl 23);
+            end;
+          #$27: // SWP/SWPB
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 20);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 4);
+              { set regs }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+              bytes:=bytes or getsupreg(oper[1]^.reg);
+              if ops=3 then
+                bytes:=bytes or (getsupreg(oper[2]^.ref^.base) shl 16);
+            end;
+          #$28: // BX/BLX
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              { set offset }
+              if oper[0]^.typ=top_const then
+                bytes:=bytes or ((oper[0]^.val shr 2) and $ffffff)
+              else
+                begin
+                  currsym:=objdata.symbolref(oper[0]^.ref^.symbol);
+                  if (currsym.bind<>AB_LOCAL) and (currsym.objsection<>objdata.CurrObjSec) then
+                    begin
+                      bytes:=bytes or $fffffe; // TODO: Not sure this is right, but it matches the output of gas
+                      objdata.writereloc(oper[0]^.ref^.offset,0,currsym,RELOC_RELATIVE_24_THUMB);
+                    end
+                  else
+                    begin
+                      offset:=(((currsym.offset-insoffset-8) shr 2) and $ffffff);
+                      bytes:=bytes or ((offset shr 2) and $ffffff);
+                      bytes:=bytes or ((offset shr 1) and $1) shl 24;
+                    end;
+                end;
+            end;
+          #$29: // SUB
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              { set regs }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+              { set S if necessary }
+              if oppostfix=PF_S then
+                bytes:=bytes or (1 shl 20);
+            end;
+          #$2A:
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set opers }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+              bytes:=bytes or ((oper[1]^.val and $1F) shl 16);
+              bytes:=bytes or getsupreg(oper[2]^.reg);
 
-          // Rs
-          bytes[2] = regval (&ins->oprs[2],1);
+              if (ops>3) and
+                (oper[3]^.typ=top_shifterop) and
+                (oper[3]^.shifterop^.rs=NR_NO) then
+                begin
+                  bytes:=bytes or ((oper[3]^.shifterop^.shiftimm and $1F) shl 7);
+                  if oper[3]^.shifterop^.shiftmode=SM_ASR then
+                    bytes:=bytes or (1 shl 6)
+                  else if oper[3]^.shifterop^.shiftmode<>SM_LSL then
+                    Message1(asmw_e_invalid_opcode_and_operands,GetString);
+                end;
+            end;
+          #$2B: // SETEND
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set endian specifier }
+              bytes:=bytes or ((oper[0]^.val and 1) shl 9);
+            end;
+          #$2C: // MOVW
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              { set destination }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+              { set imm }
+              bytes:=bytes or (oper[1]^.val and $FFF);
+              bytes:=bytes or ((oper[1]^.val and $F000) shl 4);
+            end;
+          #$2D: // BFX
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
 
-          if (keep == 0x15)
-            {
-              bytes[2] |= regval (&ins->oprs[3],1) << 4;
-            }
-          break;
+              if ops=3 then
+                begin
+                  msb:=(oper[1]^.val+oper[2]^.val-1);
+
+                  { set destination }
+                  bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+                  { set immediates }
+                  bytes:=bytes or ((oper[1]^.val and $1F) shl 7);
+                  bytes:=bytes or ((msb and $1F) shl 16);
+                end
+              else
+                begin
+                  if opcode in [A_BFC,A_BFI] then
+                    msb:=(oper[2]^.val+oper[3]^.val-1)
+                  else
+                    msb:=oper[3]^.val-1;
+
+                  { set destination }
+                  bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+                  bytes:=bytes or getsupreg(oper[1]^.reg);
+                  { set immediates }
+                  bytes:=bytes or ((oper[2]^.val and $1F) shl 7);
+                  bytes:=bytes or ((msb and $1F) shl 16);
+                end;
+            end;
+          #$2E: // Cache stuff
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set code }
+              bytes:=bytes or (oper[0]^.val and $F);
+            end;
+          #$2F: // Nop
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+            end;
+          #$30: // Shifts
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set destination }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+              bytes:=bytes or getsupreg(oper[1]^.reg);
+              if ops>2 then
+                begin
+                  { set shift }
+                  if oper[2]^.typ=top_reg then
+                    bytes:=bytes or (getsupreg(oper[2]^.reg) shl 8)
+                  else
+                    bytes:=bytes or ((oper[2]^.val and $1F) shl 7);
+                end;
+              { set S if necessary }
+              if oppostfix=PF_S then
+                bytes:=bytes or (1 shl 20);
+            end;
+          #$31: // BKPT
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 0);
+              { set imm }
+              bytes:=bytes or (oper[0]^.val and $FFF0) shl 4;
+              bytes:=bytes or (oper[0]^.val and $F);
+            end;
+          #$32: // CLZ/REV
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set regs }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+              bytes:=bytes or getsupreg(oper[1]^.reg);
+            end;
+          #$33:
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              { set regs }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
 
-        case 0x16:      // SMLAL RdHi,RdLo,Rm,Rs
-          ++codes;
+              if oper[1]^.typ=top_ref then
+                begin
+                  { set offset }
+                  offset:=0;
+                  currsym:=objdata.symbolref(oper[1]^.ref^.symbol);
+                  if assigned(currsym) then
+                    offset:=currsym.offset-insoffset-8;
+                  offset:=offset+oper[1]^.ref^.offset;
+                  if offset>=0 then
+                    begin
+                      { set U flag }
+                      bytes:=bytes or (1 shl 23);
+                      bytes:=bytes or offset
+                    end
+                  else
+                    begin
+                      bytes:=bytes or (1 shl 22);
+                      offset:=-offset;
+                      bytes:=bytes or offset
+                    end;
+                end
+              else
+                begin
+                  if is_shifter_const(oper[1]^.val,r) then
+                    begin
+                      setshifterop(1);
+                      bytes:=bytes or (1 shl 23);
+                    end
+                  else
+                    begin
+                      bytes:=bytes or (1 shl 22);
+                      oper[1]^.val:=-oper[1]^.val;
+                      setshifterop(1);
+                    end;
+                end;
+            end;
+          #$40: // VMOV
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+
+              { set regs }
+              case oppostfix of
+                PF_None:
+                  begin
+                    if ops=4 then
+                      begin
+                        if (getregtype(oper[0]^.reg)=R_MMREGISTER) and
+                           (getregtype(oper[2]^.reg)=R_INTREGISTER) then
+                          begin
+                            Rd:=getmmreg(oper[0]^.reg);
+                            Rm:=getsupreg(oper[2]^.reg);
+                            Rn:=getsupreg(oper[3]^.reg);
+                          end
+                        else if (getregtype(oper[0]^.reg)=R_INTREGISTER) and
+                                (getregtype(oper[2]^.reg)=R_MMREGISTER) then
+                          begin
+                            Rm:=getsupreg(oper[0]^.reg);
+                            Rn:=getsupreg(oper[1]^.reg);
+                            Rd:=getmmreg(oper[2]^.reg);
+                          end
+                        else
+                          message(asmw_e_invalid_opcode_and_operands);
+
+                        bytes:=bytes or (((Rd and $1E) shr 1) shl 0);
+                        bytes:=bytes or ((Rd and $1) shl 5);
+
+                        bytes:=bytes or (Rm shl 12);
+                        bytes:=bytes or (Rn shl 16);
+                      end
+                    else if ops=3 then
+                      begin
+                        if (getregtype(oper[0]^.reg)=R_MMREGISTER) and
+                           (getregtype(oper[1]^.reg)=R_INTREGISTER) then
+                          begin
+                            Rd:=getmmreg(oper[0]^.reg);
+                            Rm:=getsupreg(oper[1]^.reg);
+                            Rn:=getsupreg(oper[2]^.reg);
+                          end
+                        else if (getregtype(oper[0]^.reg)=R_INTREGISTER) and
+                                (getregtype(oper[2]^.reg)=R_MMREGISTER) then
+                          begin
+                            Rm:=getsupreg(oper[0]^.reg);
+                            Rn:=getsupreg(oper[1]^.reg);
+                            Rd:=getmmreg(oper[2]^.reg);
+                          end
+                        else
+                          message(asmw_e_invalid_opcode_and_operands);
+
+                        bytes:=bytes or ((Rd and $F) shl 0);
+                        bytes:=bytes or ((Rd and $10) shl 1);
+
+                        bytes:=bytes or (Rm shl 12);
+                        bytes:=bytes or (Rn shl 16);
+                      end
+                    else if ops=2 then
+                      begin
+                        if (getregtype(oper[0]^.reg)=R_MMREGISTER) and
+                           (getregtype(oper[1]^.reg)=R_INTREGISTER) then
+                          begin
+                            Rd:=getmmreg(oper[0]^.reg);
+                            Rm:=getsupreg(oper[1]^.reg);
+                          end
+                        else if (getregtype(oper[0]^.reg)=R_INTREGISTER) and
+                                (getregtype(oper[1]^.reg)=R_MMREGISTER) then
+                          begin
+                            Rm:=getsupreg(oper[0]^.reg);
+                            Rd:=getmmreg(oper[1]^.reg);
+                          end
+                        else
+                          message(asmw_e_invalid_opcode_and_operands);
 
-          bytes[0] = c | *codes++;
+                        bytes:=bytes or (((Rd and $1E) shr 1) shl 16);
+                        bytes:=bytes or ((Rd and $1) shl 7);
 
-          bytes[1] = *codes++;
+                        bytes:=bytes or (Rm shl 12);
+                      end;
+                  end;
+                PF_F32:
+                  begin
+                    if (getregtype(oper[0]^.reg)<>R_MMREGISTER) or
+                       (getregtype(oper[1]^.reg)<>R_MMREGISTER) then
+                      Message(asmw_e_invalid_opcode_and_operands);
 
-          bytes[3] = *codes;
+                    Rd:=getmmreg(oper[0]^.reg);
+                    Rm:=getmmreg(oper[1]^.reg);
 
-          // RdHi
-          bytes[1] |= regval (&ins->oprs[1],1);
-          if (has_S_code)
-            bytes[1] |= 0x10;
+                    bytes:=bytes or (((Rd and $1E) shr 1) shl 12);
+                    bytes:=bytes or ((Rd and $1) shl 22);
 
-          // RdLo
-          bytes[2] = regval (&ins->oprs[0],1) << 4;
-          // Rm
-          bytes[3] |= regval (&ins->oprs[2],1);
+                    bytes:=bytes or (((Rm and $1E) shr 1) shl 0);
+                    bytes:=bytes or ((Rm and $1) shl 5);
+                  end;
+                PF_F64:
+                  begin
+                    if (getregtype(oper[0]^.reg)<>R_MMREGISTER) or
+                       (getregtype(oper[1]^.reg)<>R_MMREGISTER) then
+                      Message(asmw_e_invalid_opcode_and_operands);
 
-          // Rs
-          bytes[2] |= regval (&ins->oprs[3],1);
+                    Rd:=getmmreg(oper[0]^.reg);
+                    Rm:=getmmreg(oper[1]^.reg);
 
-          break;
+                    bytes:=bytes or ((Rd and $F) shl 12);
+                    bytes:=bytes or (((Rd and $10) shr 4) shl 22);
 
-        case 0x17:      // LDR Rd, expression
-          ++codes;
+                    bytes:=bytes or (Rm and $F);
+                    bytes:=bytes or ((Rm and $10) shl 1);
+                  end;
+              end;
+            end;
+          #$41: // VMRS/VMSR
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set regs }
+              if opcode=A_VMRS then
+                begin
+                  case oper[1]^.reg of
+                    NR_FPSID: Rn:=$0;
+                    NR_FPSCR: Rn:=$1;
+                    NR_MVFR1: Rn:=$6;
+                    NR_MVFR0: Rn:=$7;
+                    NR_FPEXC: Rn:=$8;
+                  else
+                    message(asmw_e_invalid_opcode_and_operands);
+                  end;
 
-          bytes[0] = c | *codes++;
+                  bytes:=bytes or (Rn shl 16);
 
-          bytes[1] = *codes++;
+                  if oper[0]^.reg=NR_APSR_nzcv then
+                    bytes:=bytes or ($F shl 12)
+                  else
+                    bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+                end
+              else
+                begin
+                  case oper[0]^.reg of
+                    NR_FPSID: Rn:=$0;
+                    NR_FPSCR: Rn:=$1;
+                    NR_FPEXC: Rn:=$8;
+                  else
+                    message(asmw_e_invalid_opcode_and_operands);
+                  end;
 
-          // Rd
-          bytes[2] = regval (&ins->oprs[0],1) << 4;
-          if (has_B_code)
-            bytes[1] |= 0x40;
-          if (has_T_code)
-            {
-              errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
-            }
-          if (has_W_code)
-            {
-              errfunc (ERR_NONFATAL, "'!' not allowed");
-            }
+                  bytes:=bytes or (Rn shl 16);
 
-          // Rn - implicit R15
-          bytes[1] |= 0xF;
+                  bytes:=bytes or (getsupreg(oper[1]^.reg) shl 12);
+                end;
+            end;
+          #$42: // VMUL
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set regs }
+              if ops=3 then
+                begin
+                  Rd:=getmmreg(oper[0]^.reg);
+                  Rn:=getmmreg(oper[1]^.reg);
+                  Rm:=getmmreg(oper[2]^.reg);
+                end
+              else if oper[1]^.typ=top_const then
+                begin
+                  Rd:=getmmreg(oper[0]^.reg);
+                  Rn:=0;
+                  Rm:=0;
+                end
+              else
+                begin
+                  Rd:=getmmreg(oper[0]^.reg);
+                  Rn:=0;
+                  Rm:=getmmreg(oper[1]^.reg);
+                end;
 
-          if (ins->oprs[1].segment != segment)
-            {
-              errfunc (ERR_NONFATAL, "label not in same segment");
-            }
+              if oppostfix=PF_F32 then
+                begin
+                  D:=rd and $1; Rd:=Rd shr 1;
+                  N:=rn and $1; Rn:=Rn shr 1;
+                  M:=rm and $1; Rm:=Rm shr 1;
+                end
+              else
+                begin
+                  D:=(rd shr 4) and $1; Rd:=Rd and $F;
+                  N:=(rn shr 4) and $1; Rn:=Rn and $F;
+                  M:=(rm shr 4) and $1; Rm:=Rm and $F;
 
-          data = ins->oprs[1].offset - (offset + 8);
+                  bytes:=bytes or (1 shl 8);
+                end;
 
-          if (data < 0)
-            {
-              data = -data;
-            }
-          else
-            {
-              bytes[1] |= 0x80;
-            }
+              bytes:=bytes or (Rd shl 12);
+              bytes:=bytes or (Rn shl 16);
+              bytes:=bytes or (Rm shl 0);
 
-          if (data >= 0x1000)
-            {
-              errfunc (ERR_NONFATAL, "too long offset");
-            }
+              bytes:=bytes or (D shl 22);
+              bytes:=bytes or (N shl 7);
+              bytes:=bytes or (M shl 5);
+            end;
+          #$43: // VCVT
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set regs }
+              Rd:=getmmreg(oper[0]^.reg);
+              Rm:=getmmreg(oper[1]^.reg);
+
+              if (ops=2) and
+                 (oppostfix in [PF_F32F64,PF_F64F32]) then
+                begin
+                  if oppostfix=PF_F32F64 then
+                    begin
+                      bytes:=bytes or (1 shl 8);
 
-          bytes[2] |= ((data & 0xF00) >> 8);
-          bytes[3] = data & 0xFF;
-          break;
+                      D:=rd and $1; Rd:=Rd shr 1;
+                      M:=(rm shr 4) and $1; Rm:=Rm and $F;
+                    end
+                  else
+                    begin
+                      D:=(rd shr 4) and $1; Rd:=Rd and $F;
+                      M:=rm and $1; Rm:=Rm shr 1;
+                    end;
 
-        case 0x18:      // LDR Rd, [Rn]
-          ++codes;
+                  bytes:=bytes and $FFF0FFFF;
+                  bytes:=bytes or ($7 shl 16);
 
-          bytes[0] = c | *codes++;
+                  bytes:=bytes or (Rd shl 12);
+                  bytes:=bytes or (Rm shl 0);
 
-          bytes[1] = *codes++;
+                  bytes:=bytes or (D shl 22);
+                  bytes:=bytes or (M shl 5);
+                end
+              else if ops=2 then
+                begin
+                  case oppostfix of
+                    PF_S32F64,
+                    PF_U32F64,
+                    PF_F64S32,
+                    PF_F64U32:
+                      bytes:=bytes or (1 shl 8);
+                  end;
 
-          // Rd
-          bytes[2] = regval (&ins->oprs[0],1) << 4;
-          if (has_B_code)
-            bytes[1] |= 0x40;
-          if (has_T_code)
-            {
-              bytes[1] |= 0x20;         // write-back
-            }
-          else
-            {
-              bytes[0] |= 0x01;         // implicit pre-index mode
-            }
+                  if oppostfix in [PF_S32F32,PF_S32F64,PF_U32F32,PF_U32F64] then
+                    begin
+                      case oppostfix of
+                        PF_S32F64,
+                        PF_S32F32:
+                          bytes:=bytes or (1 shl 16);
+                      end;
 
-          if (has_W_code)
-            {
-              bytes[1] |= 0x20;         // write-back
-            }
+                      bytes:=bytes or (1 shl 18);
 
-          // Rn
-          c = regval (&ins->oprs[1],1);
-          bytes[1] |= c;
+                      D:=rd and $1; Rd:=Rd shr 1;
 
-          if (c == 0x15)                // R15
-            data = -8;
-          else
-            data = 0;
+                      if oppostfix in [PF_S32F64,PF_U32F64] then
+                        begin
+                          M:=(rm shr 4) and $1; Rm:=Rm and $F;
+                        end
+                      else
+                        begin
+                          M:=rm and $1; Rm:=Rm shr 1;
+                        end;
+                    end
+                  else
+                    begin
+                      case oppostfix of
+                        PF_F64S32,
+                        PF_F32S32:
+                          bytes:=bytes or (1 shl 7);
+                        else
+                          bytes:=bytes and $FFFFFF7F;
+                      end;
 
-          if (data < 0)
-            {
-              data = -data;
-            }
-          else
-            {
-              bytes[1] |= 0x80;
-            }
+                      M:=rm and $1; Rm:=Rm shr 1;
 
-          bytes[2] |= ((data & 0xF00) >> 8);
-          bytes[3] = data & 0xFF;
-          break;
-
-        case 0x19:      // LDR Rd, [Rn,#expression]
-        case 0x20:      // LDR Rd, [Rn,Rm]
-        case 0x21:      // LDR Rd, [Rn,Rm,shift]
-          ++codes;
-
-          bytes[0] = c | *codes++;
-
-          bytes[1] = *codes++;
-
-          // Rd
-          bytes[2] = regval (&ins->oprs[0],1) << 4;
-          if (has_B_code)
-            bytes[1] |= 0x40;
-
-          // Rn
-          c = regval (&ins->oprs[1],1);
-          bytes[1] |= c;
-
-          if (ins->oprs[ins->operands-1].bracket)       // FIXME: Bracket on last operand -> pre-index  <--
-            {
-              bytes[0] |= 0x01;         // pre-index mode
-              if (has_W_code)
-                {
-                  bytes[1] |= 0x20;
-                }
-              if (has_T_code)
-                {
-                  errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
-                }
-            }
-          else
-            {
-              if (has_T_code)           // Forced write-back in post-index mode
-                {
-                  bytes[1] |= 0x20;
-                }
-              if (has_W_code)
-                {
-                  errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
-                }
-            }
+                      if oppostfix in [PF_F64S32,PF_F64U32] then
+                        begin
+                          D:=(rd shr 4) and $1; Rd:=Rd and $F;
+                        end
+                      else
+                        begin
+                          D:=rd and $1; Rd:=Rd shr 1;
+                        end
+                    end;
 
-          if (keep == 0x19)
-            {
-              data = ins->oprs[2].offset;
+                  bytes:=bytes or (Rd shl 12);
+                  bytes:=bytes or (Rm shl 0);
 
-              if (data < 0)
-                {
-                  data = -data;
-                }
+                  bytes:=bytes or (D shl 22);
+                  bytes:=bytes or (M shl 5);
+                end
               else
-                {
-                  bytes[1] |= 0x80;
-                }
-
-              if (data >= 0x1000)
-                {
-                  errfunc (ERR_NONFATAL, "too long offset");
-                }
+                begin
+                  if rd<>rm then
+                    message(asmw_e_invalid_opcode_and_operands);
+
+                  case oppostfix of
+                    PF_S32F32,PF_U32F32,
+                    PF_F32S32,PF_F32U32,
+                    PF_S32F64,PF_U32F64,
+                    PF_F64S32,PF_F64U32:
+                      begin
+                        if not (oper[2]^.val in [1..32]) then
+                          message1(asmw_e_invalid_opcode_and_operands, 'fbits not within 1-32');
 
-              bytes[2] |= ((data & 0xF00) >> 8);
-              bytes[3] = data & 0xFF;
-            }
-          else
-            {
-              if (ins->oprs[2].minus == 0)
-                {
-                  bytes[1] |= 0x80;
-                }
-              c = regval (&ins->oprs[2],1);
-              bytes[3] = c;
-
-              if (keep == 0x21)
-                {
-                  c = ins->oprs[3].offset;
-                  if (c > 0x1F)
-                    {
-                      errfunc (ERR_NONFATAL, "too large shiftvalue");
-                      c = c & 0x1F;
-                    }
-
-                  bytes[2] |= c >> 1;
-                  if (c & 0x01)
-                    {
-                      bytes[3] |= 0x80;
-                    }
-                  bytes[3] |= shiftval (&ins->oprs[3]) << 5;
-                }
-            }
+                        bytes:=bytes or (1 shl 7);
+                        rn:=32;
+                      end;
+                    PF_S16F64,PF_U16F64,
+                    PF_F64S16,PF_F64U16,
+                    PF_S16F32,PF_U16F32,
+                    PF_F32S16,PF_F32U16:
+                      begin
+                        if not (oper[2]^.val in [0..16]) then
+                          message1(asmw_e_invalid_opcode_and_operands, 'fbits not within 0-16');
 
-          break;
+                        rn:=16;
+                      end;
+                  else
+                    message(asmw_e_invalid_opcode_and_operands);
+                  end;
 
-        case 0x22:      // LDRH Rd, expression
-          ++codes;
+                  case oppostfix of
+                    PF_S16F64,PF_U16F64,
+                    PF_S32F64,PF_U32F64,
+                    PF_F64S16,PF_F64U16,
+                    PF_F64S32,PF_F64U32:
+                      begin
+                        bytes:=bytes or (1 shl 8);
+                        D:=(rd shr 4) and $1; Rd:=Rd and $F;
+                      end;
+                  else
+                    begin
+                      D:=rd and $1; Rd:=Rd shr 1;
+                    end;
+                  end;
 
-          bytes[0] = c | 0x01;          // Implicit pre-index
+                  case oppostfix of
+                    PF_U16F64,PF_U16F32,
+                    PF_U32F32,PF_U32F64,
+                    PF_F64U16,PF_F32U16,
+                    PF_F32U32,PF_F64U32:
+                      bytes:=bytes or (1 shl 16);
+                  end;
 
-          bytes[1] = *codes++;
+                  if oppostfix in [PF_S32F32,PF_S32F64,PF_U32F32,PF_U32F64,PF_S16F32,PF_S16F64,PF_U16F32,PF_U16F64] then
+                    bytes:=bytes or (1 shl 18);
 
-          // Rd
-          bytes[2] = regval (&ins->oprs[0],1) << 4;
+                  bytes:=bytes or (Rd shl 12);
+                  bytes:=bytes or (D shl 22);
 
-          // Rn - implicit R15
-          bytes[1] |= 0xF;
+                  rn:=rn-oper[2]^.val;
 
-          if (ins->oprs[1].segment != segment)
-            {
-              errfunc (ERR_NONFATAL, "label not in same segment");
-            }
+                  bytes:=bytes or ((rn and $1) shl 5);
+                  bytes:=bytes or ((rn and $1E) shr 1);
+                end;
+            end;
+          #$44: // VLDM/VSTM/VPUSH/VPOP
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              { set regs }
+              if ops=2 then
+                begin
+                  if oper[0]^.typ=top_ref then
+                    begin
+                      Rn:=getsupreg(oper[0]^.ref^.base);
 
-          data = ins->oprs[1].offset - (offset + 8);
+                      if oper[0]^.ref^.addressmode<>AM_OFFSET then
+                        begin
+                          { set W }
+                          bytes:=bytes or (1 shl 21);
+                        end
+                      else if oppostfix = PF_DB then
+                        message1(asmw_e_invalid_opcode_and_operands, 'Invalid postfix without writeback');
+                    end
+                  else
+                    begin
+                      Rn:=getsupreg(oper[0]^.reg);
 
-          if (data < 0)
-            {
-              data = -data;
-            }
-          else
-            {
-              bytes[1] |= 0x80;
-            }
+                      if oppostfix = PF_DB then
+                        message1(asmw_e_invalid_opcode_and_operands, 'Invalid postfix without writeback');
+                    end;
 
-          if (data >= 0x100)
-            {
-              errfunc (ERR_NONFATAL, "too long offset");
-            }
-          bytes[3] = *codes++;
+                  bytes:=bytes or (Rn shl 16);
 
-          bytes[2] |= ((data & 0xF0) >> 4);
-          bytes[3] |= data & 0xF;
-          break;
+                  { Set PU bits }
+                  case oppostfix of
+                    PF_None,
+                    PF_IA:
+                      bytes:=bytes or (1 shl 23);
+                    PF_DB:
+                      bytes:=bytes or (2 shl 23);
+                  end;
 
-        case 0x23:      // LDRH Rd, Rn
-          ++codes;
+                  dp_operation:=(oper[1]^.subreg=R_SUBFD);
+                  if oper[1]^.regset^=[] then
+                    message1(asmw_e_invalid_opcode_and_operands, 'Regset cannot be empty');
 
-          bytes[0] = c | 0x01;          // Implicit pre-index
+                  for r:=0 to 31 do
+                    if r in oper[1]^.regset^ then
+                      begin
+                        rd:=r;
+                        break;
+                      end;
 
-          bytes[1] = *codes++;
+                  rn:=32-rd;
+                  for r:=rd+1 to 31 do
+                    if not(r in oper[1]^.regset^) then
+                      begin
+                        rn:=r-rd;
+                        break;
+                      end;
 
-          // Rd
-          bytes[2] = regval (&ins->oprs[0],1) << 4;
+                  if dp_operation then
+                    begin
+                      bytes:=bytes or (1 shl 8);
 
-          // Rn
-          c = regval (&ins->oprs[1],1);
-          bytes[1] |= c;
+                      bytes:=bytes or (rn*2);
 
-          if (c == 0x15)                // R15
-            data = -8;
-          else
-            data = 0;
+                      bytes:=bytes or ((rd and $F) shl 12);
+                      bytes:=bytes or (((rd and $10) shr 4) shl 22);
+                    end
+                  else
+                    begin
+                      bytes:=bytes or rn;
 
-          if (data < 0)
-            {
-              data = -data;
-            }
-          else
-            {
-              bytes[1] |= 0x80;
-            }
+                      bytes:=bytes or ((rd and $1) shl 22);
+                      bytes:=bytes or (((rd and $1E) shr 1) shl 12);
+                    end;
+                end
+              else { VPUSH/VPOP }
+                begin
+                  dp_operation:=(oper[0]^.subreg=R_SUBFD);
+                  if oper[0]^.regset^=[] then
+                    message1(asmw_e_invalid_opcode_and_operands, 'Regset cannot be empty');
 
-          if (data >= 0x100)
-            {
-              errfunc (ERR_NONFATAL, "too long offset");
-            }
-          bytes[3] = *codes++;
+                  for r:=0 to 31 do
+                    if r in oper[0]^.regset^ then
+                      begin
+                        rd:=r;
+                        break;
+                      end;
 
-          bytes[2] |= ((data & 0xF0) >> 4);
-          bytes[3] |= data & 0xF;
-          break;
+                  rn:=32-rd;
+                  for r:=rd+1 to 31 do
+                    if not(r in oper[0]^.regset^) then
+                      begin
+                        rn:=r-rd;
+                        break;
+                      end;
 
-        case 0x24:      // LDRH Rd, Rn, expression
-        case 0x25:      // LDRH Rd, Rn, Rm
-          ++codes;
+                  if dp_operation then
+                    begin
+                      bytes:=bytes or (1 shl 8);
 
-          bytes[0] = c;
+                      bytes:=bytes or (rn*2);
 
-          bytes[1] = *codes++;
+                      bytes:=bytes or ((rd and $F) shl 12);
+                      bytes:=bytes or (((rd and $10) shr 4) shl 22);
+                    end
+                  else
+                    begin
+                      bytes:=bytes or rn;
 
-          // Rd
-          bytes[2] = regval (&ins->oprs[0],1) << 4;
+                      bytes:=bytes or ((rd and $1) shl 22);
+                      bytes:=bytes or (((rd and $1E) shr 1) shl 12);
+                    end;
+                end;
+            end;
+          #$45: // VLDR/VSTR
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              { set regs }
+              rd:=getmmreg(oper[0]^.reg);
 
-          // Rn
-          c = regval (&ins->oprs[1],1);
-          bytes[1] |= c;
+              if getsubreg(oper[0]^.reg)=R_SUBFD then
+                begin
+                  bytes:=bytes or (1 shl 8);
 
-          if (ins->oprs[ins->operands-1].bracket)       // FIXME: Bracket on last operand -> pre-index  <--
-            {
-              bytes[0] |= 0x01;         // pre-index mode
-              if (has_W_code)
-                {
-                  bytes[1] |= 0x20;
-                }
-            }
-          else
-            {
-              if (has_W_code)
-                {
-                  errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
-                }
-            }
+                  bytes:=bytes or ((rd and $F) shl 12);
+                  bytes:=bytes or (((rd and $10) shr 4) shl 22);
+                end
+              else
+                begin
+                  bytes:=bytes or (((rd and $1E) shr 1) shl 12);
+                  bytes:=bytes or ((rd and $1) shl 22);
+                end;
 
-          bytes[3] = *codes++;
+              { set ref }
+              bytes:=bytes or getsupreg(oper[1]^.ref^.base) shl 16;
+              if getregtype(oper[1]^.ref^.index)=R_INVALIDREGISTER then
+                begin
+                  { set offset }
+                  offset:=0;
+                  currsym:=objdata.symbolref(oper[1]^.ref^.symbol);
+                  if assigned(currsym) then
+                    offset:=currsym.offset-insoffset-8;
+                  offset:=offset+oper[1]^.ref^.offset;
 
-          if (keep == 0x24)
-            {
-              data = ins->oprs[2].offset;
+                  offset:=offset div 4;
 
-              if (data < 0)
-                {
-                  data = -data;
-                }
+                  if offset>=0 then
+                    begin
+                      { set U flag }
+                      bytes:=bytes or (1 shl 23);
+                      bytes:=bytes or offset
+                    end
+                  else
+                    begin
+                      offset:=-offset;
+                      bytes:=bytes or offset
+                    end;
+                end
               else
-                {
-                  bytes[1] |= 0x80;
-                }
-
-              if (data >= 0x100)
-                {
-                  errfunc (ERR_NONFATAL, "too long offset");
-                }
-
-              bytes[2] |= ((data & 0xF0) >> 4);
-              bytes[3] |= data & 0xF;
-            }
+                message(asmw_e_invalid_opcode_and_operands);
+            end;
+          #$fe: // No written data
+            begin
+              exit;
+            end;
+          #$ff:
+            internalerror(2005091101);
           else
-            {
-              if (ins->oprs[2].minus == 0)
-                {
-                  bytes[1] |= 0x80;
-                }
-              c = regval (&ins->oprs[2],1);
-              bytes[3] |= c;
-
-            }
-          break;
-
-        case 0x26:      // LDM/STM Rn, {reg-list}
-          ++codes;
-
-          bytes[0] = c;
-
-          bytes[0] |= ( *codes >> 4) & 0xF;
-          bytes[1] = ( *codes << 4) & 0xF0;
-          ++codes;
-
-          if (has_W_code)
-            {
-              bytes[1] |= 0x20;
-            }
-          if (has_F_code)
-            {
-              bytes[1] |= 0x40;
-            }
-
-          // Rn
-          bytes[1] |= regval (&ins->oprs[0],1);
-
-          data = ins->oprs[1].basereg;
-
-          bytes[2] = ((data >> 8) & 0xFF);
-          bytes[3] = (data & 0xFF);
-
-          break;
-
-        case 0x27:      // SWP Rd, Rm, [Rn]
-          ++codes;
-
-          bytes[0] = c;
-
-          bytes[0] |= *codes++;
-
-          bytes[1] = regval (&ins->oprs[2],1);
-          if (has_B_code)
-            {
-              bytes[1] |= 0x40;
-            }
-          bytes[2] = regval (&ins->oprs[0],1) << 4;
-          bytes[3] = *codes++;
-          bytes[3] |= regval (&ins->oprs[1],1);
-          break;
-
-        default:
-          errfunc (ERR_FATAL, "unknown decoding of instruction");
-
-          bytes[0] = c;
-          // And a fix nibble
-          ++codes;
-          bytes[0] |= *codes++;
-
-         if ( *codes == 0x01)           // An I bit
-           {
-
-           }
-         if ( *codes == 0x02)           // An I bit
-           {
-
-           }
-         ++codes;
-      }
-    out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
-}
+            begin
+              writeln(ord(insentry^.code[0]), ' - ', opcode);
+              internalerror(2005091102);
+            end;
+        end;
+        { we're finished, write code }
+        objdata.writebytes(bytes,bytelen);
+      end;
 
-*)
-{$endif dummy}
 
-  constructor tai_thumb_func.create;
-    begin
-      inherited create;
-      typ:=ait_thumb_func;
-    end;
+    constructor tai_thumb_func.create;
+      begin
+        inherited create;
+        typ:=ait_thumb_func;
+      end;
 
 begin
   cai_align:=tai_align;

compiler/arm/armatt.inc

@@ -1,10 +1,6 @@
 { don't edit, this file is generated from armins.dat }
 (
 'none',
-'abs',
-'acs',
-'asn',
-'atn',
 'adc',
 'add',
 'adf',
@@ -17,24 +13,18 @@
 'bkpt',
 'bx',
 'cdp',
-'cmf',
-'cmfe',
 'cmn',
 'cmp',
+'cmf',
+'cmfe',
+'stf',
+'ldf',
+'lfm',
 'clz',
-'cnf',
-'cos',
 'cps',
 'cpsid',
 'cpsie',
-'dvf',
 'eor',
-'exp',
-'fdv',
-'flt',
-'fix',
-'fml',
-'frd',
 'ldc',
 'ldm',
 'ldrbt',
@@ -44,41 +34,31 @@
 'ldrsb',
 'ldrsh',
 'ldrt',
-'ldf',
-'lfm',
-'lgn',
-'log',
 'mcr',
+'mcr2',
+'mrc',
+'mrc2',
+'mcrr',
+'mcrr2',
+'mrrc',
+'mrrc2',
 'mla',
 'mov',
-'mrc',
 'mrs',
 'msr',
-'mnf',
-'muf',
 'mul',
 'mvf',
 'mvn',
+'vmov',
 'nop',
 'orr',
-'rdf',
-'rfs',
-'rfc',
-'rmf',
-'rpw',
 'rsb',
 'rsc',
-'rsf',
-'rnd',
-'pol',
 'sbc',
 'sfm',
 'sin',
 'smlal',
 'smull',
-'sqt',
-'suf',
-'stf',
 'stm',
 'str',
 'strb',
@@ -89,16 +69,14 @@
 'swi',
 'swp',
 'swpb',
-'tan',
 'teq',
 'tst',
 'umlal',
 'umull',
 'wfs',
 'ldrd',
-'mcrr',
-'mrrc',
 'pld',
+'pldw',
 'qadd',
 'qdadd',
 'qdsub',
@@ -113,6 +91,12 @@
 'smlaltt',
 'smlawb',
 'smlawt',
+'vldm',
+'vstm',
+'vpop',
+'vpush',
+'vldr',
+'vstr',
 'smulbb',
 'smulbt',
 'smultb',
@@ -120,67 +104,15 @@
 'smulwb',
 'smulwt',
 'strd',
-'fabsd',
-'fabss',
-'faddd',
-'fadds',
-'fcmpd',
-'fcmped',
-'fcmpes',
-'fcmpezd',
-'fcmpezs',
-'fcmps',
-'fcmpzd',
-'fcmpzs',
-'fcpyd',
-'fcpys',
-'fcvtds',
-'fcvtsd',
-'fdivd',
-'fdivs',
-'fldd',
-'fldm',
-'flds',
-'fmacd',
-'fmacs',
-'fmdhr',
-'fmdlr',
-'fmrdh',
-'fmrdl',
-'fmrs',
-'fmrx',
-'fmscd',
-'fmscs',
-'fmsr',
-'fmstat',
-'fmuld',
-'fmuls',
-'fmxr',
-'fnegd',
-'fnegs',
-'fnmacd',
-'fnmacs',
-'fnmscd',
-'fnmscs',
-'fnmuld',
-'fnmuls',
-'fsitod',
-'fsitos',
-'fsqrtd',
-'fsqrts',
+'ldrht',
+'strht',
+'ldrsbt',
+'strsbt',
+'ldrsht',
+'strsht',
 'fstd',
 'fstm',
 'fsts',
-'fsubd',
-'fsubs',
-'ftosid',
-'ftosis',
-'ftouid',
-'ftouis',
-'fuitod',
-'fuitos',
-'fmdrr',
-'fmrrd',
 'bfc',
 'bfi',
 'clrex',
@@ -188,8 +120,13 @@
 'ldrexb',
 'ldrexd',
 'ldrexh',
+'strex',
+'strexb',
+'strexd',
+'strexh',
 'mls',
-'pkh',
+'pkhbt',
+'pkhtb',
 'pli',
 'qadd16',
 'qadd8',
@@ -212,6 +149,8 @@
 'lsr',
 'lsl',
 'ror',
+'rrx',
+'umaal',
 'shadd16',
 'shadd8',
 'shasx',
@@ -233,49 +172,102 @@
 'ssax',
 'ssub16',
 'ssub8',
-'strex',
-'strexb',
-'strexd',
-'strexh',
 'sxtab',
 'sxtab16',
 'sxtah',
+'ubfx',
+'uxtab',
+'uxtab16',
+'uxtah',
 'sxtb',
 'sxtb16',
+'sxth',
 'uxtb',
+'uxtb16',
 'uxth',
-'sxth',
 'uadd16',
 'uadd8',
 'uasx',
-'ubfx',
 'uhadd16',
 'uhadd8',
 'uhasx',
 'uhsax',
 'uhsub16',
 'uhsub8',
-'umaal',
 'uqadd16',
 'uqadd8',
 'uqasx',
 'uqsax',
 'uqsub16',
 'uqsub8',
-'uqsad8',
-'uqsada8',
+'usad8',
+'usada8',
 'usat',
 'usat16',
 'usax',
 'usub16',
 'usub8',
-'uxtab',
-'uxtab16',
-'uxtah',
-'uxtb16',
 'wfe',
 'wfi',
 'yield',
+'fabsd',
+'fabss',
+'faddd',
+'fadds',
+'fcmpd',
+'fcmped',
+'fcmpes',
+'fcmpezd',
+'fcmpezs',
+'fcmps',
+'fcmpzd',
+'fcmpzs',
+'fcpyd',
+'fcpys',
+'fcvtds',
+'fcvtsd',
+'fdivd',
+'fdivs',
+'fldd',
+'fldm',
+'flds',
+'fmacd',
+'fmacs',
+'fmdhr',
+'fmdlr',
+'fmrdh',
+'fmrdl',
+'fmrs',
+'fmrx',
+'fmscd',
+'fmscs',
+'fmsr',
+'fmstat',
+'fmuld',
+'fmuls',
+'fmxr',
+'fnegd',
+'fnegs',
+'fnmacd',
+'fnmacs',
+'fnmscd',
+'fnmscs',
+'fnmuld',
+'fnmuls',
+'fsitod',
+'fsitos',
+'fsqrtd',
+'fsqrts',
+'fsubd',
+'fsubs',
+'ftosid',
+'ftosis',
+'ftouid',
+'ftouis',
+'fuitod',
+'fuitos',
+'fmdrr',
+'fmrrd',
 'pop',
 'push',
 'sdiv',
@@ -306,29 +298,57 @@
 'vcmp',
 'vcmpe',
 'vcvt',
+'vcvtr',
 'vdiv',
-'vldm',
-'vldr',
-'vmov',
 'vmrs',
 'vmsr',
-'vmul',
 'vmla',
 'vmls',
+'vmul',
 'vnmla',
 'vnmls',
+'vnmul',
 'vfma',
 'vfms',
 'vfnma',
 'vfnms',
 'vneg',
-'vnmul',
-'vpop',
-'vpush',
 'vsqrt',
-'vstm',
-'vstr',
 'vsub',
+'dmb',
+'isb',
+'dsb',
+'smc',
 'neg',
-'svc'
+'svc',
+'bxj',
+'udf',
+'tan',
+'sqt',
+'suf',
+'rsf',
+'rnd',
+'pol',
+'rdf',
+'rfs',
+'rfc',
+'rmf',
+'rpw',
+'mnf',
+'muf',
+'abs',
+'acs',
+'asn',
+'atn',
+'cnf',
+'cos',
+'dvf',
+'exp',
+'fdv',
+'flt',
+'fix',
+'fml',
+'frd',
+'lgn',
+'log'
 );

compiler/arm/armatts.inc

@@ -330,5 +330,25 @@ attsufNONE,
 attsufNONE,
 attsufNONE,
 attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
 attsufNONE
 );

compiler/arm/armins.dat

@@ -85,470 +85,394 @@
 [NONE]
 void                  void                            none
 
-[ABScc]
-
-[ACScc]
-
-[ASNcc]
-
-[ATNcc]
-
 [ADCcc]
-reg32,reg32,reg32        \4\x0\xA0                     ARM7
-reg32,reg32,reg32,reg32  \5\x0\xA0                     ARM7
-reg32,reg32,reg32,imm    \6\x0\xA0                     ARM7
-reg32,reg32,imm          \7\x2\xA0                     ARM7
+reg32,reg32,reg32           \4\x0\xA0                     ARM32,ARMv4
+reg32,reg32,reg32,shifterop \6\x0\xA0                     ARM32,ARMv4
+reg32,reg32,immshifter      \7\x2\xA0                     ARM32,ARMv4
 
 [ADDcc]
-reg32,reg32,reg32        \4\x0\x80                     ARM7
-reg32,reg32,reg32,reg32  \5\x0\x80                     ARM7
-reg32,reg32,reg32,imm    \6\x0\x80                     ARM7
-reg32,reg32,imm          \7\x2\x80                     ARM7
+reg32,reg32,reg32           \4\x0\x80                     ARM32,ARMv4
+reg32,reg32,reg32,shifterop \6\x0\x80                     ARM32,ARMv4
+reg32,reg32,immshifter      \7\x2\x80                     ARM32,ARMv4
 
 [ADFcc]
 
 [ADRcc]
+reg32,immshifter            \x33\x2\x0F                   ARM32,ARMv4
+reg32,imm32                 \x33\x2\x0F                   ARM32,ARMv4
+reg32,memam2                \x33\x2\x0F                   ARM32,ARMv4
 
 [ANDcc]
-reg32,reg32,reg32        \4\x0\x00                     ARM7
-reg32,reg32,reg32,reg32  \5\x0\x00                     ARM7
-reg32,reg32,reg32,imm    \6\x0\x00                     ARM7
-reg32,reg32,imm          \7\x2\x00                     ARM7
+reg32,reg32,reg32           \x4\x0\x00                    ARM32,ARMv4
+reg32,reg32,reg32,shifterop \x6\x0\x00                    ARM32,ARMv4
+reg32,reg32,immshifter      \x7\x2\x00                    ARM32,ARMv4
 
 [Bcc]
-mem32                    \1\x0A                        ARM7
-imm24                    \1\x0A                        ARM7
+mem32                       \x1\x0A                       ARM32,ARMv4
+imm                         \x1\x0A                       ARM32,ARMv4
+immshifter                  \x1\x0A                       ARM32,ARMv4
 
 [BICcc]
-reg32,reg32,reg32        \4\x1\xC0                     ARM7
-reg32,reg32,reg32,reg32  \5\x1\xC0                     ARM7
-reg32,reg32,reg32,imm    \6\x1\xC0                     ARM7
-reg32,reg32,imm          \7\x3\xC0                     ARM7
+reg32,reg32,reg32           \x6\x1\xC0                    ARM32,ARMv4
+reg32,reg32,reg32,shifterop \x6\x1\xC0                    ARM32,ARMv4
+reg32,reg32,immshifter      \x7\x3\xC0                    ARM32,ARMv4
 
 [BLcc]
-mem32                    \1\x0B                        ARM7
-imm24                    \1\x0B                        ARM7
+mem32                    \x1\x0B                        ARM32,ARMv4
+imm                      \x1\x0B                        ARM32,ARMv4
+immshifter               \x1\x0B                        ARM32,ARMv4
 
 [BLX]
-mem32                    \xff                        ARM7
-imm24                    \xff                        ARM7
+mem32                    \x28\xFA                      ARM32,ARMv4
+imm                      \x28\xFA                      ARM32,ARMv4
+immshifter               \x28\xFA                      ARM32,ARMv4
+reg32                    \3\x01\x2F\xFF\x30            ARM32,ARMv4
 
 [BKPTcc]
+imm                      \x31\x1\x20\x70               ARM32,ARMv5T
+immshifter               \x31\x1\x20\x70               ARM32,ARMv5T
 
 [BXcc]
-reg32                    \3\x01\x2F\xFF\x10            ARM7
+reg32                    \3\x01\x2F\xFF\x10            ARM32,ARMv4
 
 [CDP]
-reg8,reg8           \300\1\x10\101                ARM7
+reg8,reg8                \300\1\x10\101                ARM32,ARMv4
+
+[CMNcc]
+reg32,reg32              \xC\x1\x60                     ARM32,ARMv4
+reg32,reg32,shifterop    \xE\x1\x60                     ARM32,ARMv4
+reg32,immshifter         \xF\x1\x60                     ARM32,ARMv4
+
+[CMPcc]
+reg32,reg32              \xC\x1\x40                     ARM32,ARMv4
+reg32,reg32,shifterop    \xE\x1\x40                     ARM32,ARMv4
+reg32,immshifter         \xF\x3\x40                     ARM32,ARMv4
 
 [CMFcc]
 
 [CMFEcc]
 
-[CMNcc]
-reg32,reg32              \xC\x1\x60                     ARM7
-reg32,reg32,reg32        \xD\x1\x60                     ARM7
-reg32,reg32,imm          \xE\x1\x60                     ARM7
-reg32,imm                \xF\x3\x60                     ARM7
-
-[CMPcc]
-reg32,reg32              \xC\x1\x40                     ARM7
-reg32,reg32,reg32        \xD\x1\x40                     ARM7
-reg32,reg32,imm          \xE\x1\x40                     ARM7
-reg32,imm                \xF\x3\x40                     ARM7
+[STFcc]
 
-[CLZcc]
-reg32,reg32              \x27\x01\x01                   ARM7
+[LDFcc]
 
-[CNFcc]
+[LFMcc]
+reg32,imm8,fpureg        \xF0\x02\x01                   FPA
 
-[COScc]
+[CLZcc]
+reg32,reg32              \x32\x01\x6F\xF\x10            ARM32,ARMv4
 
 [CPS]
 [CPSID]
 [CPSIE]
 
-[DVFcc]
-
 [EORcc]
-reg32,reg32,reg32        \4\x0\x20                     ARM7
-reg32,reg32,reg32,reg32  \5\x0\x20                     ARM7
-reg32,reg32,reg32,imm    \6\x0\x20                     ARM7
-reg32,reg32,imm          \7\x2\x20                     ARM7
-
-[EXPcc]
-
-[FDVcc]
-
-[FLTcc]
-
-[FIXcc]
-
-[FMLcc]
-
-[FRDcc]
+reg32,reg32,reg32           \4\x0\x20                     ARM32,ARMv4
+reg32,reg32,reg32,shifterop \6\x0\x20                     ARM32,ARMv4
+reg32,reg32,immshifter      \7\x2\x20                     ARM32,ARMv4
 
 [LDC]
-reg32,reg32         \321\300\1\x11\101            ARM7
+reg32,reg32         \321\300\1\x11\101            ARM32,ARMv4
 
 [LDMcc]
-memam4,reglist		   \x26\x81			ARM7
+memam4,reglist		   \x26\x81			ARM32,ARMv4
+reg32,reglist		   \x26\x81			ARM32,ARMv4
 
 [LDRBTcc]
+reg32,memam2              \x17\x04\x70                           ARM32,ARMv4
+reg32,immshifter          \x17\x04\x70                           ARM32,ARMv4
 
 [LDRBcc]
-reg32,memam2              \x17\x07\x10                            ARM7
+reg32,memam2              \x17\x04\x50                            ARM32,ARMv4
 
 [LDRcc]
-reg32,memam2              \x17\x05\x10                   ARM7
-; reg32,imm32              \x17\x05\x10                   ARM7
-; reg32,reg32              \x18\x04\x10                   ARM7
-; reg32,reg32,imm32        \x19\x04\x10                   ARM7
-; reg32,reg32,reg32        \x20\x06\x10                   ARM7
-; reg32,reg32,reg32,imm32  \x21\x06\x10                   ARM7
+reg32,memam2              \x17\x04\x10                   ARM32,ARMv4
 
 [LDRHcc]
-reg32,imm32              \x22\x50\xB0               ARM7
-reg32,reg32              \x23\x50\xB0               ARM7
-reg32,reg32,imm32        \x24\x50\xB0                   ARM7
-reg32,reg32,reg32        \x25\x10\xB0                   ARM7
+reg32,memam2              \x22\x10\xB0               ARM32,ARMv4
 
 [LDRSBcc]
-reg32,imm32              \x22\x50\xD0               ARM7
-reg32,reg32              \x23\x50\xD0               ARM7
-reg32,reg32,imm32        \x24\x50\xD0                   ARM7
-reg32,reg32,reg32        \x25\x10\xD0                   ARM7
+reg32,memam2             \x22\x10\xD0               ARM32,ARMv4
+reg32,reg32              \x23\x50\xD0               ARM32,ARMv4
+reg32,reg32,imm32        \x24\x50\xD0                   ARM32,ARMv4
+reg32,reg32,reg32        \x25\x10\xD0                   ARM32,ARMv4
 
 [LDRSHcc]
-reg32,imm32              \x22\x50\xF0               ARM7
-reg32,reg32              \x23\x50\xF0               ARM7
-reg32,reg32,imm32        \x24\x50\xF0                   ARM7
-reg32,reg32,reg32        \x25\x10\xF0                   ARM7
+reg32,memam2              \x22\x10\xF0               ARM32,ARMv4
 
 [LDRTcc]
+reg32,memam2              \x17\x04\x30                   ARM32,ARMv4
 
-[LDFcc]
+[MCRcc]
+regf,immshifter,reg32,regf,regf              \x1C\xE\x0\x1     ARM32,ARMv4
+regf,immshifter,reg32,regf,regf,immshifter   \x1C\xE\x0\x1     ARM32,ARMv4
 
-[LFMcc]
-reg32,imm8,fpureg        \xF0\x02\x01                   FPA
+[MCR2cc]
+regf,immshifter,reg32,regf,regf              \x1C\xFE\x0\x1    ARM32,ARMv5T
+regf,immshifter,reg32,regf,regf,immshifter   \x1C\xFE\x0\x1    ARM32,ARMv5T
 
-[LGNcc]
+[MRCcc]
+regf,immshifter,reg32,regf,regf              \x1C\xE\x10\x1    ARM32,ARMv4
+regf,immshifter,reg32,regf,regf,immshifter   \x1C\xE\x10\x1    ARM32,ARMv4
 
-[LOGcc]
+[MRC2cc]
+regf,immshifter,reg32,regf,regf              \x1C\xFE\x10\x1   ARM32,ARMv5T
+regf,immshifter,reg32,regf,regf,immshifter   \x1C\xFE\x10\x1   ARM32,ARMv5T
+
+[MCRRcc]
+regf,immshifter,reg32,reg32,regf             \x1D\xC\x40\x0    ARM32,ARMv5TE
+
+[MCRR2cc]
+regf,immshifter,reg32,reg32,regf             \x1D\xFC\x40\x0   ARM32,ARMv6
+
+[MRRCcc]
+regf,immshifter,reg32,reg32,regf             \x1D\xC\x50\x0    ARM32,ARMv5TE
 
-[MCR]
-; reg32,mem32         \320\301\1\x13\110            ARM7
+[MRRC2cc]
+regf,immshifter,reg32,reg32,regf             \x1D\xFC\x50\x0   ARM32,ARMv6
 
 [MLAcc]
-reg32,reg32,reg32,reg32  \x15\x00\x20\x90               ARM7
+reg32,reg32,reg32,reg32  \x15\x00\x20\x9                ARM32,ARMv4
 
 [MOVcc]
-; reg32,shifterop              \x8\x0\0xd                   ARM7
-; reg32,immshifter             \x8\x0\0xd                  ARM7
-; reg32,reg32,reg32        \x9\x1\xA0                     ARM7
-; reg32,reg32,imm          \xA\x1\xA0                     ARM7
-; reg32,imm                \xB\x3\xA0                     ARM7
-
-[MRC]
-; reg32,reg32         \321\301\1\x13\110                  ARM7
+reg32,shifterop        \x8\x1\xA0                       ARM32,ARMv4
+reg32,reg32,shifterop  \xA\x1\xA0                       ARM32,ARMv4
+reg32,immshifter       \xB\x1\xA0                       ARM32,ARMv4
 
 [MRScc]
-reg32,reg32         \x10\x01\x0F                        ARM7
+reg32,reg32         \x10\x01\x0F                        ARM32,ARMv4
 
 [MSRcc]
-reg32,reg32         \x11\x01\x29\xF0                    ARM7
-regf,reg32          \x12\x01\x28\xF0                    ARM7
-regf,imm            \x13\x03\x28\xF0                    ARM7
-
-[MNFcc]
-
-[MUFcc]
+reg32,reg32         \x11\x01\x29\xF0                    ARM32,ARMv4
+regf,reg32          \x12\x01\x28\xF0                    ARM32,ARMv4
+regf,imm            \x13\x03\x28\xF0                    ARM32,ARMv4
 
 [MULcc]
-reg32,reg32,reg32        \x14\x00\x00\x90          ARM7
+reg32,reg32,reg32      \x14\x00\x00\x90          ARM32,ARMv4
 
 [MVFcc]
 fpureg,fpureg              \xF2                      FPA
 fpureg,immfpu              \xF2                      FPA
 
 [MVNcc]
-; reg32,reg32         \x8\x0\0xf                     ARM7
-; reg32,reg32,reg32   \x9\x1\xE0                     ARM7
-; reg32,reg32,imm     \xA\x1\xE0                     ARM7
-; reg32,imm           \xB\x3\xE0                     ARM7
+reg32,reg32            \x8\x1\xE0                       ARM32,ARMv4
+reg32,reg32,shifterop  \xA\x1\xE0                       ARM32,ARMv4
+reg32,immshifter       \xB\x1\xE0                       ARM32,ARMv4
 
-[NOP]
+[VMOVcc]
+vreg,vreg         \x40\xE\xB0\xA\x40            ARM32,VFPv2
 
-[ORRcc]
-reg32,reg32,reg32        \4\x1\x80                     ARM7
-reg32,reg32,reg32,reg32  \5\x1\x80                     ARM7
-reg32,reg32,reg32,imm    \6\x1\x80                     ARM7
-reg32,reg32,imm          \7\x3\x80                     ARM7
+reg32,vreg        \x40\xE\x10\xA\x10            ARM32,VFPv2
+vreg,reg32        \x40\xE\x00\xA\x10            ARM32,VFPv2
 
-[RDFcc]
+reg32,reg32,vreg,vreg \x40\xC\x50\xA\x10        ARM32,VFPv2
+vreg,vreg,reg32,reg32 \x40\xC\x40\xA\x10        ARM32,VFPv2
 
-[RFScc]
-
-[RFCcc]
+reg32,reg32,vreg      \x40\xC\x50\xB\x10        ARM32,VFPv2
+vreg,reg32,reg32      \x40\xC\x40\xB\x10        ARM32,VFPv2
 
-[RMFcc]
+[NOP]
+void                    \x2F\x03\x20\xF0\x0           ARM32,ARMv6K
 
-[RPWcc]
+[ORRcc]
+reg32,reg32,reg32            \4\x1\x80               ARM32,ARMv4
+reg32,reg32,reg32,reg32      \5\x1\x80               ARM32,ARMv4
+reg32,reg32,reg32,shifterop  \6\x1\x80               ARM32,ARMv4
+reg32,reg32,immshifter       \7\x3\x80               ARM32,ARMv4
 
 [RSBcc]
-reg32,reg32,reg32        \4\x0\x60                     ARM7
-reg32,reg32,reg32,reg32  \5\x0\x60                     ARM7
-reg32,reg32,reg32,imm    \6\x0\x60                     ARM7
-reg32,reg32,imm          \7\x2\x60                     ARM7
+reg32,reg32,reg32            \6\x0\x60                     ARM32,ARMv4
+reg32,reg32,reg32,shifterop  \6\x0\x60                     ARM32,ARMv4
+reg32,reg32,immshifter       \7\x0\x60                     ARM32,ARMv4
 
 [RSCcc]
-reg32,reg32,reg32        \4\x0\xE0                     ARM7
-reg32,reg32,reg32,reg32  \5\x0\xE0                     ARM7
-reg32,reg32,reg32,imm    \6\x0\xE0                     ARM7
-reg32,reg32,imm          \7\x2\xE0                     ARM7
-
-[RSFcc]
-
-[RNDcc]
-
-[POLcc]
+reg32,reg32,reg32            \4\x0\xE0                     ARM32,ARMv4
+reg32,reg32,reg32,reg32      \5\x0\xE0                     ARM32,ARMv4
+reg32,reg32,reg32,shifterop  \6\x0\xE0                     ARM32,ARMv4
+reg32,reg32,immshifter       \7\x2\xE0                     ARM32,ARMv4
 
 [SBCcc]
-reg32,reg32,reg32        \4\x0\xC0                     ARM7
-reg32,reg32,reg32,reg32  \5\x0\xC0                     ARM7
-reg32,reg32,reg32,imm    \6\x0\xC0                     ARM7
-reg32,reg32,imm          \7\x2\xC0                     ARM7
+reg32,reg32,reg32           \4\x0\xC0                     ARM32,ARMv4
+reg32,reg32,reg32,reg32     \5\x0\xC0                     ARM32,ARMv4
+reg32,reg32,reg32,imm       \6\x0\xC0                     ARM32,ARMv4
+reg32,reg32,reg32,shifterop \6\x0\xC0                     ARM32,ARMv4
+reg32,reg32,immshifter      \7\x2\xC0                     ARM32,ARMv4
 
 [SFMcc]
-reg32,imm8,fpureg        \xF0\x02\x00                   FPA
+reg32,imm8,fpureg           \xF0\x02\x00                  FPA
 
 [SINcc]
 
 [SMLALcc]
-reg32,reg32,reg32,reg32  \x16\x00\xE0\x90		 ARM7
+reg32,reg32,reg32,reg32     \x16\x00\xE0\x9               ARM32,ARMv4
 
 [SMULLcc]
-reg32,reg32,reg32,reg32  \x16\x00\xC0\x90		 ARM7
-
-[SQTcc]
-
-[SUFcc]
-
-[STFcc]
+reg32,reg32,reg32,reg32     \x16\x00\xC0\x9               ARM32,ARMv4
 
 [STMcc]
-memam4,reglist		   \x26\x80			ARM7
+memam4,reglist		          \x26\x80			   ARM32,ARMv4
+reg32,reglist		          \x26\x80			   ARM32,ARMv4
 
 [STRcc]
-reg32,memam2              \x17\x04\x00                   ARM7
-; reg32,imm32              \x17\x05\x00                   ARM7
-; reg32,reg32              \x18\x04\x00                   ARM7
-; reg32,reg32,imm32        \x19\x04\x00                   ARM7
-; reg32,reg32,reg32        \x20\x06\x00                   ARM7
-; reg32,reg32,reg32,imm32  \x21\x06\x00                   ARM7
+reg32,memam2                \x17\x04\x00                   ARM32,ARMv4
 
 [STRBcc]
-reg32,memam2              \x17\x06\x00                           ARM7
+reg32,memam2                \x17\x04\x40                           ARM32,ARMv4
 
 [STRBTcc]
+reg32,memam2                \x17\x04\x60                           ARM32,ARMv4
+reg32,immshifter            \x17\x04\x60                           ARM32,ARMv4
 
-; A dummy since it is parsed as STR{cond}H
 [STRHcc]
-reg32,imm32              \x22\x40\xB0              ARM7
-reg32,reg32              \x23\x40\xB0               ARM7
-reg32,reg32,imm32        \x24\x40\xB0                   ARM7
-reg32,reg32,reg32        \x25\x00\xB0                   ARM7
+reg32,memam2                \x22\x00\xB0              ARM32,ARMv4
 
 [STRTcc]
+reg32,memam2                \x17\x04\x20                   ARM32,ARMv4
 
 [SUBcc]
-reg32,reg32,shifterop     \4\x0\x40                     ARM7
-reg32,reg32,immshifter    \4\x0\x40                     ARM7
-reg32,reg32,reg32        \4\x0\x40                     ARM7
-; reg32,reg32,reg32,reg32  \5\x0\x40                     ARM7
-; reg32,reg32,reg32,imm    \6\x0\x40                     ARM7
-; reg32,reg32,imm          \7\x2\x40                     ARM7
+reg32,reg32,shifterop       \x4\x0\x40                     ARM32,ARMv4
+reg32,reg32,immshifter      \x4\x0\x40                     ARM32,ARMv4
+reg32,reg32,reg32           \x4\x0\x40                     ARM32,ARMv4
+reg32,reg32,reg32,shifterop \x6\x0\x40                     ARM32,ARMv4
 
 [SWIcc]
-imm                 \2\x0F                        ARM7
+imm                         \x2\x0F                        ARM32,ARMv4
+immshifter                  \x2\x0F                        ARM32,ARMv4
 
 [SWPcc]
-reg32,reg32,reg32   \x27\x01\x90                   ARM7
+reg32,reg32,memam2          \x27\x10\x09                   ARM32,ARMv4
 
 [SWPBcc]
-reg32,reg32,reg32   \x27\x01\x90                   ARM7
-
-[TANcc]
+reg32,reg32,memam2          \x27\x14\x09                   ARM32,ARMv4
 
 [TEQcc]
-reg32,reg32         \xC\x1\x20                     ARM7
-reg32,reg32,reg32   \xD\x1\x20                     ARM7
-reg32,reg32,imm     \xE\x1\x20                     ARM7
-reg32,imm           \xF\x3\x20                     ARM7
+reg32,reg32           \xC\x1\x20                     ARM32,ARMv4
+reg32,reg32,reg32     \xD\x1\x20                     ARM32,ARMv4
+reg32,reg32,shifterop \xE\x1\x20                     ARM32,ARMv4
+reg32,immshifter      \xF\x3\x20                     ARM32,ARMv4
 
 [TSTcc]
-reg32,reg32         \xC\x1\x00                     ARM7
-reg32,reg32,reg32   \xD\x1\x00                     ARM7
-reg32,reg32,imm     \xE\x1\x00                     ARM7
-reg32,imm           \xF\x3\x00                     ARM7
+reg32,reg32           \xC\x1\x00                     ARM32,ARMv4
+reg32,reg32,reg32     \xD\x1\x00                     ARM32,ARMv4
+reg32,reg32,shifterop \xE\x1\x00                     ARM32,ARMv4
+reg32,immshifter      \xF\x3\x00                     ARM32,ARMv4
 
 [UMLALcc]
-reg32,reg32,reg32,reg32  \x16\x00\xA0\x90		 ARM7
+reg32,reg32,reg32,reg32     \x16\x00\xA0\x9         ARM32,ARMv4
 
 [UMULLcc]
-reg32,reg32,reg32,reg32  \x16\x00\x80\x90		 ARM7
+reg32,reg32,reg32,reg32     \x16\x00\x80\x9         ARM32,ARMv4
 
 [WFScc]
 
 ; EDSP instructions
 [LDRDcc]
-
-[MCRRcc]
-
-[MRRCcc]
+reg32,reg32,memam2        \x19\x0\x0\x0\xD0           ARM32,ARMv4
 
 [PLD]
+memam2                     \x25\xF7\x50\xF0\x0                 ARM32,ARMv5TE
+
+[PLDW]
+memam2                     \x25\xF7\x10\xF0\x0                 ARM32,ARMv7
 
 [QADDcc]
+reg32,reg32,reg32          \x1A\x01\x00\x05                    ARM32,ARMv5TE
 
 [QDADDcc]
+reg32,reg32,reg32          \x1A\x01\x40\x05                    ARM32,ARMv5TE
 
 [QDSUBcc]
+reg32,reg32,reg32          \x1A\x01\x60\x05                    ARM32,ARMv5TE
 
 [QSUBcc]
+reg32,reg32,reg32          \x1A\x01\x20\x05                    ARM32,ARMv5TE
 
 [SMLABBcc]
+reg32,reg32,reg32,reg32     \x15\x01\x40\x8                     ARM32,ARMv5TE
 
 [SMLABTcc]
+reg32,reg32,reg32,reg32     \x15\x01\x00\xC                     ARM32,ARMv5TE
 
 [SMLATBcc]
+reg32,reg32,reg32,reg32     \x15\x01\x00\xA                     ARM32,ARMv5TE
 
 [SMLATTcc]
+reg32,reg32,reg32,reg32     \x15\x01\x00\xE                     ARM32,ARMv5TE
 
 [SMLALBBcc]
+reg32,reg32,reg32,reg32     \x16\x01\x40\x8                     ARM32,ARMv5TE
 
 [SMLALBTcc]
+reg32,reg32,reg32,reg32     \x16\x01\x40\xC                     ARM32,ARMv5TE
 
 [SMLALTBcc]
+reg32,reg32,reg32,reg32     \x16\x01\x40\xA                     ARM32,ARMv5TE
 
 [SMLALTTcc]
+reg32,reg32,reg32,reg32     \x16\x01\x40\xE                     ARM32,ARMv5TE
 
 [SMLAWBcc]
 
 [SMLAWTcc]
 
+[VLDMcc]
+memam4,reglist		      \x44\xC\x10\xA		         ARM32,VFPv2
+reg32,reglist		      \x44\xC\x10\xA		         ARM32,VFPv2
+
+[VSTMcc]
+memam4,reglist		      \x44\xC\x00\xA		         ARM32,VFPv2
+reg32,reglist		      \x44\xC\x00\xA		         ARM32,VFPv2
+
+[VPOP]
+reglist		            \x44\xC\xBD\xA		         ARM32,VFPv2
+
+[VPUSH]
+reglist		            \x44\xD\x2D\xA		         ARM32,VFPv2
+
+[VLDRcc]
+vreg,memam2             \x45\xD\x10\xA             ARM32,VFPv2
+
+[VSTRcc]
+vreg,memam2             \x45\xD\x0\xA              ARM32,VFPv2
+
 [SMULBBcc]
+reg32,reg32,reg32           \x15\x01\x60\x8                     ARM32,ARMv5TE
 
 [SMULBTcc]
+reg32,reg32,reg32           \x15\x01\x60\xC                     ARM32,ARMv5TE
 
 [SMULTBcc]
+reg32,reg32,reg32           \x15\x01\x60\xA                     ARM32,ARMv5TE
 
 [SMULTTcc]
+reg32,reg32,reg32           \x15\x01\x60\xE                     ARM32,ARMv5TE
 
 [SMULWBcc]
+reg32,reg32,reg32           \x14\x1\x20\xA0                     ARM32,ARMv5TE
 
 [SMULWTcc]
+reg32,reg32,reg32           \x14\x1\x20\xE0                     ARM32,ARMv5TE
 
 [STRDcc]
+reg32,reg32,memam2        \x19\x0\x0\x0\xF0           ARM32,ARMv4
 
-;
-; vfp instructions
-;
-[FABSDcc]
-
-[FABSScc]
-
-[FADDDcc]
-
-[FADDScc]
-
-[FCMPDcc]
-
-[FCMPEDcc]
-
-[FCMPEScc]
-
-[FCMPEZDcc]
-
-[FCMPEZScc]
-
-[FCMPScc]
-
-[FCMPZDcc]
-
-[FCMPZScc]
-
-[FCPYDcc]
-
-[FCPYScc]
-
-[FCVTDScc]
-
-[FCVTSDcc]
-
-[FDIVDcc]
-
-[FDIVScc]
-
-[FLDDcc]
-
-[FLDMcc]
-
-[FLDScc]
+[LDRHTcc]
+reg32,memam2              \x19\x0\x20\x0\xB0           ARM32,ARMv4
 
-[FMACDcc]
+[STRHTcc]
+reg32,memam2              \x19\x0\x20\x0\xB0           ARM32,ARMv4
 
-[FMACScc]
+[LDRSBTcc]
+reg32,memam2              \x19\x0\x30\x0\xD0           ARM32,ARMv4
 
-[FMDHRcc]
+[STRSBTcc]
+reg32,memam2              \x19\x0\x30\x0\xD0           ARM32,ARMv4
 
-[FMDLRcc]
+[LDRSHTcc]
+reg32,memam2              \x19\x0\x30\x0\xF0           ARM32,ARMv4
 
-[FMRDHcc]
-
-[FMRDLcc]
-
-[FMRScc]
-
-[FMRXcc]
-
-[FMSCDcc]
-
-[FMSCScc]
-
-[FMSRcc]
-
-[FMSTATcc]
-
-[FMULDcc]
-
-[FMULScc]
-
-[FMXRcc]
-
-[FNEGDcc]
-
-[FNEGScc]
-
-[FNMACDcc]
-
-[FNMACScc]
-
-[FNMSCDcc]
-
-[FNMSCScc]
-
-[FNMULDcc]
-
-[FNMULScc]
-
-[FSITODcc]
-
-[FSITOScc]
-
-[FSQRTDcc]
-
-[FSQRTScc]
+[STRSHTcc]
+reg32,memam2              \x19\x0\x30\x0\xF0           ARM32,ARMv4
 
 [FSTDcc]
 
@@ -556,242 +480,644 @@ reg32,reg32,reg32,reg32  \x16\x00\x80\x90		 ARM7
 
 [FSTScc]
 
-[FSUBDcc]
-
-[FSUBScc]
-
-[FTOSIDcc]
-
-[FTOSIScc]
-
-[FTOUIDcc]
-
-[FTOUIScc]
-
-[FUITODcc]
-
-[FUITOScc]
-
-[FMDRRcc]
-
-[FMRRDcc]
-
 ; ARMv6
 
 [BFCcc]
+reg32,immshifter,immshifter       \x2D\x7\xC0\x0\x1F            ARM32,ARMv4
+reg32,immshifter,imm32            \x2D\x7\xC0\x0\x1F            ARM32,ARMv4
 
 [BFIcc]
+reg32,reg32,immshifter,immshifter \x2D\x7\xC0\x0\x10            ARM32,ARMv4
+reg32,reg32,immshifter,imm32      \x2D\x7\xC0\x0\x10            ARM32,ARMv4
 
 [CLREX]
+void                      \x2F\xF5\x7F\xF0\x1F            ARM32,ARMv6K
 
 [LDREXcc]
+reg32,memam6              \x18\x01\x90\x0F\x9F            ARM32,ARMv4
 [LDREXBcc]
+reg32,memam6              \x18\x01\xD0\x0F\x9F            ARM32,ARMv4
 [LDREXDcc]
+reg32,reg32,memam6        \x18\x01\xB0\x0F\x9F            ARM32,ARMv4
 [LDREXHcc]
+reg32,memam6              \x18\x01\xF0\x0F\x9F            ARM32,ARMv4
+
+[STREXcc]
+reg32,reg32,memam6        \x18\x01\x80\x0F\x90            ARM32,ARMv4
+[STREXBcc]
+reg32,reg32,memam6        \x18\x01\xC0\x0F\x90            ARM32,ARMv4
+[STREXDcc]
+reg32,reg32,reg32,memam6  \x18\x01\xA0\x0F\x90            ARM32,ARMv4
+[STREXHcc]
+reg32,reg32,memam6        \x18\x01\xE0\x0F\x90            ARM32,ARMv4
 
 [MLScc]
+reg32,reg32,reg32,reg32   \x15\x00\x60\x9                 ARM32,ARMv6T2
+
+[PKHBTcc]
+reg32,reg32,reg32           \x16\x6\x80\x1                     ARM32,ARMv6
+reg32,reg32,reg32,shifterop \x16\x6\x80\x1                     ARM32,ARMv6
 
-[PKHcc]
+[PKHTBcc]
+reg32,reg32,reg32           \x16\x6\x80\x5                     ARM32,ARMv6
+reg32,reg32,reg32,shifterop \x16\x6\x80\x5                     ARM32,ARMv6
 
 [PLI]
+memam2                     \x25\xF6\x50\xF0\x0                 ARM32,ARMv7
 
 [QADD16cc]
+reg32,reg32,reg32          \x16\x06\x20\xF1                    ARM32,ARMv6
 [QADD8cc]
+reg32,reg32,reg32          \x16\x06\x20\xF9                    ARM32,ARMv6
 [QASXcc]
+reg32,reg32,reg32          \x16\x06\x20\xF3                    ARM32,ARMv6
 [QSAXcc]
+reg32,reg32,reg32          \x16\x06\x20\xF5                    ARM32,ARMv6
 [QSUB16cc]
+reg32,reg32,reg32          \x16\x06\x20\xF7                    ARM32,ARMv6
 [QSUB8cc]
+reg32,reg32,reg32          \x16\x06\x20\xFF                    ARM32,ARMv6
 
 [RBITcc]
+reg32,reg32                \x32\x6\xBF\xF\x30                  ARM32,ARMv6T2
 
 [REVcc]
+reg32,reg32                \x32\x6\xBF\xF\x30                  ARM32,ARMv6
+
 [REV16cc]
+reg32,reg32                \x32\x6\xBF\xF\xB0                  ARM32,ARMv6
+
 [REVSHcc]
+reg32,reg32                \x32\x6\xFF\xF\xB0                  ARM32,ARMv6
 
 [SADD16cc]
+reg32,reg32,reg32          \x16\x06\x10\xF1                    ARM32,ARMv6
+
 [SADD8cc]
+reg32,reg32,reg32          \x16\x06\x10\xF9                    ARM32,ARMv6
+
 [SASXcc]
+reg32,reg32,reg32          \x16\x06\x10\xF3                    ARM32,ARMv6
 
 [SBFXcc]
+reg32,reg32,immshifter,immshifter \x2D\x7\xA0\x0\x50           ARM32,ARMv6T2
 
 [SELcc]
+reg32,reg32,reg32          \x16\x06\x80\xFB                    ARM32,ARMv6
 
 [SETEND]
+imm                        \x2B\xF1\x01\x0\x0                  ARM32,ARMv6
 
 [SEVcc]
+void                       \x2F\x3\x20\xF0\x4                  ARM32,ARMv6K
 
 [ASRcc]
+reg32,reg32,reg32          \x30\x1\xA0\x0\x50                  ARM32,ARMv4
+reg32,reg32,immshifter     \x30\x1\xA0\x0\x40                  ARM32,ARMv4
 
 [LSRcc]
+reg32,reg32,reg32          \x30\x1\xA0\x0\x30                  ARM32,ARMv4
+reg32,reg32,immshifter     \x30\x1\xA0\x0\x20                  ARM32,ARMv4
 
 [LSLcc]
+reg32,reg32,reg32          \x30\x1\xA0\x0\x10                  ARM32,ARMv4
+reg32,reg32,immshifter     \x30\x1\xA0\x0\x00                  ARM32,ARMv4
 
 [RORcc]
+reg32,reg32,reg32          \x30\x1\xA0\x0\x70                  ARM32,ARMv4
+reg32,reg32,immshifter     \x30\x1\xA0\x0\x60                  ARM32,ARMv4
+
+[RRXcc]
+reg32,reg32                \x30\x1\xA0\x0\x60                  ARM32,ARMv4
+
+[UMAALcc]
+reg32,reg32,reg32,reg32     \x16\x0\x40\x9                     ARM32,ARMv6
 
 [SHADD16cc]
+reg32,reg32,reg32          \x16\x06\x30\xF1                    ARM32,ARMv6
+
 [SHADD8cc]
+reg32,reg32,reg32          \x16\x06\x30\xF9                    ARM32,ARMv6
+
 [SHASXcc]
+reg32,reg32,reg32          \x16\x06\x30\xF3                    ARM32,ARMv6
+
 [SHSAXcc]
+reg32,reg32,reg32          \x16\x06\x30\xF5                    ARM32,ARMv6
+
 [SHSUB16cc]
+reg32,reg32,reg32          \x16\x06\x30\xF7                    ARM32,ARMv6
+
 [SHSUB8cc]
+reg32,reg32,reg32          \x16\x06\x30\xFF                    ARM32,ARMv6
 
 [SMLADcc]
+reg32,reg32,reg32,reg32    \x15\x7\x00\x1                      ARM32,ARMv6
+
 [SMLALDcc]
+reg32,reg32,reg32,reg32    \x16\x7\x40\x1                      ARM32,ARMv4
+
 [SMLSDcc]
+reg32,reg32,reg32,reg32    \x15\x7\x00\x5                      ARM32,ARMv6
+
 [SMLSLDcc]
+reg32,reg32,reg32,reg32    \x16\x7\x40\x5                      ARM32,ARMv6
+
 [SMMLAcc]
+reg32,reg32,reg32,reg32    \x15\x7\x50\x1                      ARM32,ARMv6
+
 [SMMLScc]
+reg32,reg32,reg32,reg32    \x15\x7\x50\xD                      ARM32,ARMv6
+
 [SMMULcc]
+reg32,reg32,reg32          \x15\x7\x50\x1                      ARM32,ARMv6
+
 [SMUADcc]
+reg32,reg32,reg32          \x15\x7\x00\x1                      ARM32,ARMv6
+
 [SMUSDcc]
+reg32,reg32,reg32          \x15\x7\x00\x5                      ARM32,ARMv6
 
 [SRScc]
 
 [SSATcc]
+reg32,immshifter,reg32            \x2A\x6\xA0\x0\x10                  ARM32,ARMv6
+reg32,immshifter,reg32,shifterop  \x2A\x6\xA0\x0\x10                  ARM32,ARMv6
+
 [SSAT16cc]
+reg32,immshifter,reg32            \x2A\x6\xA0\x0\x30                  ARM32,ARMv6
+
 [SSAXcc]
+reg32,reg32,reg32          \x16\x06\x10\xF5                    ARM32,ARMv6
 
 [SSUB16cc]
-[SSUB8cc]
+reg32,reg32,reg32          \x16\x06\x10\xF7                    ARM32,ARMv6
 
-[STREXcc]
-[STREXBcc]
-[STREXDcc]
-[STREXHcc]
+[SSUB8cc]
+reg32,reg32,reg32          \x16\x06\x10\xFF                    ARM32,ARMv6
 
 [SXTABcc]
+reg32,reg32,reg32           \x16\x06\xA0\x07                    ARM32,ARMv6
+reg32,reg32,reg32,shifterop \x16\x06\xA0\x07                    ARM32,ARMv6
+
 [SXTAB16cc]
+reg32,reg32,reg32           \x16\x06\x80\x07                    ARM32,ARMv6
+reg32,reg32,reg32,shifterop \x16\x06\x80\x07                    ARM32,ARMv6
+
 [SXTAHcc]
+reg32,reg32,reg32           \x16\x06\xB0\x07                    ARM32,ARMv6
+reg32,reg32,reg32,shifterop \x16\x06\xB0\x07                    ARM32,ARMv6
+
+[UBFXcc]
+reg32,reg32,immshifter,immshifter \x2D\x7\xE0\x0\x50           ARM32,ARMv4
+
+[UXTABcc]
+reg32,reg32,reg32           \x16\x6\xE0\x7                     ARM32,ARMv6
+reg32,reg32,reg32,shifterop \x16\x6\xE0\x7                     ARM32,ARMv6
+
+[UXTAB16cc]
+reg32,reg32,reg32           \x16\x6\xC0\x7                     ARM32,ARMv6
+reg32,reg32,reg32,shifterop \x16\x6\xC0\x7                     ARM32,ARMv6
+
+[UXTAHcc]
+reg32,reg32,reg32           \x16\x6\xF0\x7                     ARM32,ARMv6
+reg32,reg32,reg32,shifterop \x16\x6\xF0\x7                     ARM32,ARMv6
+
 [SXTBcc]
+reg32,reg32                 \x1B\x6\xAF\x7                     ARM32,ARMv6
+reg32,reg32,shifterop       \x1B\x6\xAF\x7                     ARM32,ARMv6
+
 [SXTB16cc]
+reg32,reg32                 \x1B\x6\x8F\x7                     ARM32,ARMv6
+reg32,reg32,shifterop       \x1B\x6\x8F\x7                     ARM32,ARMv6
+
+[SXTHcc]
+reg32,reg32                 \x1B\x6\xBF\x7                     ARM32,ARMv6
+reg32,reg32,shifterop       \x1B\x6\xBF\x7                     ARM32,ARMv6
 
 [UXTBcc]
-[UXTHcc]
+reg32,reg32                 \x1B\x6\xEF\x7                     ARM32,ARMv6
+reg32,reg32,shifterop       \x1B\x6\xEF\x7                     ARM32,ARMv6
 
-[SXTHcc]
+[UXTB16cc]
+reg32,reg32                 \x1B\x6\xCF\x7                     ARM32,ARMv6
+reg32,reg32,shifterop       \x1B\x6\xCF\x7                     ARM32,ARMv6
+
+[UXTHcc]
+reg32,reg32                 \x1B\x6\xFF\x7                     ARM32,ARMv6
+reg32,reg32,shifterop       \x1B\x6\xFF\x7                     ARM32,ARMv6
 
 [UADD16cc]
+reg32,reg32,reg32          \x16\x06\x50\xF1                    ARM32,ARMv6
+
 [UADD8cc]
-[UASXcc]
+reg32,reg32,reg32          \x16\x06\x50\xF9                    ARM32,ARMv6
 
-[UBFXcc]
+[UASXcc]
+reg32,reg32,reg32          \x16\x06\x50\xF3                    ARM32,ARMv6
 
 [UHADD16cc]
+reg32,reg32,reg32          \x16\x06\x70\xF1                    ARM32,ARMv6
+
 [UHADD8cc]
+reg32,reg32,reg32          \x16\x06\x70\xF9                    ARM32,ARMv6
+
 [UHASXcc]
+reg32,reg32,reg32          \x16\x06\x70\xF3                    ARM32,ARMv6
+
 [UHSAXcc]
+reg32,reg32,reg32          \x16\x06\x70\xF5                    ARM32,ARMv6
+
 [UHSUB16cc]
-[UHSUB8cc]
+reg32,reg32,reg32          \x16\x06\x70\xF7                    ARM32,ARMv6
 
-[UMAALcc]
+[UHSUB8cc]
+reg32,reg32,reg32          \x16\x06\x70\xFF                    ARM32,ARMv6
 
 [UQADD16cc]
+reg32,reg32,reg32          \x16\x06\x60\xF1                    ARM32,ARMv6
+
 [UQADD8]
+reg32,reg32,reg32          \x16\x06\x60\xF9                    ARM32,ARMv6
+
 [UQASXcc]
+reg32,reg32,reg32          \x16\x06\x60\xF3                    ARM32,ARMv6
+
 [UQSAXcc]
+reg32,reg32,reg32          \x16\x06\x60\xF5                    ARM32,ARMv6
 
 [UQSUB16cc]
+reg32,reg32,reg32          \x16\x06\x60\xF7                    ARM32,ARMv6
+
 [UQSUB8cc]
-[UQSAD8cc]
-[UQSADA8cc]
+reg32,reg32,reg32          \x16\x06\x60\xFF                    ARM32,ARMv6
+
+[USAD8cc]
+reg32,reg32,reg32          \x15\x07\x80\x01                    ARM32,ARMv6
+
+[USADA8cc]
+reg32,reg32,reg32,reg32    \x15\x07\x80\x01                    ARM32,ARMv6
 
 [USATcc]
+reg32,immshifter,reg32            \x2A\x6\xE0\x0\x10                  ARM32,ARMv6
+reg32,immshifter,reg32,shifterop  \x2A\x6\xE0\x0\x10                  ARM32,ARMv6
+
 [USAT16cc]
+reg32,immshifter,reg32            \x2A\x6\xE0\x0\x30                  ARM32,ARMv6
+
 [USAXcc]
+reg32,reg32,reg32          \x16\x06\x50\xF6                    ARM32,ARMv6
 
 [USUB16cc]
-[USUB8cc]
+reg32,reg32,reg32          \x16\x06\x50\xF7                    ARM32,ARMv6
 
-[UXTABcc]
-[UXTAB16cc]
-[UXTAHcc]
-[UXTB16cc]
+[USUB8cc]
+reg32,reg32,reg32          \x16\x06\x50\xFF                    ARM32,ARMv6
 
 [WFEcc]
+void                          \x2F\x3\x20\xF0\x2               ARM32,ARMv6K
+
 [WFIcc]
+void                          \x2F\x3\x20\xF0\x3               ARM32,ARMv6K
+
 [YIELDcc]
+void                          \x2F\x3\x20\xF0\x1               ARM32,ARMv6K
+
+;
+; vfp instructions
+;
+[FABSDcc]
+
+[FABSScc]
+
+[FADDDcc]
+
+[FADDScc]
+
+[FCMPDcc]
+
+[FCMPEDcc]
+
+[FCMPEScc]
+
+[FCMPEZDcc]
+
+[FCMPEZScc]
+
+[FCMPScc]
+
+[FCMPZDcc]
+
+[FCMPZScc]
+
+[FCPYDcc]
+
+[FCPYScc]
+
+[FCVTDScc]
+
+[FCVTSDcc]
+
+[FDIVDcc]
+
+[FDIVScc]
+
+[FLDDcc]
+
+[FLDMcc]
+
+[FLDScc]
+
+[FMACDcc]
+
+[FMACScc]
+
+[FMDHRcc]
+
+[FMDLRcc]
+
+[FMRDHcc]
+
+[FMRDLcc]
+
+[FMRScc]
+
+[FMRXcc]
+
+[FMSCDcc]
+
+[FMSCScc]
+
+[FMSRcc]
+
+[FMSTATcc]
+
+[FMULDcc]
+
+[FMULScc]
+
+[FMXRcc]
+
+[FNEGDcc]
+
+[FNEGScc]
+
+[FNMACDcc]
+
+[FNMACScc]
+
+[FNMSCDcc]
+
+[FNMSCScc]
+
+[FNMULDcc]
+
+[FNMULScc]
+
+[FSITODcc]
+
+[FSITOScc]
+
+[FSQRTDcc]
+
+[FSQRTScc]
+
+[FSUBDcc]
+
+[FSUBScc]
+
+[FTOSIDcc]
+
+[FTOSIScc]
+
+[FTOUIDcc]
+
+[FTOUIScc]
+
+[FUITODcc]
+
+[FUITOScc]
+
+[FMDRRcc]
+
+[FMRRDcc]
 
 ; Thumb-2
 
 [POP]
+reglist		                  \x26\x80		               ARM32,ARMv4
 
 [PUSH]
+reglist		                  \x26\x80		               ARM32,ARMv4
 
 [SDIVcc]
 
 [UDIVcc]
 
 [MOVTcc]
+reg32,imm                     \x2C\x3\x40                ARM32,ARMv6T2
+reg32,immshifter              \x2C\x3\x40                ARM32,ARMv6T2
 
 [IT]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITE]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITT]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITEE]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITTE]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITET]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITTT]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITEEE]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITTEE]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITETE]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITTTE]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITEET]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITTET]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITETT]
+condition                     \xFE                       ARM32,ARMv4
 
 [ITTTT]
+condition                     \xFE                       ARM32,ARMv4
 
 [TBB]
 [TBH]
 
 [MOVW]
+reg32,imm               \x2C\x3\x0                 ARM32,ARMv6T2
+reg32,immshifter        \x2C\x3\x0                 ARM32,ARMv6T2
 
 [CBZ]
 [CBNZ]
 
-; FPv4-s16 - ARMv7M floating point
-[VABS]
-[VADD]
-[VCMP]
-[VCMPE]
-[VCVT]
-[VDIV]
-[VLDM]
-[VLDR]
-[VMOV]
-[VMRS]
-[VMSR]
-[VMUL]
-[VMLA]
-[VMLS]
-[VNMLA]
-[VNMLS]
+; VFP
+[VABScc]
+vreg,vreg               \x42\xE\xB0\xA\xC0         ARM32,VFPv2
+
+[VADDcc]
+vreg,vreg,vreg          \x42\xE\x30\xA\x0          ARM32,VFPv2
+
+[VCMPcc]
+vreg,vreg               \x42\xE\xB4\xA\x40         ARM32,VFPv2
+vreg,immshifter         \x42\xE\xB5\xA\x40         ARM32,VFPv2
+
+[VCMPEcc]
+vreg,vreg               \x42\xE\xB4\xA\xC0         ARM32,VFPv2
+vreg,immshifter         \x42\xE\xB5\xA\xC0         ARM32,VFPv2
+
+[VCVTcc]
+vreg,vreg               \x43\xE\xB8\xA\xC0         ARM32,VFPv2
+vreg,vreg,immshifter    \x43\xE\xBA\xA\x40         ARM32,VFPv3
+
+[VCVTRcc]
+vreg,vreg               \x43\xE\xB8\xA\x40         ARM32,VFPv2
+
+[VDIVcc]
+vreg,vreg,vreg          \x42\xE\x80\xA\x0          ARM32,VFPv2
+
+[VMRScc]
+reg32,regf              \x41\xE\xF0\xA\x10         ARM32,VFPv2
+regf,regf               \x41\xE\xF0\xA\x10         ARM32,VFPv2
+
+[VMSRcc]
+regf,reg32              \x41\xE\xE0\xA\x10         ARM32,VFPv2
+
+[VMLAcc]
+vreg,vreg,vreg          \x42\xE\x0\xA\x00          ARM32,VFPv2
+
+[VMLScc]
+vreg,vreg,vreg          \x42\xE\x0\xA\x40          ARM32,VFPv2
+
+[VMULcc]
+vreg,vreg,vreg          \x42\xE\x20\xA\x0          ARM32,VFPv2
+
+[VNMLAcc]
+vreg,vreg,vreg          \x42\xE\x10\xA\x40         ARM32,VFPv2
+
+[VNMLScc]
+vreg,vreg,vreg          \x42\xE\x10\xA\x00         ARM32,VFPv2
+
+[VNMULcc]
+vreg,vreg,vreg          \x42\xE\x20\xA\x40         ARM32,VFPv2
+
 [VFMA]
 [VFMS]
 [VFNMA]
 [VFNMS]
-[VNEG]
-[VNMUL]
-[VPOP]
-[VPUSH]
+
+[VNEGcc]
+vreg,vreg               \x42\xE\xB1\xA\x40         ARM32,VFPv2
+
 [VSQRT]
-[VSTM]
-[VSTR]
+vreg,vreg               \x42\xE\xB1\xA\xC0         ARM32,VFPv2
+
 [VSUB]
+vreg,vreg,vreg          \x42\xE\x30\xA\x40         ARM32,VFPv2
+
+[DMB]
+immshifter        \x2E\xF5\x7F\xF0\x50             ARM32,ARMv7
+
+[ISB]
+immshifter        \x2E\xF5\x7F\xF0\x60             ARM32,ARMv7
+
+[DSB]
+immshifter        \x2E\xF5\x7F\xF0\x40             ARM32,ARMv7
+
+[SMC]
+immshifter        \x2E\x01\x60\x00\x70             ARM32,ARMv7
 
 ; Thumb armv6-m (gcc)
 [NEG]
+
 [SVC]
+imm32              \x2\x0F                         ARM32,ARMv4
+immshifter         \x2\x0F                         ARM32,ARMv4
+
+[BXJcc]
+reg32              \x3\x01\x2F\xFF\x20             ARM32,ARMv5TEJ
+
+; Undefined mnemonic
+[UDF]
+void                 void                          none
+
+; FPA
+
+
+[TANcc]
+
+[SQTcc]
+
+[SUFcc]
+
+[RSFcc]
+
+[RNDcc]
+
+[POLcc]
+
+[RDFcc]
+
+[RFScc]
+
+[RFCcc]
+
+[RMFcc]
+
+[RPWcc]
+
+[MNFcc]
+
+[MUFcc]
+
+[ABScc]
+
+[ACScc]
+
+[ASNcc]
+
+[ATNcc]
+
+[CNFcc]
+
+[COScc]
+
+[DVFcc]
+
+[EXPcc]
+
+[FDVcc]
+
+[FLTcc]
+
+[FIXcc]
+
+[FMLcc]
+
+[FRDcc]
+
+[LGNcc]
 
+[LOGcc]

compiler/arm/armnop.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armins.dat }
-105;
+339;

compiler/arm/armop.inc

@@ -1,10 +1,6 @@
 { don't edit, this file is generated from armins.dat }
 (
 A_NONE,
-A_ABS,
-A_ACS,
-A_ASN,
-A_ATN,
 A_ADC,
 A_ADD,
 A_ADF,
@@ -17,24 +13,18 @@ A_BLX,
 A_BKPT,
 A_BX,
 A_CDP,
-A_CMF,
-A_CMFE,
 A_CMN,
 A_CMP,
+A_CMF,
+A_CMFE,
+A_STF,
+A_LDF,
+A_LFM,
 A_CLZ,
-A_CNF,
-A_COS,
 A_CPS,
 A_CPSID,
 A_CPSIE,
-A_DVF,
 A_EOR,
-A_EXP,
-A_FDV,
-A_FLT,
-A_FIX,
-A_FML,
-A_FRD,
 A_LDC,
 A_LDM,
 A_LDRBT,
@@ -44,41 +34,31 @@ A_LDRH,
 A_LDRSB,
 A_LDRSH,
 A_LDRT,
-A_LDF,
-A_LFM,
-A_LGN,
-A_LOG,
 A_MCR,
+A_MCR2,
+A_MRC,
+A_MRC2,
+A_MCRR,
+A_MCRR2,
+A_MRRC,
+A_MRRC2,
 A_MLA,
 A_MOV,
-A_MRC,
 A_MRS,
 A_MSR,
-A_MNF,
-A_MUF,
 A_MUL,
 A_MVF,
 A_MVN,
+A_VMOV,
 A_NOP,
 A_ORR,
-A_RDF,
-A_RFS,
-A_RFC,
-A_RMF,
-A_RPW,
 A_RSB,
 A_RSC,
-A_RSF,
-A_RND,
-A_POL,
 A_SBC,
 A_SFM,
 A_SIN,
 A_SMLAL,
 A_SMULL,
-A_SQT,
-A_SUF,
-A_STF,
 A_STM,
 A_STR,
 A_STRB,
@@ -89,16 +69,14 @@ A_SUB,
 A_SWI,
 A_SWP,
 A_SWPB,
-A_TAN,
 A_TEQ,
 A_TST,
 A_UMLAL,
 A_UMULL,
 A_WFS,
 A_LDRD,
-A_MCRR,
-A_MRRC,
 A_PLD,
+A_PLDW,
 A_QADD,
 A_QDADD,
 A_QDSUB,
@@ -113,6 +91,12 @@ A_SMLALTB,
 A_SMLALTT,
 A_SMLAWB,
 A_SMLAWT,
+A_VLDM,
+A_VSTM,
+A_VPOP,
+A_VPUSH,
+A_VLDR,
+A_VSTR,
 A_SMULBB,
 A_SMULBT,
 A_SMULTB,
@@ -120,67 +104,15 @@ A_SMULTT,
 A_SMULWB,
 A_SMULWT,
 A_STRD,
-A_FABSD,
-A_FABSS,
-A_FADDD,
-A_FADDS,
-A_FCMPD,
-A_FCMPED,
-A_FCMPES,
-A_FCMPEZD,
-A_FCMPEZS,
-A_FCMPS,
-A_FCMPZD,
-A_FCMPZS,
-A_FCPYD,
-A_FCPYS,
-A_FCVTDS,
-A_FCVTSD,
-A_FDIVD,
-A_FDIVS,
-A_FLDD,
-A_FLDM,
-A_FLDS,
-A_FMACD,
-A_FMACS,
-A_FMDHR,
-A_FMDLR,
-A_FMRDH,
-A_FMRDL,
-A_FMRS,
-A_FMRX,
-A_FMSCD,
-A_FMSCS,
-A_FMSR,
-A_FMSTAT,
-A_FMULD,
-A_FMULS,
-A_FMXR,
-A_FNEGD,
-A_FNEGS,
-A_FNMACD,
-A_FNMACS,
-A_FNMSCD,
-A_FNMSCS,
-A_FNMULD,
-A_FNMULS,
-A_FSITOD,
-A_FSITOS,
-A_FSQRTD,
-A_FSQRTS,
+A_LDRHT,
+A_STRHT,
+A_LDRSBT,
+A_STRSBT,
+A_LDRSHT,
+A_STRSHT,
 A_FSTD,
 A_FSTM,
 A_FSTS,
-A_FSUBD,
-A_FSUBS,
-A_FTOSID,
-A_FTOSIS,
-A_FTOUID,
-A_FTOUIS,
-A_FUITOD,
-A_FUITOS,
-A_FMDRR,
-A_FMRRD,
 A_BFC,
 A_BFI,
 A_CLREX,
@@ -188,8 +120,13 @@ A_LDREX,
 A_LDREXB,
 A_LDREXD,
 A_LDREXH,
+A_STREX,
+A_STREXB,
+A_STREXD,
+A_STREXH,
 A_MLS,
-A_PKH,
+A_PKHBT,
+A_PKHTB,
 A_PLI,
 A_QADD16,
 A_QADD8,
@@ -212,6 +149,8 @@ A_ASR,
 A_LSR,
 A_LSL,
 A_ROR,
+A_RRX,
+A_UMAAL,
 A_SHADD16,
 A_SHADD8,
 A_SHASX,
@@ -233,49 +172,102 @@ A_SSAT16,
 A_SSAX,
 A_SSUB16,
 A_SSUB8,
-A_STREX,
-A_STREXB,
-A_STREXD,
-A_STREXH,
 A_SXTAB,
 A_SXTAB16,
 A_SXTAH,
+A_UBFX,
+A_UXTAB,
+A_UXTAB16,
+A_UXTAH,
 A_SXTB,
 A_SXTB16,
+A_SXTH,
 A_UXTB,
+A_UXTB16,
 A_UXTH,
-A_SXTH,
 A_UADD16,
 A_UADD8,
 A_UASX,
-A_UBFX,
 A_UHADD16,
 A_UHADD8,
 A_UHASX,
 A_UHSAX,
 A_UHSUB16,
 A_UHSUB8,
-A_UMAAL,
 A_UQADD16,
 A_UQADD8,
 A_UQASX,
 A_UQSAX,
 A_UQSUB16,
 A_UQSUB8,
-A_UQSAD8,
-A_UQSADA8,
+A_USAD8,
+A_USADA8,
 A_USAT,
 A_USAT16,
 A_USAX,
 A_USUB16,
 A_USUB8,
-A_UXTAB,
-A_UXTAB16,
-A_UXTAH,
-A_UXTB16,
 A_WFE,
 A_WFI,
 A_YIELD,
+A_FABSD,
+A_FABSS,
+A_FADDD,
+A_FADDS,
+A_FCMPD,
+A_FCMPED,
+A_FCMPES,
+A_FCMPEZD,
+A_FCMPEZS,
+A_FCMPS,
+A_FCMPZD,
+A_FCMPZS,
+A_FCPYD,
+A_FCPYS,
+A_FCVTDS,
+A_FCVTSD,
+A_FDIVD,
+A_FDIVS,
+A_FLDD,
+A_FLDM,
+A_FLDS,
+A_FMACD,
+A_FMACS,
+A_FMDHR,
+A_FMDLR,
+A_FMRDH,
+A_FMRDL,
+A_FMRS,
+A_FMRX,
+A_FMSCD,
+A_FMSCS,
+A_FMSR,
+A_FMSTAT,
+A_FMULD,
+A_FMULS,
+A_FMXR,
+A_FNEGD,
+A_FNEGS,
+A_FNMACD,
+A_FNMACS,
+A_FNMSCD,
+A_FNMSCS,
+A_FNMULD,
+A_FNMULS,
+A_FSITOD,
+A_FSITOS,
+A_FSQRTD,
+A_FSQRTS,
+A_FSUBD,
+A_FSUBS,
+A_FTOSID,
+A_FTOSIS,
+A_FTOUID,
+A_FTOUIS,
+A_FUITOD,
+A_FUITOS,
+A_FMDRR,
+A_FMRRD,
 A_POP,
 A_PUSH,
 A_SDIV,
@@ -306,29 +298,57 @@ A_VADD,
 A_VCMP,
 A_VCMPE,
 A_VCVT,
+A_VCVTR,
 A_VDIV,
-A_VLDM,
-A_VLDR,
-A_VMOV,
 A_VMRS,
 A_VMSR,
-A_VMUL,
 A_VMLA,
 A_VMLS,
+A_VMUL,
 A_VNMLA,
 A_VNMLS,
+A_VNMUL,
 A_VFMA,
 A_VFMS,
 A_VFNMA,
 A_VFNMS,
 A_VNEG,
-A_VNMUL,
-A_VPOP,
-A_VPUSH,
 A_VSQRT,
-A_VSTM,
-A_VSTR,
 A_VSUB,
+A_DMB,
+A_ISB,
+A_DSB,
+A_SMC,
 A_NEG,
-A_SVC
+A_SVC,
+A_BXJ,
+A_UDF,
+A_TAN,
+A_SQT,
+A_SUF,
+A_RSF,
+A_RND,
+A_POL,
+A_RDF,
+A_RFS,
+A_RFC,
+A_RMF,
+A_RPW,
+A_MNF,
+A_MUF,
+A_ABS,
+A_ACS,
+A_ASN,
+A_ATN,
+A_CNF,
+A_COS,
+A_DVF,
+A_EXP,
+A_FDV,
+A_FLT,
+A_FIX,
+A_FML,
+A_FRD,
+A_LGN,
+A_LOG
 );

compiler/arm/armreg.dat

@@ -87,7 +87,7 @@ S28,$04,$06,$0E,s28,0,0
 S29,$04,$06,$2E,s29,0,0
 D14,$04,$07,$0E,d14,0,0
 S30,$04,$06,$0F,s30,0,0
-S31,$04,$06,$2F,s21,0,0
+S31,$04,$06,$2F,s31,0,0
 D15,$04,$07,$0F,d15,0,0
 D16,$04,$07,$10,d16,0,0
 D17,$04,$07,$11,d17,0,0
@@ -145,4 +145,8 @@ BASEPRI,$05,$00,$1F,basepri,0,0
 BASEPRI_MAX,$05,$00,$20,basepri_max,0,0
 FAULTMASK,$05,$00,$21,faultmask,0,0
 CONTROL,$05,$00,$22,control,0,0
-
+; VFP registers
+FPSID,$05,$00,$23,fpsid,0,0
+MVFR1,$05,$00,$24,mvfr1,0,0
+MVFR0,$05,$00,$25,mvfr0,0,0
+FPEXC,$05,$00,$26,fpexc,0,0

compiler/arm/armtab.inc

@@ -3,736 +3,2374 @@
   (
     opcode  : A_NONE;
     ops     : 0;
-    optypes : (ot_none,ot_none,ot_none,ot_none);
+    optypes : (ot_none,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #0;
     flags   : if_none
   ),
   (
     opcode  : A_ADC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #4#0#160;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_ADC;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #5#0#160;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_ADC;
-    ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
     code    : #6#0#160;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_ADC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
     code    : #7#2#160;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_ADD;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #4#0#128;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_ADD;
-    ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #5#0#128;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_ADD;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
     code    : #6#0#128;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_ADD;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
     code    : #7#2#128;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_AND;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #4#0#0;
-    flags   : if_arm7
+    opcode  : A_ADR;
+    ops     : 2;
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #51#2#15;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ADR;
+    ops     : 2;
+    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none,ot_none,ot_none);
+    code    : #51#2#15;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ADR;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #51#2#15;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_AND;
-    ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #5#0#0;
-    flags   : if_arm7
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #4#0#0;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_AND;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
     code    : #6#0#0;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_AND;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
     code    : #7#2#0;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_B;
     ops     : 1;
-    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none);
+    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #1#10;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_B;
     ops     : 1;
-    optypes : (ot_immediate24,ot_none,ot_none,ot_none);
+    optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #1#10;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_BIC;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #4#1#192;
-    flags   : if_arm7
+    opcode  : A_B;
+    ops     : 1;
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #1#10;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_BIC;
-    ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #5#1#192;
-    flags   : if_arm7
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #6#1#192;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_BIC;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
     code    : #6#1#192;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_BIC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
     code    : #7#3#192;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_BL;
+    ops     : 1;
+    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #1#11;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_BL;
     ops     : 1;
-    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none);
+    optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #1#11;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_BL;
     ops     : 1;
-    optypes : (ot_immediate24,ot_none,ot_none,ot_none);
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #1#11;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_BLX;
+    ops     : 1;
+    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #40#250;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_BLX;
+    ops     : 1;
+    optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #40#250;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_BLX;
     ops     : 1;
-    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none);
-    code    : #15#15;
-    flags   : if_arm7
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #40#250;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_BLX;
     ops     : 1;
-    optypes : (ot_immediate24,ot_none,ot_none,ot_none);
-    code    : #15#15;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #3#1#47#255#48;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_BKPT;
+    ops     : 1;
+    optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #49#1#32#112;
+    flags   : if_arm32 or if_armv5t
+  ),
+  (
+    opcode  : A_BKPT;
+    ops     : 1;
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #49#1#32#112;
+    flags   : if_arm32 or if_armv5t
   ),
   (
     opcode  : A_BX;
     ops     : 1;
-    optypes : (ot_reg32,ot_none,ot_none,ot_none);
+    optypes : (ot_reg32,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #3#1#47#255#16;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_CDP;
     ops     : 2;
-    optypes : (ot_reg8,ot_reg8,ot_none,ot_none);
+    optypes : (ot_reg8,ot_reg8,ot_none,ot_none,ot_none,ot_none);
     code    : #192#1#16#65;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_CMN;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
     code    : #12#1#96;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_CMN;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #13#1#96;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_CMN;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
     code    : #14#1#96;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_CMN;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate,ot_none,ot_none);
-    code    : #15#3#96;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #15#1#96;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_CMP;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
     code    : #12#1#64;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_CMP;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #13#1#64;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_CMP;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
     code    : #14#1#64;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_CMP;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate,ot_none,ot_none);
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
     code    : #15#3#64;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LFM;
+    ops     : 3;
+    optypes : (ot_reg32,ot_immediate or ot_bits8,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #240#2#1;
+    flags   : if_fpa
   ),
   (
     opcode  : A_CLZ;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
-    code    : #39#1#1;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #50#1#111#15#16;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_EOR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #4#0#32;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_EOR;
-    ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #5#0#32;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_EOR;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
     code    : #6#0#32;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_EOR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
     code    : #7#2#32;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_LDC;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
     code    : #209#192#1#17#65;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_LDM;
     ops     : 2;
-    optypes : (ot_memoryam4,ot_reglist,ot_none,ot_none);
+    optypes : (ot_memoryam4,ot_reglist,ot_none,ot_none,ot_none,ot_none);
     code    : #38#129;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_LDRB;
+    opcode  : A_LDM;
     ops     : 2;
-    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
-    code    : #23#7#16;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reglist,ot_none,ot_none,ot_none,ot_none);
+    code    : #38#129;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_LDR;
+    opcode  : A_LDRBT;
     ops     : 2;
-    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
-    code    : #23#5#16;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #23#4#112;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_LDRH;
+    opcode  : A_LDRBT;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
-    code    : #34#80#176;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #23#4#112;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_LDRH;
+    opcode  : A_LDRB;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
-    code    : #35#80#176;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #23#4#80;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_LDRH;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
-    code    : #36#80#176;
-    flags   : if_arm7
+    opcode  : A_LDR;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #23#4#16;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_LDRH;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #37#16#176;
-    flags   : if_arm7
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #34#16#176;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_LDRSB;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
-    code    : #34#80#208;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #34#16#208;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_LDRSB;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
     code    : #35#80#208;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_LDRSB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none,ot_none);
     code    : #36#80#208;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_LDRSB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #37#16#208;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_LDRSH;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
-    code    : #34#80#240;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #34#16#240;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_LDRSH;
+    opcode  : A_LDRT;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
-    code    : #35#80#240;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #23#4#48;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_LDRSH;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
-    code    : #36#80#240;
-    flags   : if_arm7
+    opcode  : A_MCR;
+    ops     : 5;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_regf,ot_regf,ot_none);
+    code    : #28#14#0#1;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_LDRSH;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #37#16#240;
-    flags   : if_arm7
+    opcode  : A_MCR;
+    ops     : 6;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_regf,ot_regf,ot_immediateshifter);
+    code    : #28#14#0#1;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_LFM;
-    ops     : 3;
-    optypes : (ot_reg32,ot_immediate or ot_bits8,ot_fpureg,ot_none);
-    code    : #240#2#1;
-    flags   : if_fpa
+    opcode  : A_MCR2;
+    ops     : 5;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_regf,ot_regf,ot_none);
+    code    : #28#254#0#1;
+    flags   : if_arm32 or if_armv5t
+  ),
+  (
+    opcode  : A_MCR2;
+    ops     : 6;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_regf,ot_regf,ot_immediateshifter);
+    code    : #28#254#0#1;
+    flags   : if_arm32 or if_armv5t
+  ),
+  (
+    opcode  : A_MRC;
+    ops     : 5;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_regf,ot_regf,ot_none);
+    code    : #28#14#16#1;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_MRC;
+    ops     : 6;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_regf,ot_regf,ot_immediateshifter);
+    code    : #28#14#16#1;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_MRC2;
+    ops     : 5;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_regf,ot_regf,ot_none);
+    code    : #28#254#16#1;
+    flags   : if_arm32 or if_armv5t
+  ),
+  (
+    opcode  : A_MRC2;
+    ops     : 6;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_regf,ot_regf,ot_immediateshifter);
+    code    : #28#254#16#1;
+    flags   : if_arm32 or if_armv5t
+  ),
+  (
+    opcode  : A_MCRR;
+    ops     : 5;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_reg32,ot_regf,ot_none);
+    code    : #29#12#64#0;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_MCRR2;
+    ops     : 5;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_reg32,ot_regf,ot_none);
+    code    : #29#252#64#0;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_MRRC;
+    ops     : 5;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_reg32,ot_regf,ot_none);
+    code    : #29#12#80#0;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_MRRC2;
+    ops     : 5;
+    optypes : (ot_regf,ot_immediateshifter,ot_reg32,ot_reg32,ot_regf,ot_none);
+    code    : #29#252#80#0;
+    flags   : if_arm32 or if_armv6
   ),
   (
     opcode  : A_MLA;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #21#0#32#144;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#0#32#9;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_MOV;
+    ops     : 2;
+    optypes : (ot_reg32,ot_shifterop,ot_none,ot_none,ot_none,ot_none);
+    code    : #8#1#160;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_MOV;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
+    code    : #10#1#160;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_MOV;
+    ops     : 2;
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #11#1#160;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_MRS;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
     code    : #16#1#15;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_MSR;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
     code    : #17#1#41#240;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_MSR;
     ops     : 2;
-    optypes : (ot_regf,ot_reg32,ot_none,ot_none);
+    optypes : (ot_regf,ot_reg32,ot_none,ot_none,ot_none,ot_none);
     code    : #18#1#40#240;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_MSR;
     ops     : 2;
-    optypes : (ot_regf,ot_immediate,ot_none,ot_none);
+    optypes : (ot_regf,ot_immediate,ot_none,ot_none,ot_none,ot_none);
     code    : #19#3#40#240;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_MUL;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #20#0#0#144;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_MVF;
     ops     : 2;
-    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none);
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
     code    : #242;
     flags   : if_fpa
   ),
   (
     opcode  : A_MVF;
     ops     : 2;
-    optypes : (ot_fpureg,ot_immediatefpu,ot_none,ot_none);
+    optypes : (ot_fpureg,ot_immediatefpu,ot_none,ot_none,ot_none,ot_none);
     code    : #242;
     flags   : if_fpa
   ),
+  (
+    opcode  : A_MVN;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #8#1#224;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_MVN;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
+    code    : #10#1#224;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_MVN;
+    ops     : 2;
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #11#1#224;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_VMOV;
+    ops     : 2;
+    optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
+    code    : #64#14#176#10#64;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMOV;
+    ops     : 2;
+    optypes : (ot_reg32,ot_vreg,ot_none,ot_none,ot_none,ot_none);
+    code    : #64#14#16#10#16;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMOV;
+    ops     : 2;
+    optypes : (ot_vreg,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #64#14#0#10#16;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMOV;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_vreg,ot_vreg,ot_none,ot_none);
+    code    : #64#12#80#10#16;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMOV;
+    ops     : 4;
+    optypes : (ot_vreg,ot_vreg,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #64#12#64#10#16;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMOV;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_vreg,ot_none,ot_none,ot_none);
+    code    : #64#12#80#11#16;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMOV;
+    ops     : 3;
+    optypes : (ot_vreg,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #64#12#64#11#16;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_NOP;
+    ops     : 0;
+    optypes : (ot_none,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #47#3#32#240#0;
+    flags   : if_arm32 or if_armv6k
+  ),
   (
     opcode  : A_ORR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #4#1#128;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_ORR;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #5#1#128;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_ORR;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
     code    : #6#1#128;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_ORR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
     code    : #7#3#128;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_RSB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #4#0#96;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_RSB;
-    ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #5#0#96;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #6#0#96;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_RSB;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
     code    : #6#0#96;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_RSB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
-    code    : #7#2#96;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #7#0#96;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_RSC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #4#0#224;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_RSC;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #5#0#224;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_RSC;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
     code    : #6#0#224;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_RSC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
     code    : #7#2#224;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SBC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #4#0#192;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SBC;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #5#0#192;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_SBC;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate,ot_none,ot_none);
+    code    : #6#0#192;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SBC;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
     code    : #6#0#192;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SBC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
     code    : #7#2#192;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SFM;
     ops     : 3;
-    optypes : (ot_reg32,ot_immediate or ot_bits8,ot_fpureg,ot_none);
+    optypes : (ot_reg32,ot_immediate or ot_bits8,ot_fpureg,ot_none,ot_none,ot_none);
     code    : #240#2#0;
     flags   : if_fpa
   ),
   (
     opcode  : A_SMLAL;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #22#0#224#144;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#0#224#9;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SMULL;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #22#0#192#144;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#0#192#9;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_STM;
+    ops     : 2;
+    optypes : (ot_memoryam4,ot_reglist,ot_none,ot_none,ot_none,ot_none);
+    code    : #38#128;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_STM;
     ops     : 2;
-    optypes : (ot_memoryam4,ot_reglist,ot_none,ot_none);
+    optypes : (ot_reg32,ot_reglist,ot_none,ot_none,ot_none,ot_none);
     code    : #38#128;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_STR;
     ops     : 2;
-    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
     code    : #23#4#0;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_STRB;
     ops     : 2;
-    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
-    code    : #23#6#0;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #23#4#64;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_STRH;
+    opcode  : A_STRBT;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
-    code    : #34#64#176;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #23#4#96;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_STRH;
+    opcode  : A_STRBT;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
-    code    : #35#64#176;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #23#4#96;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_STRH;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
-    code    : #36#64#176;
-    flags   : if_arm7
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #34#0#176;
+    flags   : if_arm32 or if_armv4
   ),
   (
-    opcode  : A_STRH;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #37#0#176;
-    flags   : if_arm7
+    opcode  : A_STRT;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #23#4#32;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SUB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
     code    : #4#0#64;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SUB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
     code    : #4#0#64;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SUB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #4#0#64;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_SUB;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #6#0#64;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_SWI;
+    ops     : 1;
+    optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #2#15;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SWI;
     ops     : 1;
-    optypes : (ot_immediate,ot_none,ot_none,ot_none);
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #2#15;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SWP;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #39#1#144;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none);
+    code    : #39#16#9;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_SWPB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #39#1#144;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none);
+    code    : #39#20#9;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_TEQ;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
     code    : #12#1#32;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_TEQ;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #13#1#32;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_TEQ;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
     code    : #14#1#32;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_TEQ;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate,ot_none,ot_none);
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
     code    : #15#3#32;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_TST;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
     code    : #12#1#0;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_TST;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
     code    : #13#1#0;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_TST;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
     code    : #14#1#0;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_TST;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate,ot_none,ot_none);
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
     code    : #15#3#0;
-    flags   : if_arm7
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_UMLAL;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #22#0#160#144;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#0#160#9;
+    flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_UMULL;
     ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32);
-    code    : #22#0#128#144;
-    flags   : if_arm7
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#0#128#9;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LDRD;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none);
+    code    : #25#0#0#0#208;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_PLD;
+    ops     : 1;
+    optypes : (ot_memoryam2,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #37#247#80#240#0;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_PLDW;
+    ops     : 1;
+    optypes : (ot_memoryam2,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #37#247#16#240#0;
+    flags   : if_arm32 or if_armv7
+  ),
+  (
+    opcode  : A_QADD;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #26#1#0#5;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_QDADD;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #26#1#64#5;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_QDSUB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #26#1#96#5;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_QSUB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #26#1#32#5;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMLABB;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#1#64#8;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMLABT;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#1#0#12;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMLATB;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#1#0#10;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMLATT;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#1#0#14;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMLALBB;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#1#64#8;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMLALBT;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#1#64#12;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMLALTB;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#1#64#10;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMLALTT;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#1#64#14;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_VLDM;
+    ops     : 2;
+    optypes : (ot_memoryam4,ot_reglist,ot_none,ot_none,ot_none,ot_none);
+    code    : #68#12#16#10;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VLDM;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reglist,ot_none,ot_none,ot_none,ot_none);
+    code    : #68#12#16#10;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VSTM;
+    ops     : 2;
+    optypes : (ot_memoryam4,ot_reglist,ot_none,ot_none,ot_none,ot_none);
+    code    : #68#12#0#10;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VSTM;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reglist,ot_none,ot_none,ot_none,ot_none);
+    code    : #68#12#0#10;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VPOP;
+    ops     : 1;
+    optypes : (ot_reglist,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #68#12#189#10;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VPUSH;
+    ops     : 1;
+    optypes : (ot_reglist,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #68#13#45#10;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VLDR;
+    ops     : 2;
+    optypes : (ot_vreg,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #69#13#16#10;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VSTR;
+    ops     : 2;
+    optypes : (ot_vreg,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #69#13#0#10;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_SMULBB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #21#1#96#8;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMULBT;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #21#1#96#12;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMULTB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #21#1#96#10;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMULTT;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #21#1#96#14;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMULWB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #20#1#32#160;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_SMULWT;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #20#1#32#224;
+    flags   : if_arm32 or if_armv5te
+  ),
+  (
+    opcode  : A_STRD;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none);
+    code    : #25#0#0#0#240;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LDRHT;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #25#0#32#0#176;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_STRHT;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #25#0#32#0#176;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LDRSBT;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #25#0#48#0#208;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_STRSBT;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #25#0#48#0#208;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LDRSHT;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #25#0#48#0#240;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_STRSHT;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #25#0#48#0#240;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_BFC;
+    ops     : 3;
+    optypes : (ot_reg32,ot_immediateshifter,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #45#7#192#0#31;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_BFC;
+    ops     : 3;
+    optypes : (ot_reg32,ot_immediateshifter,ot_immediate or ot_bits32,ot_none,ot_none,ot_none);
+    code    : #45#7#192#0#31;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_BFI;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_immediateshifter,ot_none,ot_none);
+    code    : #45#7#192#0#16;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_BFI;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_immediate or ot_bits32,ot_none,ot_none);
+    code    : #45#7#192#0#16;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_CLREX;
+    ops     : 0;
+    optypes : (ot_none,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #47#245#127#240#31;
+    flags   : if_arm32 or if_armv6k
+  ),
+  (
+    opcode  : A_LDREX;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam6,ot_none,ot_none,ot_none,ot_none);
+    code    : #24#1#144#15#159;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LDREXB;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam6,ot_none,ot_none,ot_none,ot_none);
+    code    : #24#1#208#15#159;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LDREXD;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_memoryam6,ot_none,ot_none,ot_none);
+    code    : #24#1#176#15#159;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LDREXH;
+    ops     : 2;
+    optypes : (ot_reg32,ot_memoryam6,ot_none,ot_none,ot_none,ot_none);
+    code    : #24#1#240#15#159;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_STREX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_memoryam6,ot_none,ot_none,ot_none);
+    code    : #24#1#128#15#144;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_STREXB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_memoryam6,ot_none,ot_none,ot_none);
+    code    : #24#1#192#15#144;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_STREXD;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_memoryam6,ot_none,ot_none);
+    code    : #24#1#160#15#144;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_STREXH;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_memoryam6,ot_none,ot_none,ot_none);
+    code    : #24#1#224#15#144;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_MLS;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#0#96#9;
+    flags   : if_arm32 or if_armv6t2
+  ),
+  (
+    opcode  : A_PKHBT;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#128#1;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_PKHBT;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #22#6#128#1;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_PKHTB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#128#5;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_PKHTB;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #22#6#128#5;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_PLI;
+    ops     : 1;
+    optypes : (ot_memoryam2,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #37#246#80#240#0;
+    flags   : if_arm32 or if_armv7
+  ),
+  (
+    opcode  : A_QADD16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#32#241;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_QADD8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#32#249;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_QASX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#32#243;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_QSAX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#32#245;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_QSUB16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#32#247;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_QSUB8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#32#255;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_RBIT;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #50#6#191#15#48;
+    flags   : if_arm32 or if_armv6t2
+  ),
+  (
+    opcode  : A_REV;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #50#6#191#15#48;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_REV16;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #50#6#191#15#176;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_REVSH;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #50#6#255#15#176;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SADD16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#16#241;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SADD8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#16#249;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SASX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#16#243;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SBFX;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_immediateshifter,ot_none,ot_none);
+    code    : #45#7#160#0#80;
+    flags   : if_arm32 or if_armv6t2
+  ),
+  (
+    opcode  : A_SEL;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#128#251;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SETEND;
+    ops     : 1;
+    optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #43#241#1#0#0;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SEV;
+    ops     : 0;
+    optypes : (ot_none,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #47#3#32#240#4;
+    flags   : if_arm32 or if_armv6k
+  ),
+  (
+    opcode  : A_ASR;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #48#1#160#0#80;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ASR;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #48#1#160#0#64;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LSR;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #48#1#160#0#48;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LSR;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #48#1#160#0#32;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LSL;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #48#1#160#0#16;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_LSL;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #48#1#160#0#0;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ROR;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #48#1#160#0#112;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ROR;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #48#1#160#0#96;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_RRX;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #48#1#160#0#96;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_UMAAL;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#0#64#9;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SHADD16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#48#241;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SHADD8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#48#249;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SHASX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#48#243;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SHSAX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#48#245;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SHSUB16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#48#247;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SHSUB8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#48#255;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SMLAD;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#7#0#1;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SMLALD;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#7#64#1;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_SMLSD;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#7#0#5;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SMLSLD;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #22#7#64#5;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SMMLA;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#7#80#1;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SMMLS;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#7#80#13;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SMMUL;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #21#7#80#1;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SMUAD;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #21#7#0#1;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SMUSD;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #21#7#0#5;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SSAT;
+    ops     : 3;
+    optypes : (ot_reg32,ot_immediateshifter,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #42#6#160#0#16;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SSAT;
+    ops     : 4;
+    optypes : (ot_reg32,ot_immediateshifter,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #42#6#160#0#16;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SSAT16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_immediateshifter,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #42#6#160#0#48;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SSAX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#16#245;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SSUB16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#16#247;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SSUB8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#16#255;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTAB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#160#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTAB;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #22#6#160#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTAB16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#128#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTAB16;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #22#6#128#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTAH;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#176#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTAH;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #22#6#176#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UBFX;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_immediateshifter,ot_none,ot_none);
+    code    : #45#7#224#0#80;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_UXTAB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#224#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTAB;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #22#6#224#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTAB16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#192#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTAB16;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #22#6#192#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTAH;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#240#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTAH;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #22#6#240#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTB;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #27#6#175#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
+    code    : #27#6#175#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTB16;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #27#6#143#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTB16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
+    code    : #27#6#143#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTH;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #27#6#191#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_SXTH;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
+    code    : #27#6#191#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTB;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #27#6#239#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
+    code    : #27#6#239#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTB16;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #27#6#207#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTB16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
+    code    : #27#6#207#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTH;
+    ops     : 2;
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #27#6#255#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UXTH;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
+    code    : #27#6#255#7;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UADD16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#80#241;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UADD8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#80#249;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UASX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#80#243;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UHADD16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#112#241;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UHADD8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#112#249;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UHASX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#112#243;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UHSAX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#112#245;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UHSUB16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#112#247;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UHSUB8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#112#255;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UQADD16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#96#241;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UQADD8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#96#249;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UQASX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#96#243;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UQSAX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#96#245;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UQSUB16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#96#247;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_UQSUB8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#96#255;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_USAD8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #21#7#128#1;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_USADA8;
+    ops     : 4;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
+    code    : #21#7#128#1;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_USAT;
+    ops     : 3;
+    optypes : (ot_reg32,ot_immediateshifter,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #42#6#224#0#16;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_USAT;
+    ops     : 4;
+    optypes : (ot_reg32,ot_immediateshifter,ot_reg32,ot_shifterop,ot_none,ot_none);
+    code    : #42#6#224#0#16;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_USAT16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_immediateshifter,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #42#6#224#0#48;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_USAX;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#80#246;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_USUB16;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#80#247;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_USUB8;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
+    code    : #22#6#80#255;
+    flags   : if_arm32 or if_armv6
+  ),
+  (
+    opcode  : A_WFE;
+    ops     : 0;
+    optypes : (ot_none,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #47#3#32#240#2;
+    flags   : if_arm32 or if_armv6k
+  ),
+  (
+    opcode  : A_WFI;
+    ops     : 0;
+    optypes : (ot_none,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #47#3#32#240#3;
+    flags   : if_arm32 or if_armv6k
+  ),
+  (
+    opcode  : A_YIELD;
+    ops     : 0;
+    optypes : (ot_none,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #47#3#32#240#1;
+    flags   : if_arm32 or if_armv6k
+  ),
+  (
+    opcode  : A_POP;
+    ops     : 1;
+    optypes : (ot_reglist,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #38#128;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_PUSH;
+    ops     : 1;
+    optypes : (ot_reglist,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #38#128;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_MOVT;
+    ops     : 2;
+    optypes : (ot_reg32,ot_immediate,ot_none,ot_none,ot_none,ot_none);
+    code    : #44#3#64;
+    flags   : if_arm32 or if_armv6t2
+  ),
+  (
+    opcode  : A_MOVT;
+    ops     : 2;
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #44#3#64;
+    flags   : if_arm32 or if_armv6t2
+  ),
+  (
+    opcode  : A_IT;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITE;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITT;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITEE;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITTE;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITET;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITTT;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITEEE;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITTEE;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITETE;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITTTE;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITEET;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITTET;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITETT;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_ITTTT;
+    ops     : 1;
+    optypes : (ot_condition,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #254;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_MOVW;
+    ops     : 2;
+    optypes : (ot_reg32,ot_immediate,ot_none,ot_none,ot_none,ot_none);
+    code    : #44#3#0;
+    flags   : if_arm32 or if_armv6t2
+  ),
+  (
+    opcode  : A_MOVW;
+    ops     : 2;
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #44#3#0;
+    flags   : if_arm32 or if_armv6t2
+  ),
+  (
+    opcode  : A_VABS;
+    ops     : 2;
+    optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
+    code    : #66#14#176#10#192;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VADD;
+    ops     : 3;
+    optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
+    code    : #66#14#48#10#0;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VCMP;
+    ops     : 2;
+    optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
+    code    : #66#14#180#10#64;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VCMP;
+    ops     : 2;
+    optypes : (ot_vreg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #66#14#181#10#64;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VCMPE;
+    ops     : 2;
+    optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
+    code    : #66#14#180#10#192;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VCMPE;
+    ops     : 2;
+    optypes : (ot_vreg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #66#14#181#10#192;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VCVT;
+    ops     : 2;
+    optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
+    code    : #67#14#184#10#192;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VCVT;
+    ops     : 3;
+    optypes : (ot_vreg,ot_vreg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #67#14#186#10#64;
+    flags   : if_arm32 or if_vfpv3
+  ),
+  (
+    opcode  : A_VCVTR;
+    ops     : 2;
+    optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
+    code    : #67#14#184#10#64;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VDIV;
+    ops     : 3;
+    optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
+    code    : #66#14#128#10#0;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMRS;
+    ops     : 2;
+    optypes : (ot_reg32,ot_regf,ot_none,ot_none,ot_none,ot_none);
+    code    : #65#14#240#10#16;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMRS;
+    ops     : 2;
+    optypes : (ot_regf,ot_regf,ot_none,ot_none,ot_none,ot_none);
+    code    : #65#14#240#10#16;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMSR;
+    ops     : 2;
+    optypes : (ot_regf,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #65#14#224#10#16;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMLA;
+    ops     : 3;
+    optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
+    code    : #66#14#0#10#0;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMLS;
+    ops     : 3;
+    optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
+    code    : #66#14#0#10#64;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VMUL;
+    ops     : 3;
+    optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
+    code    : #66#14#32#10#0;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VNMLA;
+    ops     : 3;
+    optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
+    code    : #66#14#16#10#64;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VNMLS;
+    ops     : 3;
+    optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
+    code    : #66#14#16#10#0;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VNMUL;
+    ops     : 3;
+    optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
+    code    : #66#14#32#10#64;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VNEG;
+    ops     : 2;
+    optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
+    code    : #66#14#177#10#64;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VSQRT;
+    ops     : 2;
+    optypes : (ot_vreg,ot_vreg,ot_none,ot_none,ot_none,ot_none);
+    code    : #66#14#177#10#192;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_VSUB;
+    ops     : 3;
+    optypes : (ot_vreg,ot_vreg,ot_vreg,ot_none,ot_none,ot_none);
+    code    : #66#14#48#10#64;
+    flags   : if_arm32 or if_vfpv2
+  ),
+  (
+    opcode  : A_DMB;
+    ops     : 1;
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #46#245#127#240#80;
+    flags   : if_arm32 or if_armv7
+  ),
+  (
+    opcode  : A_ISB;
+    ops     : 1;
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #46#245#127#240#96;
+    flags   : if_arm32 or if_armv7
+  ),
+  (
+    opcode  : A_DSB;
+    ops     : 1;
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #46#245#127#240#64;
+    flags   : if_arm32 or if_armv7
+  ),
+  (
+    opcode  : A_SMC;
+    ops     : 1;
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #46#1#96#0#112;
+    flags   : if_arm32 or if_armv7
+  ),
+  (
+    opcode  : A_SVC;
+    ops     : 1;
+    optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #2#15;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_SVC;
+    ops     : 1;
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #2#15;
+    flags   : if_arm32 or if_armv4
+  ),
+  (
+    opcode  : A_BXJ;
+    ops     : 1;
+    optypes : (ot_reg32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #3#1#47#255#32;
+    flags   : if_arm32 or if_armv5tej
+  ),
+  (
+    opcode  : A_UDF;
+    ops     : 0;
+    optypes : (ot_none,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #0;
+    flags   : if_none
   )
 );

compiler/arm/cpubase.pas

@@ -130,6 +130,10 @@ unit cpubase;
         PF_S,
         { floating point size }
         PF_D,PF_E,PF_P,PF_EP,
+        { exchange }
+        PF_X,
+        { rounding }
+        PF_R,
         { load/store }
         PF_B,PF_SB,PF_BT,PF_H,PF_SH,PF_T,
         { multiple load/store address modes }
@@ -138,10 +142,18 @@ unit cpubase;
         PF_IAD,PF_DBD,PF_FDD,PF_EAD,
         PF_IAS,PF_DBS,PF_FDS,PF_EAS,
         PF_IAX,PF_DBX,PF_FDX,PF_EAX,
-        { FPv4 postfixes }
-        PF_32,PF_64,PF_F32,PF_F64,
-        PF_F32S32,PF_F32U32,
-        PF_S32F32,PF_U32F32
+        { VFP postfixes }
+        PF_8,PF_16,PF_32,PF_64,
+        PF_I8,PF_I16,PF_I32,PF_I64,
+        PF_S8,PF_S16,PF_S32,PF_S64,
+        PF_U8,PF_U16,PF_U32,PF_U64,
+        PF_P8, // polynomial
+        PF_F32,PF_F64,
+        PF_F32F64,PF_F64F32,
+        PF_F32S16,PF_F32U16,PF_S16F32,PF_U16F32,
+        PF_F64S16,PF_F64U16,PF_S16F64,PF_U16F64,
+        PF_F32S32,PF_F32U32,PF_S32F32,PF_U32F32,
+        PF_F64S32,PF_F64U32,PF_S32F64,PF_U32F64
       );
 
       TOpPostfixes = set of TOpPostfix;
@@ -157,14 +169,24 @@ unit cpubase;
       oppostfix2str : array[TOpPostfix] of string[8] = ('',
         's',
         'd','e','p','ep',
+        'x',
+        'r',
         'b','sb','bt','h','sh','t',
         'ia','ib','da','db','fd','fa','ed','ea',
         'iad','dbd','fdd','ead',
         'ias','dbs','fds','eas',
         'iax','dbx','fdx','eax',
-        '.32','.64','.f32','.f64',
-        '.f32.s32','.f32.u32',
-        '.s32.f32','.u32.f32');
+        '.8','.16','.32','.64',
+        '.i8','.i16','.i32','.i64',
+        '.s8','.s16','.s32','.s64',
+        '.u8','.u16','.u32','.u64',
+        '.p8',
+        '.f32','.f64',
+        '.f32.f64','.f64.f32',
+        '.f32.s16','.f32.u16','.s16.f32','.u16.f32',
+        '.f64.s16','.f64.u16','.s16.f64','.u16.f64',
+        '.f32.s32','.f32.u32','.s32.f32','.u32.f32',
+        '.f64.s32','.f64.u32','.s32.f64','.u32.f64');
 
       roundingmode2str : array[TRoundingMode] of string[1] = ('',
         'p','m','z');

compiler/arm/rarmcon.inc

@@ -123,3 +123,7 @@ NR_BASEPRI = tregister($0500001F);
 NR_BASEPRI_MAX = tregister($05000020);
 NR_FAULTMASK = tregister($05000021);
 NR_CONTROL = tregister($05000022);
+NR_FPSID = tregister($05000023);
+NR_MVFR1 = tregister($05000024);
+NR_MVFR0 = tregister($05000025);
+NR_FPEXC = tregister($05000026);

compiler/arm/rarmdwa.inc

@@ -122,4 +122,8 @@
 0,
 0,
 0,
+0,
+0,
+0,
+0,
 0

compiler/arm/rarmnor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armreg.dat }
-124
+128

compiler/arm/rarmnum.inc

@@ -122,4 +122,8 @@ tregister($0500001E),
 tregister($0500001F),
 tregister($05000020),
 tregister($05000021),
-tregister($05000022)
+tregister($05000022),
+tregister($05000023),
+tregister($05000024),
+tregister($05000025),
+tregister($05000026)

compiler/arm/rarmrni.inc

@@ -122,4 +122,8 @@
 120,
 121,
 122,
-123
+123,
+124,
+125,
+126,
+127

compiler/arm/rarmsri.inc

@@ -65,11 +65,15 @@
 23,
 24,
 122,
+127,
 90,
+124,
 114,
 113,
 111,
 117,
+126,
+125,
 109,
 119,
 118,
@@ -104,7 +108,6 @@
 53,
 28,
 55,
-71,
 56,
 58,
 59,
@@ -116,6 +119,7 @@
 68,
 29,
 70,
+71,
 31,
 32,
 34,

compiler/arm/rarmsta.inc

@@ -122,4 +122,8 @@
 0,
 0,
 0,
+0,
+0,
+0,
+0,
 0

compiler/arm/rarmstd.inc

@@ -70,7 +70,7 @@
 's29',
 'd14',
 's30',
-'s21',
+'s31',
 'd15',
 'd16',
 'd17',
@@ -122,4 +122,8 @@
 'basepri',
 'basepri_max',
 'faultmask',
-'control'
+'control',
+'fpsid',
+'mvfr1',
+'mvfr0',
+'fpexc'

compiler/arm/rarmsup.inc

@@ -123,3 +123,7 @@ RS_BASEPRI = $1F;
 RS_BASEPRI_MAX = $20;
 RS_FAULTMASK = $21;
 RS_CONTROL = $22;
+RS_FPSID = $23;
+RS_MVFR1 = $24;
+RS_MVFR0 = $25;
+RS_FPEXC = $26;

compiler/utils/mkarmins.pp

@@ -186,7 +186,7 @@ var
    opcode,
    codes,
    flags   : string;
-   optypes : array[1..4] of string;
+   optypes : array[1..6] of string;
 begin
    writeln('Narm Instruction Table Converter Version ',Version);
    insns:=0;
@@ -298,6 +298,8 @@ begin
         optypes[2]:='';
         optypes[3]:='';
         optypes[4]:='';
+        optypes[5]:='';
+        optypes[6]:='';
         codes:='';
         flags:='';
         skip:=false;
@@ -324,8 +326,8 @@ begin
           else
             break;
         until false;
-        for j:=1 to 4-ops do
-          optypes[4-j+1]:='ot_none';
+        for j:=1 to 6-ops do
+          optypes[6-j+1]:='ot_none';
         { codes }
         skipspace;
         j:=0;
@@ -385,7 +387,7 @@ begin
             writeln(insfile,'  (');
             writeln(insfile,'    opcode  : ',opcode,';');
             writeln(insfile,'    ops     : ',ops,';');
-            writeln(insfile,'    optypes : (',optypes[1],',',optypes[2],',',optypes[3],',',optypes[4],');');
+            writeln(insfile,'    optypes : (',optypes[1],',',optypes[2],',',optypes[3],',',optypes[4],',',optypes[5],',',optypes[6],');');
             writeln(insfile,'    code    : ',codes,';');
             writeln(insfile,'    flags   : ',flags);
             write(insfile,'  )');