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* better zero extension for Risc-V32

florian 1 year ago
parent
commit
d270c2ccdd
1 changed files with 2 additions and 0 deletions
  1. 2 0
      compiler/riscv32/cgcpu.pas

+ 2 - 0
compiler/riscv32/cgcpu.pas

@@ -127,6 +127,8 @@ unit cgcpu;
           end
         else if (tcgsize2unsigned[tosize]=OS_32) and (fromsize=OS_8) then
           list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
+        else if (tosize=OS_8) and (fromsize<>OS_8) then
+          list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
         else if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or
           ((tcgsize2size[fromsize] = tcgsize2size[tosize]) and (fromsize <> tosize)) or
           { do we need to mask out the sign when loading from smaller signed to larger unsigned type? }