* correctly handle sign/zero extensions for optimization "var3", resolves #37254

git-svn-id: trunk@45713 -

.gitattributes

@@ -18345,6 +18345,7 @@ tests/webtbs/tw3719.pp svneol=native#text/plain
 tests/webtbs/tw3721.pp svneol=native#text/plain
 tests/webtbs/tw37218.pp svneol=native#text/pascal
 tests/webtbs/tw37228.pp svneol=native#text/plain
+tests/webtbs/tw37254.pp svneol=native#text/pascal
 tests/webtbs/tw37272a.pp svneol=native#text/pascal
 tests/webtbs/tw3742.pp svneol=native#text/plain
 tests/webtbs/tw3751.pp svneol=native#text/plain

compiler/x86/aoptx86.pas

@@ -5261,6 +5261,8 @@ unit aoptx86;
           MatchInstruction(hp2,A_MOV,[]) and
           (taicpu(hp2).oper[0]^.typ = top_reg) and
           OpsEqual(taicpu(hp2).oper[1]^,taicpu(p).oper[0]^) and
+          ((taicpu(p).opsize in [S_BW,S_BL]) and (taicpu(hp2).opsize=S_B) or
+           (taicpu(p).opsize in [S_WL]) and (taicpu(hp2).opsize=S_W)) and
 {$ifdef i386}
            { not all registers have byte size sub registers on i386 }
            ((taicpu(hp2).opsize<>S_B) or (getsupreg(taicpu(hp1).oper[0]^.reg) in [RS_EAX, RS_EBX, RS_ECX, RS_EDX])) and

tests/webtbs/tw37254.pp

@@ -0,0 +1,22 @@
+{ OPT=-O- -O1 }
+{$mode objfpc}
+function Get8bShr1_CORRECT(n: SizeUint): SizeUint;
+begin
+  result := uint8(n) shr 1;
+end;
+
+
+function Get8bShr1_BUGGY_x86_32(n: SizeUint): SizeUint;
+begin
+  result := n;
+  result := uint8(result) shr 1;
+end;
+
+
+begin
+  writeln('Correct: ', HexStr(Get8bShr1_CORRECT($AAAAAA), bitsizeof(SizeUint) div 4));
+  writeln('Wrong: ', HexStr(Get8bShr1_BUGGY_x86_32($AAAAAA), bitsizeof(SizeUint) div 4));
+  if Get8bShr1_BUGGY_x86_32($AAAAAA)<>$55 then
+    halt(1);
+  writeln('ok');
+end.