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@@ -106,7 +106,12 @@ uses
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taicpu = class(tai_cpu_abstract_sym)
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private
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+ { next fields are filled in pass1, so pass2 is faster }
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+ insentry : PInsEntry;
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+ inssize : shortint;
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+
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function Matches(p:PInsEntry):boolean;
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+ function FindInsentry(objdata:TObjData):boolean;
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public
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constructor op_none(op : tasmop);
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@@ -131,6 +136,8 @@ uses
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{ register spilling code }
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function spilling_get_operation_type(opnr: longint): topertype;override;
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+
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+ function GetString:string;
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end;
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tai_align = class(tai_align_abstract)
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@@ -333,6 +340,50 @@ implementation
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end;
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+ function taicpu.FindInsentry(objdata: TObjData): boolean;
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+ var
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+ i : longint;
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+ begin
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+ result:=false;
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+ { Things which may only be done once, not when a second pass is done to
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+ optimize }
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+
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+ if (Insentry=nil) {or (IF_PASS2 in InsEntry^.flags)} then
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+ begin
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+ { set the file postion }
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+ current_filepos:=fileinfo;
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+ end
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+ else
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+ begin
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+ { we've already an insentry so it's valid }
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+ result:=true;
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+ exit;
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+ end;
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+ { Lookup opcode in the table }
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+ InsSize:=-1;
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+ i:=instabcache^[opcode];
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+ if i=-1 then
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+ begin
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+ Message1(asmw_e_opcode_not_in_table,std_op2str[opcode]);
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+ exit;
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+ end;
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+ insentry:=@instab[i];
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+ while (insentry^.opcode=opcode) do
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+ begin
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+ if matches(insentry) then
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+ begin
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+ result:=true;
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+ exit;
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+ end;
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+ inc(insentry);
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+ end;
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+ Message1(asmw_e_invalid_opcode_and_operands,GetString);
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+ { No instruction found, set insentry to nil and inssize to -1 }
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+ insentry:=nil;
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+ inssize:=-1;
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+ end;
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+
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+
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constructor taicpu.op_none(op : tasmop);
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begin
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inherited create(op);
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@@ -490,6 +541,130 @@ implementation
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end;
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+ function taicpu.GetString: string;
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+ var
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+ //i : longint;
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+ s : string;
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+ //regnr: string;
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+ //addsize : boolean;
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+ begin
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+ s:='['+std_op2str[opcode];
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+ //for i:=0 to ops-1 do
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+ // begin
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+ // with oper[i]^ do
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+ // begin
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+ // if i=0 then
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+ // s:=s+' '
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+ // else
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+ // s:=s+',';
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+ // { type }
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+ // addsize:=false;
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+ //
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+ // regnr := '';
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+ // if getregtype(reg) = R_MMREGISTER then
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+ // str(getsupreg(reg),regnr);
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+ //
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+ // if (ot and OT_XMMREG)=OT_XMMREG then
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+ // s:=s+'xmmreg' + regnr
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+ // else
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+ // if (ot and OT_YMMREG)=OT_YMMREG then
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+ // s:=s+'ymmreg' + regnr
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+ // else
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+ // if (ot and OT_ZMMREG)=OT_ZMMREG then
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+ // s:=s+'zmmreg' + regnr
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+ //
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+ // else
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+ // if (ot and OT_REG_EXTRA_MASK)=OT_MMXREG then
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+ // s:=s+'mmxreg'
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+ // else
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+ // if (ot and OT_REG_EXTRA_MASK)=OT_FPUREG then
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+ // s:=s+'fpureg'
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+ // else
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+ // if (ot and OT_REGISTER)=OT_REGISTER then
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+ // begin
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+ // s:=s+'reg';
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+ // addsize:=true;
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+ // end
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+ // else
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+ // if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
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+ // begin
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+ // s:=s+'imm';
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+ // addsize:=true;
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+ // end
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+ // else
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+ // if (ot and OT_MEMORY)=OT_MEMORY then
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+ // begin
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+ // s:=s+'mem';
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+ // addsize:=true;
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+ // end
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+ // else
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+ // s:=s+'???';
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+ // { size }
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+ // if addsize then
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+ // begin
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+ // if (ot and OT_BITS8)<>0 then
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+ // s:=s+'8'
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+ // else
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+ // if (ot and OT_BITS16)<>0 then
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+ // s:=s+'16'
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+ // else
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+ // if (ot and OT_BITS32)<>0 then
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+ // s:=s+'32'
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+ // else
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+ // if (ot and OT_BITS64)<>0 then
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+ // s:=s+'64'
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+ // else
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+ // if (ot and OT_BITS128)<>0 then
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+ // s:=s+'128'
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+ // else
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+ // if (ot and OT_BITS256)<>0 then
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+ // s:=s+'256'
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+ // else
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+ // if (ot and OT_BITS512)<>0 then
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+ // s:=s+'512'
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+ // else
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+ // s:=s+'??';
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+ // { signed }
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+ // if (ot and OT_SIGNED)<>0 then
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+ // s:=s+'s';
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+ // end;
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+ //
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+ // if vopext <> 0 then
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+ // begin
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+ // str(vopext and $07, regnr);
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+ // if vopext and OTVE_VECTOR_WRITEMASK = OTVE_VECTOR_WRITEMASK then
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+ // s := s + ' {k' + regnr + '}';
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+ //
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+ // if vopext and OTVE_VECTOR_ZERO = OTVE_VECTOR_ZERO then
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+ // s := s + ' {z}';
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+ //
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+ // if vopext and OTVE_VECTOR_SAE = OTVE_VECTOR_SAE then
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+ // s := s + ' {sae}';
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+ //
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+ //
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+ // if vopext and OTVE_VECTOR_BCST = OTVE_VECTOR_BCST then
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+ // case vopext and OTVE_VECTOR_BCST_MASK of
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+ // OTVE_VECTOR_BCST2: s := s + ' {1to2}';
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+ // OTVE_VECTOR_BCST4: s := s + ' {1to4}';
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+ // OTVE_VECTOR_BCST8: s := s + ' {1to8}';
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+ // OTVE_VECTOR_BCST16: s := s + ' {1to16}';
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+ // end;
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+ //
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+ // if vopext and OTVE_VECTOR_ER = OTVE_VECTOR_ER then
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+ // case vopext and OTVE_VECTOR_ER_MASK of
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+ // OTVE_VECTOR_RNSAE: s := s + ' {rn-sae}';
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+ // OTVE_VECTOR_RDSAE: s := s + ' {rd-sae}';
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+ // OTVE_VECTOR_RUSAE: s := s + ' {ru-sae}';
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+ // OTVE_VECTOR_RZSAE: s := s + ' {rz-sae}';
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+ // end;
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+ //
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+ // end;
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+ // end;
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+ // end;
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+ GetString:=s+']';
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+ end;
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+
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+
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function spilling_create_load(const ref:treference;r:tregister):Taicpu;
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begin
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case getregtype(r) of
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nickysn