* don't emit the "SUB ECX,32" instruction on i386, when doing a 64-bit shift by

  reg, with a value >=32. The instruction is redundant, because the SHL/SHR
  instructions already AND mask the shift count by 31.

git-svn-id: trunk@35836 -

compiler/i386/cgcpu.pas

@@ -701,7 +701,6 @@ unit cgcpu;
               current_asmdata.getjumplabel(l2);
               list.Concat(taicpu.op_const_reg(A_TEST,S_L,32,NR_ECX));
               cg.a_jmp_flags(list,F_E,l1);
-              list.Concat(taicpu.op_const_reg(A_SUB,S_L,32,NR_ECX));
               tmpreg:=cg.getintregister(list,OS_32);
               case op of
                 OP_SHL:
@@ -835,7 +834,6 @@ unit cgcpu;
               current_asmdata.getjumplabel(l2);
               list.Concat(taicpu.op_const_reg(A_TEST,S_L,32,NR_ECX));
               cg.a_jmp_flags(list,F_E,l1);
-              list.Concat(taicpu.op_const_reg(A_SUB,S_L,32,NR_ECX));
               case op of
                 OP_SHL:
                   begin

compiler/i386/n386mat.pas

@@ -181,7 +181,6 @@ implementation
             current_asmdata.getjumplabel(l3);
             emit_const_reg(A_TEST,S_L,32,NR_ECX);
             cg.a_jmp_flags(current_asmdata.CurrAsmList,F_E,l2);
-            emit_const_reg(A_SUB,S_L,32,NR_ECX);
             if nodetype=shln then
               begin
                 emit_reg_reg(A_SHL,S_L,NR_CL,hreg64lo);