first insertion 2002\08\22

compiler/sparc/attinstr.inc

@@ -0,0 +1,72 @@
+{*****************************************************************************}
+{ File                   : attinstr.inc                                       }
+{ Author                 : Mazen NEIFER                                       }
+{ Project                : Free Pascal Compiler (FPC)                         }
+{ Creation date          : 2002\05\08                                         }
+{ Last modification date : 2002\07\01                                         }
+{ Licence                : GPL                                                }
+{ Bug report             : [email protected]                        }
+{*****************************************************************************}
+          'NONE',
+          'ABCD',
+          'ADD','ADDcc','ADDX','ADDXcc',
+          'AND','ANDcc','ANDN','ADDNcc',
+          'BN','BNE','BE','BG','BLE','BGE','BI','BGU','BLEU','BCC',
+          'BCS','BPOS','NEG','BVC','BVS','BA',
+          'CALL',
+          'CBccc',
+          'FBN','FBU','FBG','FBUG','FBL','FBUL','FBLG','FBNE',
+          'FBE','FBUE','FBGE','FBUGE','FBLE','FBULE','FBO','FBA',
+          'FLUSH',
+          'JMPL',
+          'LDSB','LDSH','LDSTUB',
+          'LDUB','LDUH','LD','LDD','LDF','LDFSR','LDDF','LDC','LDCSR','LDDC',
+          'LDSBA','LDSHA','LDUBA','LDUHA','LDA','LDDA',
+          'LDSTUBA',
+          'MULScc',
+          'NOP',
+          'OR','ORcc','ORN','ORNcc',
+          'RDASR','RDY','RDPSR','RDWIM','RDTBR',
+          'RESTORE',
+          'RETT',
+          'SAVE',
+          'SDIV','SDIVcc',
+          'SMUL','SMULcc',
+          'SETHI',
+          'SLL','SRL','SRA',
+          'STB','STH','ST','STD','STF','STDF','STFSR','STDFQ',
+          'STC','STDC','STCSR','STDCQ',
+          'STBA','STHA','STA','STDA',
+          'SUB','SUBcc','SUBX','SUBXcc',
+          'SWAP','SWAPA','Ticc','TADDcc','TSUBcc','TADDccTV','TSUBccTV',
+          'UDIV','UDIVcc',
+          'UMUL','UMULcc',
+          'UNMP',
+          'WRASR','WRY','WRPSR','WRWIM','WRTBR',
+          'XNOR','XNORcc',
+          'XOR','XORcc',
+          {Floating-point instructions}
+          'FiTOs','FiTOd','FiTOq',
+          'FsTOi','FdTOi','FqTOi',
+          'FsTOd','FsTOq',
+          'FdTOs','FdTOq',
+          'FqTOd','FqTOs',
+          'MOVs','NEGs','FABSs',
+          'FSQRTs','FSQRTd','FSQRTq',
+          'FADDs','FADDd','FADDq',
+          'FSUBs','FSUBd','FSUBq',
+          'FMULs','FMULd','FMULQ',
+          'FdMULq','FsMULd',
+          'DIVs','DIVd','FDIVq',
+          'FCMPs','FCMPd','FCMPq',
+          'FCPop1','CPop2',
+          {Synthetic instructions}
+          'btst','bset','bclr','btog',
+          'clr','clrb','clrh',
+          'cmp',
+          'dec','deccc',
+          'inc','inccc',
+          'not',
+          'set',
+          'skipz','skipnz',
+          'tst'

compiler/sparc/cga.pas

@@ -0,0 +1,300 @@
+{*****************************************************************************}
+{ File                   : cga.pas                                            }
+{ Author                 : Mazen NEIFER                                       }
+{ Project                : Free Pascal Compiler (FPC)                         }
+{ Creation date          : 2002\26\26                                         }
+{ Last modification date : 2002\07\13                                         }
+{ Licence                : GPL                                                }
+{ Bug report             : [email protected]                        }
+{*****************************************************************************}
+{
+    $Id$
+    Copyright (c) 1998-2002 by Florian Klaempfl
+
+    Helper routines for the i386 code generator
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+
+unit cga;
+
+{$i fpcdefs.inc}
+
+interface
+
+    uses
+       cpuinfo,cpubase,cginfo,
+       symconst,symtype,symdef,aasmbase,aasmtai,aasmcpu;
+
+{$define TESTGETTEMP to store const that
+ are written into temps for later release PM }
+
+    function def_opsize(p1:tdef):topsize;
+    function def_getreg(p1:tdef):tregister;
+
+    procedure emitjmp(c : tasmcond;var l : tasmlabel);
+
+    procedure emit_none(i : tasmop;s : topsize);
+
+    procedure emit_const(i : tasmop;s : topsize;c : longint);
+    procedure emit_reg(i : tasmop;s : topsize;reg : tregister);
+    procedure emit_ref(i : tasmop;s : topsize;const ref : treference);
+
+    procedure emit_const_reg(i : tasmop;s : topsize;c : longint;reg : tregister);
+    procedure emit_const_ref(i : tasmop;s : topsize;c : longint;const ref : treference);
+    procedure emit_ref_reg(i : tasmop;s : topsize;const ref : treference;reg : tregister);
+    procedure emit_reg_ref(i : tasmop;s : topsize;reg : tregister;const ref : treference);
+    procedure emit_reg_reg(i : tasmop;s : topsize;reg1,reg2 : tregister);
+
+    procedure emit_const_reg_reg(i : tasmop;s : topsize;c : longint;reg1,reg2 : tregister);
+    procedure emit_reg_reg_reg(i : tasmop;s : topsize;reg1,reg2,reg3 : tregister);
+
+
+    procedure emit_sym(i : tasmop;s : topsize;op : tasmsymbol);
+
+
+implementation
+
+    uses
+       cutils,
+       systems,globals,verbose,
+       cgbase,cgobj,tgobj,rgobj,rgcpu;
+
+
+{*****************************************************************************
+                                Helpers
+*****************************************************************************}
+
+    function def_opsize(p1:tdef):topsize;
+      begin
+        case p1.size of
+         1 : def_opsize:=S_B;
+         2 : def_opsize:=S_W;
+         4 : def_opsize:=S_L;
+         { I don't know if we need it (FK) }
+         8 : def_opsize:=S_L;
+        else
+         internalerror(130820001);
+        end;
+      end;
+
+
+    function def_getreg(p1:tdef):tregister;
+      begin
+        def_getreg:=rg.makeregsize(rg.getregisterint(exprasmlist),int_cgsize(p1.size));
+      end;
+
+
+{*****************************************************************************
+                              Emit Assembler
+*****************************************************************************}
+
+    procedure emitjmp(c : tasmcond;var l : tasmlabel);
+      var
+        ai : taicpu;
+      begin
+        if c=C_None then
+          ai := Taicpu.Op_sym(A_JMPL,S_NO,l)
+        else
+          begin
+            ai:=Taicpu.Op_sym(A_JMPL,S_NO,l);
+            ai.SetCondition(c);
+          end;
+        ai.is_jmp:=true;
+        exprasmList.concat(ai);
+      end;
+
+
+    procedure emit_none(i : tasmop;s : topsize);
+      begin
+         exprasmList.concat(Taicpu.Op_none(i,s));
+      end;
+
+    procedure emit_reg(i : tasmop;s : topsize;reg : tregister);
+      begin
+         exprasmList.concat(Taicpu.Op_reg(i,s,reg));
+      end;
+
+    procedure emit_ref(i : tasmop;s : topsize;const ref : treference);
+      begin
+         exprasmList.concat(Taicpu.Op_ref(i,s,ref));
+      end;
+
+    procedure emit_const(i : tasmop;s : topsize;c : longint);
+      begin
+         exprasmList.concat(Taicpu.Op_const(i,s,aword(c)));
+      end;
+
+    procedure emit_const_reg(i : tasmop;s : topsize;c : longint;reg : tregister);
+      begin
+         exprasmList.concat(Taicpu.Op_const_reg(i,s,aword(c),reg));
+      end;
+
+    procedure emit_const_ref(i : tasmop;s : topsize;c : longint;const ref : treference);
+      begin
+         exprasmList.concat(Taicpu.Op_const_ref(i,s,aword(c),ref));
+      end;
+
+    procedure emit_ref_reg(i : tasmop;s : topsize;const ref : treference;reg : tregister);
+      begin
+         exprasmList.concat(Taicpu.Op_ref_reg(i,s,ref,reg));
+      end;
+
+    procedure emit_reg_ref(i : tasmop;s : topsize;reg : tregister;const ref : treference);
+      begin
+         exprasmList.concat(Taicpu.Op_reg_ref(i,s,reg,ref));
+      end;
+
+PROCEDURE emit_reg_reg(i:tasmop;s:topsize;reg1,reg2:tregister);
+  BEGIN
+    IF reg1<>reg2
+    THEN
+      exprasmList.concat(Taicpu.Op_reg_reg(i,s,reg1,reg2));
+  END;
+
+    procedure emit_const_reg_reg(i : tasmop;s : topsize;c : longint;reg1,reg2 : tregister);
+      begin
+         exprasmList.concat(Taicpu.Op_reg_const_reg(i,s,reg1,c,reg2));
+      end;
+
+    procedure emit_reg_reg_reg(i : tasmop;s : topsize;reg1,reg2,reg3 : tregister);
+      begin
+         exprasmList.concat(Taicpu.Op_reg_reg_reg(i,s,reg1,reg2,reg3));
+      end;
+
+    procedure emit_sym(i : tasmop;s : topsize;op : tasmsymbol);
+      begin
+        exprasmList.concat(Taicpu.Op_sym(i,s,op));
+      end;
+
+end.
+{
+  $Log$
+  Revision 1.1  2002-08-22 08:30:50  mazen
+  first insertion 2002\08\22
+
+  Revision 1.32  2002/05/18 13:34:21  peter
+    * readded missing revisions
+
+  Revision 1.31  2002/05/16 19:46:50  carl
+  + defines.inc -> fpcdefs.inc to avoid conflicts if compiling by hand
+  + try to fix temp allocation (still in ifdef)
+  + generic constructor calls
+  + start of tassembler / tmodulebase class cleanup
+
+  Revision 1.29  2002/05/13 19:54:37  peter
+    * removed n386ld and n386util units
+    * maybe_save/maybe_restore added instead of the old maybe_push
+
+  Revision 1.28  2002/05/12 16:53:16  peter
+    * moved entry and exitcode to ncgutil and cgobj
+    * foreach gets extra argument for passing local data to the
+      iterator function
+    * -CR checks also class typecasts at runtime by changing them
+      into as
+    * fixed compiler to cycle with the -CR option
+    * fixed stabs with elf writer, finally the global variables can
+      be watched
+    * removed a lot of routines from cga unit and replaced them by
+      calls to cgobj
+    * u32bit-s32bit updates for and,or,xor nodes. When one element is
+      u32bit then the other is typecasted also to u32bit without giving
+      a rangecheck warning/error.
+    * fixed pascal calling method with reversing also the high tree in
+      the parast, detected by tcalcst3 test
+
+  Revision 1.27  2002/04/25 20:16:39  peter
+    * moved more routines from cga/n386util
+
+  Revision 1.26  2002/04/21 15:29:53  carl
+  * changeregsize -> rg.makeregsize
+
+  Revision 1.25  2002/04/20 21:37:07  carl
+  + generic FPC_CHECKPOINTER
+  + first parameter offset in stack now portable
+  * rename some constants
+  + move some cpu stuff to other units
+  - remove unused constents
+  * fix stacksize for some targets
+  * fix generic size problems which depend now on EXTEND_SIZE constant
+  * removing frame pointer in routines is only available for : i386,m68k and vis targets
+
+  Revision 1.24  2002/04/19 15:39:34  peter
+    * removed some more routines from cga
+    * moved location_force_reg/mem to ncgutil
+    * moved arrayconstructnode secondpass to ncgld
+
+  Revision 1.23  2002/04/15 19:44:20  peter
+    * fixed stackcheck that would be called recursively when a stack
+      error was found
+    * generic changeregsize(reg,size) for i386 register resizing
+    * removed some more routines from cga unit
+    * fixed returnvalue handling
+    * fixed default stacksize of linux and go32v2, 8kb was a bit small :-)
+
+  Revision 1.22  2002/04/14 20:54:17  carl
+  + stack checking enabled for all targets (it is simulated now)
+
+  Revision 1.21  2002/04/04 19:06:08  peter
+    * removed unused units
+    * use tlocation.size in cg.a_*loc*() routines
+
+  Revision 1.20  2002/04/04 18:30:22  carl
+  + added wdosx support (patch from Pavel)
+
+  Revision 1.19  2002/04/02 17:11:33  peter
+    * tlocation,treference update
+    * LOC_CONSTANT added for better constant handling
+    * secondadd splitted in multiple routines
+    * location_force_reg added for loading a location to a register
+      of a specified size
+    * secondassignment parses now first the right and then the left node
+      (this is compatible with Kylix). This saves a lot of push/pop especially
+      with string operations
+    * adapted some routines to use the new cg methods
+
+  Revision 1.18  2002/03/31 20:26:37  jonas
+    + a_loadfpu_* and a_loadmm_* methods in tcg
+    * register allocation is now handled by a class and is mostly processor
+      independent (+rgobj.pas and i386/rgcpu.pas)
+    * temp allocation is now handled by a class (+tgobj.pas, -i386\tgcpu.pas)
+    * some small improvements and fixes to the optimizer
+    * some register allocation fixes
+    * some fpuvaroffset fixes in the unary minus node
+    * push/popusedregisters is now called rg.save/restoreusedregisters and
+      (for i386) uses temps instead of push/pop's when using -Op3 (that code is
+      also better optimizable)
+    * fixed and optimized register saving/restoring for new/dispose nodes
+    * LOC_FPU locations now also require their "register" field to be set to
+      R_ST, not R_ST0 (the latter is used for LOC_CFPUREGISTER locations only)
+    - list field removed of the tnode class because it's not used currently
+      and can cause hard-to-find bugs
+
+  Revision 1.17  2002/03/28 16:07:52  armin
+  + initialize threadvars defined local in units
+
+  Revision 1.16  2002/03/04 19:10:12  peter
+    * removed compiler warnings
+
+  Revision 1.15  2002/01/24 18:25:53  peter
+   * implicit result variable generation for assembler routines
+   * removed m_tp modeswitch, use m_tp7 or not(m_fpc) instead
+
+  Revision 1.14  2002/01/19 14:21:17  peter
+    * fixed init/final for value parameters
+
+}

compiler/sparc/cpunode.pas

@@ -0,0 +1,44 @@
+{*****************************************************************************}
+{ File                   : cpunode.pas                                        }
+{ Author                 : Mazen NEIFER                                       }
+{ Project                : Free Pascal Compiler (FPC)                         }
+{ Creation date          : 2002\26\26                                         }
+{ Last modification date : 2002\07\14                                         }
+{ Licence                : GPL                                                }
+{ Bug report             : [email protected]                        }
+{*****************************************************************************}
+{
+    $Id$
+    Copyright (c) 2000 by Florian Klaempfl
+
+    Includes the iSPARC code generator
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************}
+UNIT cpunode;
+{$INCLUDE fpcdefs.inc}
+INTERFACE
+{This unit is used to define the specific CPU implementations. All needed
+actions are included in the INITALIZATION part of these units. This explains
+the behaviour of such a unit having just a USES clause!}
+IMPLEMENTATION
+USES
+  ncgbas,ncgflw,ncgcnv,ncgld,ncgmem,ncgcon,{ncgset,}
+  naddcpu,{n386cal,n386con,n386cnv,n386flw,n386mat,n386mem,}
+  {n386set,n386inl,n386opt,}
+  { this not really a node }
+  {nSPARCobj,} rgcpu;
+END.

compiler/sparc/cpuswtch.pas

@@ -0,0 +1,187 @@
+{
+    $Id$
+    Copyright (c) 1998-2000 by Florian Klaempfl, Pierre Muller
+
+    interprets the commandline options which are i386 specific
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+unit cpuswtch;
+
+{$INCLUDE fpcdefs.inc}
+
+interface
+
+uses
+  options;
+
+type
+  toption386=class(toption)
+    procedure interpret_proc_specific_options(const opt:string);override;
+  end;
+
+implementation
+
+uses
+  cutils,globtype,systems,globals;
+
+procedure toption386.interpret_proc_specific_options(const opt:string);
+var
+  j     : longint;
+  More  : string;
+begin
+  More:=Upper(copy(opt,3,length(opt)-2));
+  case opt[2] of
+   'O' : Begin
+           j := 3;
+           While (j <= Length(Opt)) Do
+             Begin
+               case opt[j] of
+                 '-' :
+                   begin
+                     initglobalswitches:=initglobalswitches-[cs_optimize,cs_fastoptimize,cs_slowoptimize,cs_littlesize,
+                       cs_regalloc,cs_uncertainopts];
+                     FillChar(ParaAlignment,sizeof(ParaAlignment),0);
+                   end;
+                 'a' :
+                   begin
+                     UpdateAlignmentStr(Copy(Opt,j+1,255),ParaAlignment);
+                     j:=length(Opt);
+                   end;
+                 'g' : initglobalswitches:=initglobalswitches+[cs_littlesize];
+                 'G' : initglobalswitches:=initglobalswitches-[cs_littlesize];
+                 'r' :
+                   begin
+                     initglobalswitches:=initglobalswitches+[cs_regalloc];
+                     Simplify_ppu:=false;
+                   end;
+                 'u' : initglobalswitches:=initglobalswitches+[cs_uncertainopts];
+                 '1' : initglobalswitches:=initglobalswitches-[cs_fastoptimize,cs_slowoptimize]+[cs_optimize];
+                 '2' : initglobalswitches:=initglobalswitches-[cs_slowoptimize]+[cs_optimize,cs_fastoptimize];
+                 '3' : initglobalswitches:=initglobalswitches+[cs_optimize,cs_fastoptimize,cs_slowoptimize];
+                 'p' :
+                   Begin
+                     If j < Length(Opt) Then
+                       Begin
+                         Case opt[j+1] Of
+                           '1': initoptprocessor := Class386;
+                           '2': initoptprocessor := ClassP5;
+                           '3': initoptprocessor := ClassP6
+                           Else IllegalPara(Opt)
+                         End;
+                         Inc(j);
+                       End
+                     Else IllegalPara(opt)
+                   End;
+{$ifdef USECMOV}
+                 's' :
+                   Begin
+                     If j < Length(Opt) Then
+                       Begin
+                         Case opt[j+1] Of
+                           '3': initspecificoptprocessor:=ClassP6
+                           Else IllegalPara(Opt)
+                         End;
+                         Inc(j);
+                       End
+                     Else IllegalPara(opt)
+                   End
+{$endif USECMOV}
+                 else IllegalPara(opt);
+               End;
+               Inc(j)
+             end;
+         end;
+   'R' : begin
+           if More='ATT' then
+            initasmmode:=asmmode_i386_att
+           else
+            if More='INTEL' then
+             initasmmode:=asmmode_i386_intel
+           else
+            if More='DIRECT' then
+             initasmmode:=asmmode_i386_direct
+           else
+            IllegalPara(opt);
+         end;
+  else
+   IllegalPara(opt);
+  end;
+end;
+
+
+initialization
+  coption:=toption386;
+end.
+{
+  $Log$
+  Revision 1.1  2002-08-22 08:30:50  mazen
+  first insertion 2002\08\22
+
+  Revision 1.4  2001/07/01 20:16:20  peter
+    * alignmentinfo record added
+    * -Oa argument supports more alignment settings that can be specified
+      per type: PROC,LOOP,VARMIN,VARMAX,CONSTMIN,CONSTMAX,RECORDMIN
+      RECORDMAX,LOCALMIN,LOCALMAX. It is possible to set the mimimum
+      required alignment and the maximum usefull alignment. The final
+      alignment will be choosen per variable size dependent on these
+      settings
+
+  Revision 1.3  2001/05/12 12:11:31  peter
+    * simplify_ppu is now the default, a recompile of the compiler now
+      only compiles pp.pas
+
+  Revision 1.2  2000/12/23 19:46:49  peter
+    * object to class conversion
+    * more verbosity for -vt and -vd
+    * -i options can be put after eachother so the Makefiles only need
+      to call fpc once for all info (will be twice as the first one will
+      be to check the version if fpc supports multiple info)
+
+  Revision 1.1  2000/11/30 22:42:50  florian
+  * renamed
+
+  Revision 1.1  2000/11/30 22:21:56  florian
+    * moved to i386
+
+  Revision 1.6  2000/10/24 10:40:53  jonas
+    + register renaming ("fixes" bug1088)
+    * changed command line options meanings for optimizer:
+        O2 now means peepholopts, CSE and register renaming in 1 pass
+        O3 is the same, but repeated until no further optimizations are
+          possible or until 5 passes have been done (to avoid endless loops)
+    * changed aopt386 so it does this looping
+    * added some procedures from csopt386 to the interface because they're
+      used by rropt386 as well
+    * some changes to csopt386 and daopt386 so that newly added instructions
+      by the CSE get optimizer info (they were simply skipped previously),
+      this fixes some bugs
+
+  Revision 1.5  2000/09/24 15:06:20  peter
+    * use defines.inc
+
+  Revision 1.4  2000/08/27 16:11:51  peter
+    * moved some util functions from globals,cobjects to cutils
+    * splitted files into finput,fmodule
+
+  Revision 1.3  2000/07/27 13:03:36  jonas
+    * release alignopts
+
+  Revision 1.2  2000/07/13 11:32:44  michael
+  + removed logs
+
+}

compiler/sparc/cputarg.pas

@@ -0,0 +1,76 @@
+{
+    $Id$
+    Copyright (c) 2001 by Peter Vreman
+
+    Includes the i386 dependent target units
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+unit cputarg;
+
+{$INCLUDE fpcdefs.inc}
+
+interface
+
+
+implementation
+
+    uses
+      systems { prevent a syntax error when nothing is included }
+
+{**************************************
+             Targets
+**************************************}
+
+    {$ifndef NOTARGETLINUX}
+      ,t_linux
+    {$endif}
+    {$ifndef NOTARGETFREEBSD}
+      ,t_fbsd
+    {$endif}
+    {$ifndef NOTARGETSUNOS}
+      ,t_sunos
+    {$endif}
+    {$ifndef NOTARGETBEOS}
+      ,t_beos
+    {$endif}
+
+{**************************************
+             Assemblers
+**************************************}
+
+      ,CpuGas
+      ,ogcoff
+      ,ogelf
+      ;
+
+end.
+{
+  $Log$
+  Revision 1.1  2002-08-22 08:30:50  mazen
+  first insertion 2002\08\22
+
+  Revision 1.3  2002/03/28 20:48:04  carl
+  - remove go32v1 support
+
+  Revision 1.2  2001/06/03 15:12:47  peter
+    * t_beos target inclusion
+
+  Revision 1.1  2001/04/18 22:02:01  peter
+    * registration of targets and assemblers
+
+}

compiler/sparc/naddcpu.pas

@@ -0,0 +1,515 @@
+{*****************************************************************************}
+{ File                   : naddcpu.pas                                        }
+{ Author                 : Mazen NEIFER                                       }
+{ Project                : Free Pascal Compiler (FPC)                         }
+{ Creation date          : 2002\07\14                                         }
+{ Last modification date : 2002\07\26                                         }
+{ Licence                : GPL                                                }
+{ Bug report             : [email protected]                        }
+{*****************************************************************************}
+{
+    $Id$
+    Copyright (c) 2000-2002 by Florian Klaempfl
+
+    Code generation for add nodes on the i386
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; IF not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************}
+UNIT naddcpu;
+{$INCLUDE fpcdefs.inc}
+INTERFACE
+USES
+  node,nadd,cpubase,cginfo;
+TYPE
+  TSparcAddNode=CLASS(TAddNode)
+    PROCEDURE pass_2;OVERRIDE;
+  PRIVATE
+    FUNCTION GetResFlags(unsigned:Boolean):TResFlags;
+    PROCEDURE left_must_be_reg(OpSize:TOpSize;NoSwap:Boolean);
+    PROCEDURE emit_generic_code(op:TAsmOp;OpSize:TOpSize;unsigned,extra_not,mboverflow:Boolean);
+    PROCEDURE emit_op_right_left(op:TAsmOp;OpSize:TOpsize);
+    PROCEDURE set_result_location(cmpOp,unsigned:Boolean);
+  END;
+IMPLEMENTATION
+USES
+  globtype,systems,
+  cutils,verbose,globals,
+  symconst,symdef,paramgr,
+  aasmbase,aasmtai,aasmcpu,defbase,htypechk,
+  cgbase,pass_2,regvars,
+  cpupara,
+  ncon,nset,
+  cga,ncgutil,tgobj,rgobj,rgcpu,cgobj,cg64f32;
+CONST
+  opsize_2_cgSize:ARRAY[S_B..S_L]OF TCgSize=(OS_8,OS_16,OS_32);
+FUNCTION TSparcAddNode.GetResFlags(unsigned:Boolean):TResFlags;
+  BEGIN
+    CASE NodeType OF
+      equaln:
+        GetResFlags:=F_E;
+      unequaln:
+        GetResFlags:=F_NE;
+      ELSE
+        IF NOT(unsigned)
+        THEN
+          BEGIN
+            IF nf_swaped IN flags
+            THEN
+              CASE NodeType OF
+                ltn:
+                  GetResFlags:=F_G;
+                lten:
+                  GetResFlags:=F_GE;
+                gtn:
+                  GetResFlags:=F_L;
+                gten:
+                  GetResFlags:=F_LE;
+              END
+            ELSE
+              CASE NodeType OF
+                ltn:
+                  GetResFlags:=F_L;
+                lten:
+                  GetResFlags:=F_LE;
+                gtn:
+                  GetResFlags:=F_G;
+                gten:
+                  GetResFlags:=F_GE;
+              END;
+          END
+        ELSE
+          BEGIN
+            IF nf_swaped IN Flags
+            THEN
+              CASE NodeType OF
+                ltn:
+                  GetResFlags:=F_A;
+                lten:
+                  GetResFlags:=F_AE;
+                gtn:
+                  GetResFlags:=F_B;
+                gten:
+                  GetResFlags:=F_BE;
+              END
+            ELSE
+              CASE NodeType OF
+                ltn:
+                  GetResFlags:=F_B;
+                lten:
+                  GetResFlags:=F_BE;
+                gtn:
+                  GetResFlags:=F_A;
+                gten:
+                  GetResFlags:=F_AE;
+              END;
+          END;
+    END;
+  END;
+PROCEDURE TSparcAddNode.left_must_be_reg(OpSize:TOpSize;NoSwap:Boolean);
+  BEGIN
+    IF(left.location.loc<>LOC_REGISTER)
+    THEN{left location is not a register}
+      BEGIN
+        IF(NOT NoSwap)AND(right.location.loc=LOC_REGISTER)
+        THEN{right is register so we can swap the locations}
+          BEGIN
+            location_swap(left.location,right.location);
+            toggleflag(nf_swaped);
+          END
+        ELSE
+          BEGIN
+{maybe we can reuse a constant register when the operation is a comparison that
+doesn't change the value of the register}
+            location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],(nodetype IN [ltn,lten,gtn,gten,equaln,unequaln]));
+          END;
+      END;
+   END;
+PROCEDURE TSparcAddNode.emit_generic_code(op:TAsmOp;OpSize:TOpSize;unsigned,extra_not,mboverflow:Boolean);
+  VAR
+    power:LongInt;
+    hl4:TAsmLabel;
+  BEGIN
+    { at this point, left.location.loc should be LOC_REGISTER }
+    IF right.location.loc=LOC_REGISTER
+    THEN
+      BEGIN
+           { right.location is a LOC_REGISTER }
+           { when swapped another result register }
+        IF(nodetype=subn)AND(nf_swaped IN flags)
+        THEN
+          BEGIN
+            IF extra_not
+            THEN
+              emit_reg(A_NOT,S_L,left.location.register);
+              emit_reg_reg(op,opsize,left.location.register,right.location.register);
+            { newly swapped also set swapped flag }
+            location_swap(left.location,right.location);
+            toggleflag(nf_swaped);
+          END
+        ELSE
+          BEGIN
+            IF extra_not
+            THEN
+              emit_reg(A_NOT,S_L,right.location.register);
+            emit_reg_reg(op,opsize,right.location.register,left.location.register);
+          END;
+      END
+    ELSE
+      BEGIN
+        { right.location is not a LOC_REGISTER }
+        IF(nodetype=subn)AND(nf_swaped IN flags)
+        THEN
+          BEGIN
+            IF extra_not
+            THEN
+              emit_reg(A_NOT,opsize,left.location.register);
+//          rg.getexplicitregisterint(exprasmlist,R_EDI);
+//          cg.a_load_loc_reg(exprasmlist,right.location,R_EDI);
+//          emit_reg_reg(op,opsize,left.location.register,R_EDI);
+//          emit_reg_reg(A_MOV,opsize,R_EDI,left.location.register);
+//          rg.ungetregisterint(exprasmlist,R_EDI);
+          END
+        ELSE
+          BEGIN
+            { Optimizations when right.location is a constant value }
+            IF(op=A_CMP)AND(nodetype IN [equaln,unequaln])AND(right.location.loc=LOC_CONSTANT)AND(right.location.value=0)
+            THEN
+              BEGIN
+//                emit_reg_reg(A_TEST,opsize,left.location.register,left.location.register);
+              END
+            ELSE IF(op=A_ADD)AND(right.location.loc=LOC_CONSTANT)AND(right.location.value=1)AND NOT(cs_check_overflow in aktlocalswitches)
+            THEN
+              BEGIN
+                emit_reg(A_INC,opsize,left.location.register);
+              END
+            ELSE IF(op=A_SUB)AND(right.location.loc=LOC_CONSTANT)AND(right.location.value=1)AND NOT(cs_check_overflow in aktlocalswitches)
+            THEN
+              BEGIN
+                emit_reg(A_DEC,opsize,left.location.register);
+              END
+            ELSE IF(op=A_SMUL)AND(right.location.loc=LOC_CONSTANT)AND(ispowerof2(right.location.value,power))AND NOT(cs_check_overflow in aktlocalswitches)
+            THEN
+              BEGIN
+                emit_const_reg(A_SLL,opsize,power,left.location.register);
+              END
+            ELSE
+              BEGIN
+                IF extra_not
+                THEN
+                  BEGIN
+//                  rg.getexplicitregisterint(exprasmlist,R_EDI);
+//                  cg.a_load_loc_reg(exprasmlist,right.location,R_EDI);
+//                  emit_reg(A_NOT,S_L,R_EDI);
+//                  emit_reg_reg(A_AND,S_L,R_EDI,left.location.register);
+//                  rg.ungetregisterint(exprasmlist,R_EDI);
+                  END
+                ELSE
+                  BEGIN
+                    emit_op_right_left(op,opsize);
+                  END;
+              END;
+          END;
+      END;
+    { only in case of overflow operations }
+    { produce overflow code }
+    { we must put it here directly, because sign of operation }
+    { is in unsigned VAR!!                                   }
+    IF mboverflow
+    THEN
+      BEGIN
+        IF cs_check_overflow IN aktlocalswitches
+        THEN
+          BEGIN
+            getlabel(hl4);
+            IF unsigned
+            THEN
+              emitjmp(C_NB,hl4)
+            ELSE
+              emitjmp(C_NO,hl4);
+            cg.a_call_name(exprasmlist,'FPC_OVERFLOW');
+            cg.a_label(exprasmlist,hl4);
+          END;
+       END;
+  END;
+PROCEDURE TSparcAddNode.emit_op_right_left(op:TAsmOp;OpSize:TOpsize);
+  BEGIN
+    {left must be a register}
+    CASE right.location.loc OF
+      LOC_REGISTER,LOC_CREGISTER:
+        exprasmlist.concat(taicpu.op_reg_reg(op,opsize,right.location.register,left.location.register));
+      LOC_REFERENCE,LOC_CREFERENCE :
+        exprasmlist.concat(taicpu.op_ref_reg(op,opsize,right.location.reference,left.location.register));
+      LOC_CONSTANT:
+        exprasmlist.concat(taicpu.op_const_reg(op,opsize,right.location.value,left.location.register));
+    ELSE
+      InternalError(200203232);
+    END;
+  END;
+PROCEDURE TSparcAddNode.set_result_location(cmpOp,unsigned:Boolean);
+  BEGIN
+    IF cmpOp
+    THEN
+      BEGIN
+        location_reset(location,LOC_FLAGS,OS_NO);
+        location.resflags:=GetResFlags(unsigned);
+      END
+    ELSE
+      location_copy(location,left.location);
+  END;
+PROCEDURE TSparcAddNode.pass_2;
+{is also being used for "xor", and "mul", "sub", or and comparative operators}
+  VAR
+    popeax,popedx,pushedfpu,mboverflow,cmpop:Boolean;
+    op:TAsmOp;
+    power:LongInt;
+    OpSize:TOpSize;
+    unsigned:Boolean;{true, if unsigned types are compared}
+         { is_in_dest if the result is put directly into }
+         { the resulting refernce or varregister }
+         {is_in_dest : boolean;}
+         { true, if for sets subtractions the extra not should generated }
+    extra_not:Boolean;
+  BEGIN
+{to make it more readable, string and set (not smallset!) have their own
+procedures }
+    CASE left.resulttype.def.deftype OF
+      orddef:
+        BEGIN
+          IF is_boolean(left.resulttype.def)AND is_boolean(right.resulttype.def)
+          THEN{handling boolean expressions}
+            BEGIN
+              InternalError(20020726);//second_addboolean;
+              exit;
+            END
+          ELSE IF is_64bitint(left.resulttype.def)
+          THEN{64bit operations}
+            BEGIN
+              InternalError(20020726);//second_add64bit;
+              exit;
+            END;
+        END;
+      stringdef:
+        BEGIN
+          InternalError(20020726);//second_addstring;
+          exit;
+        END;
+      setdef:
+        BEGIN
+          {normalsets are already handled in pass1}
+          IF(tsetdef(left.resulttype.def).settype<>smallset)
+          THEN
+            internalerror(200109041);
+          InternalError(20020726);//second_addsmallset;
+          exit;
+        END;
+      arraydef :
+        BEGIN
+{$ifdef SUPPORT_MMX}
+               if is_mmx_able_array(left.resulttype.def) then
+                begin
+                  InternalError(20020726);//second_addmmx;
+                  exit;
+                end;
+{$endif SUPPORT_MMX}
+        END;
+      floatdef :
+        BEGIN
+          InternalError(20020726);//second_addfloat;
+          exit;
+        END;
+    END;
+{defaults}
+    {is_in_dest:=false;}
+    extra_not:=false;
+    mboverflow:=false;
+    cmpop:=false;
+    unsigned:=not(is_signed(left.resulttype.def))or not(is_signed(right.resulttype.def));
+    opsize:=def_opsize(left.resulttype.def);
+    //pass_left_and_right(pushedfpu);
+    IF(left.resulttype.def.deftype=pointerdef)OR
+      (right.resulttype.def.deftype=pointerdef) or
+      (is_class_or_interface(right.resulttype.def) and is_class_or_interface(left.resulttype.def)) or
+      (left.resulttype.def.deftype=classrefdef) or
+      (left.resulttype.def.deftype=procvardef) or
+      ((left.resulttype.def.deftype=enumdef)and(left.resulttype.def.size=4)) or
+      ((left.resulttype.def.deftype=orddef)and(torddef(left.resulttype.def).typ in [s32bit,u32bit])) or
+      ((right.resulttype.def.deftype=orddef)and(torddef(right.resulttype.def).typ in [s32bit,u32bit]))
+    THEN
+      BEGIN
+        CASE NodeType OF
+          addn:
+            BEGIN
+              op:=A_ADD;
+              mboverflow:=true;
+            END;
+          muln:
+            BEGIN
+              IF unsigned
+              THEN
+                op:=A_UMUL
+              ELSE
+                op:=A_SMUL;
+              mboverflow:=true;
+            END;
+          subn:
+            BEGIN
+              op:=A_SUB;
+              mboverflow:=true;
+            END;
+          ltn,lten,
+          gtn,gten,
+          equaln,unequaln:
+            BEGIN
+              op:=A_CMP;
+              cmpop:=true;
+            END;
+          xorn:
+            op:=A_XOR;
+          orn:
+            op:=A_OR;
+          andn:
+            op:=A_AND;
+        ELSE
+          CGMessage(type_e_mismatch);
+        END;
+   { filter MUL, which requires special handling }
+        IF op=A_UMUL
+        THEN
+          BEGIN
+            popeax:=false;
+            popedx:=false;
+               { here you need to free the symbol first }
+               { left.location and right.location must }
+               { only be freed when they are really released,  }
+               { because the optimizer NEEDS correct regalloc  }
+               { info!!! (JM)                                  }
+               { the location.register will be filled in later (JM) }
+            location_reset(location,LOC_REGISTER,OS_INT);
+{$IfNDef NoShlMul}
+            IF right.nodetype=ordconstn
+            THEN
+              swapleftright;
+            IF(left.nodetype=ordconstn)and
+              ispowerof2(tordconstnode(left).value, power)and
+              not(cs_check_overflow in aktlocalswitches)
+            THEN
+              BEGIN
+                   { This release will be moved after the next }
+                   { instruction by the optimizer. No need to  }
+                   { release left.location, since it's a   }
+                   { constant (JM)                             }
+                location_release(exprasmlist,right.location);
+                location.register:=rg.getregisterint(exprasmlist);
+                cg.a_load_loc_reg(exprasmlist,right.location,location.register);
+                cg.a_op_const_reg(exprasmlist,OP_SHL,power,location.register);
+              END
+            ELSE
+              BEGIN
+{$EndIf NoShlMul}
+{In SPARC there is no push/pop mechanism. There is a windowing mechanism using
+ SAVE and RESTORE instructions.}
+                //regstopush:=all_registers;
+                //remove_non_regvars_from_loc(right.location,regstopush);
+                //remove_non_regvars_from_loc(left.location,regstopush);
+                {left.location can be R_EAX !!!}
+//              rg.GetExplicitRegisterInt(exprasmlist,R_EDI);
+                {load the left value}
+//                cg.a_load_loc_reg(exprasmlist,left.location,R_EDI);
+//                location_release(exprasmlist,left.location);
+                  { allocate EAX }
+//                if R_EAX in rg.unusedregsint then
+//                  exprasmList.concat(tai_regalloc.Alloc(R_EAX));
+                  { load he right value }
+//                cg.a_load_loc_reg(exprasmlist,right.location,R_EAX);
+//                location_release(exprasmlist,right.location);
+                  { allocate EAX if it isn't yet allocated (JM) }
+//                if (R_EAX in rg.unusedregsint) then
+//                  exprasmList.concat(tai_regalloc.Alloc(R_EAX));
+                  { also allocate EDX, since it is also modified by }
+                  { a mul (JM)                                      }
+{                if R_EDX in rg.unusedregsint then
+                    exprasmList.concat(tai_regalloc.Alloc(R_EDX));
+                  emit_reg(A_MUL,S_L,R_EDI);
+                  rg.ungetregisterint(exprasmlist,R_EDI);
+                  if R_EDX in rg.unusedregsint then
+                    exprasmList.concat(tai_regalloc.DeAlloc(R_EDX));
+                  if R_EAX in rg.unusedregsint then
+                    exprasmList.concat(tai_regalloc.DeAlloc(R_EAX));
+                  location.register:=rg.getregisterint(exprasmlist);
+                  emit_reg_reg(A_MOV,S_L,R_EAX,location.register);
+                  if popedx then
+                   emit_reg(A_POP,S_L,R_EDX);
+                  if popeax then
+                   emit_reg(A_POP,S_L,R_EAX);}
+{$IfNDef NoShlMul}
+                End;
+{$endif NoShlMul}
+               location_freetemp(exprasmlist,left.location);
+               location_freetemp(exprasmlist,right.location);
+               exit;
+             end;
+
+            { Convert flags to register first }
+            if (left.location.loc=LOC_FLAGS) then
+             location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],false);
+            if (right.location.loc=LOC_FLAGS) then
+             location_force_reg(exprasmlist,right.location,opsize_2_cgsize[opsize],false);
+
+            left_must_be_reg(OpSize,false);
+            emit_generic_code(op,opsize,unsigned,extra_not,mboverflow);
+            location_freetemp(exprasmlist,right.location);
+            location_release(exprasmlist,right.location);
+            if cmpop and
+               (left.location.loc<>LOC_CREGISTER) then
+             begin
+               location_freetemp(exprasmlist,left.location);
+               location_release(exprasmlist,left.location);
+             end;
+            set_result_location(cmpop,unsigned);
+          end
+
+         { 8/16 bit enum,char,wchar types }
+{         else
+          if ((left.resulttype.def.deftype=orddef) and
+              (torddef(left.resulttype.def).typ in [uchar,uwidechar])) or
+             ((left.resulttype.def.deftype=enumdef) and
+              ((left.resulttype.def.size=1) or
+               (left.resulttype.def.size=2))) then
+           begin
+             case nodetype of
+               ltn,lten,gtn,gten,
+               equaln,unequaln :
+                 cmpop:=true;
+               else
+                 CGMessage(type_e_mismatch);
+             end;
+             left_must_be_reg(opsize,false);
+             emit_op_right_left(A_CMP,opsize);
+             location_freetemp(exprasmlist,right.location);
+             location_release(exprasmlist,right.location);
+             if left.location.loc<>LOC_CREGISTER then
+              begin
+                location_freetemp(exprasmlist,left.location);
+                location_release(exprasmlist,left.location);
+              end;
+             set_result_location(true,true);
+           end
+         else
+           CGMessage(type_e_mismatch);}
+      end;
+BEGIN
+  cAddNode:=TSparcAddNode;
+END.

compiler/sparc/ncgcall.pas

@@ -0,0 +1,1584 @@
+{*****************************************************************************}
+{ File                   : ncgcall.pas                                        }
+{ Author                 : Mazen NEIFER                                       }
+{ Project                : Free Pascal Compiler (FPC)                         }
+{ Creation date          : 2002\26\26                                         }
+{ Last modification date : 2002\07\01                                         }
+{ Licence                : GPL                                                }
+{ Bug report             : [email protected]                        }
+{*****************************************************************************}
+{
+    $Id$
+    Copyright (c) 1998-2002 by Florian Klaempfl
+
+    Generate SPARC assembler for in call nodes
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published bymethodpointer
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************}
+UNIT ncgcall;
+{$INCLUDE fpcdefs.inc}{$MACRO ON}
+INTERFACE
+{$DEFINE R_ESI:=R_I0}
+{$DEFINE R_EDI:=R_O0}
+{$DEFINE R_CS:=R_PSR}
+{$DEFINE R_ST:=R_PSR}
+{$DEFINE A_LEA:=A_NONE}
+{$DEFINE A_FSTP:=A_NONE}
+USES
+  symdef,node,ncal;
+TYPE
+  tSPARCcallparanode=CLASS(tcallparanode)
+    PROCEDURE secondcallparan(defcoll : TParaItem;
+    push_from_left_to_right,inlined,is_cdecl : boolean;
+    para_alignment,para_offset : longint);override;
+  end;
+  tSPARCcallnode = class(tcallnode)
+    PROCEDURE pass_2;override;
+  end;
+  tSPARCprocinlinenode = class(tprocinlinenode)
+    PROCEDURE pass_2;override;
+  end;
+IMPLEMENTATION
+USES
+  globtype,systems,
+  cutils,verbose,globals,
+  symconst,symbase,symsym,symtable,types,
+{$ifdef GDB}
+  {$ifdef delphi}
+      sysutils,
+  {$else}
+      strings,
+  {$endif}
+      gdb,
+{$endif GDB}
+      cginfo,cgbase,pass_2,
+      cpubase,aasm,tainst,
+      nmem,nld,ncnv,
+      ncgutil,cga,cgobj,tgobj,regvars,rgobj,rgcpu,cg64f32,cgcpu;
+
+{*****************************************************************************
+                             TSPARCCALLPARANODE
+*****************************************************************************}
+
+    PROCEDURE tSPARCcallparanode.secondcallparan(defcoll : TParaItem;
+                push_from_left_to_right,inlined,is_cdecl : boolean;para_alignment,para_offset : longint);
+
+      PROCEDURE maybe_push_high;
+        begin
+           { open array ? }
+           { defcoll.data can be nil for read/write }
+           if assigned(defcoll.paratype.def) and
+              assigned(hightree) then
+            begin
+              secondpass(hightree);
+              { this is a longint anyway ! }
+              push_value_para(hightree,inlined,false,para_offset,4);
+            end;
+        end;
+
+      var
+         otlabel,oflabel : tasmlabel;
+         { temporary variables: }
+         tempdeftype : tdeftype;
+         tmpreg : tregister;
+         href   : treference;
+
+      begin
+         { set default para_alignment to target_info.stackalignment }
+         if para_alignment=0 then
+          para_alignment:=aktalignment.paraalign;
+
+         { push from left to right if specified }
+         if push_from_left_to_right and assigned(right) then
+          begin
+            if (nf_varargs_para in flags) then
+              tcallparanode(right).secondcallparan(defcoll,push_from_left_to_right,
+                                                   inlined,is_cdecl,para_alignment,para_offset)
+            else
+              tcallparanode(right).secondcallparan(TParaItem(defcoll.next),push_from_left_to_right,
+                                                   inlined,is_cdecl,para_alignment,para_offset);
+          end;
+
+         otlabel:=truelabel;
+         oflabel:=falselabel;
+         getlabel(truelabel);
+         getlabel(falselabel);
+         secondpass(left);
+         { handle varargs first, because defcoll is not valid }
+         if (nf_varargs_para in flags) then
+           begin
+             if push_addr_param(left.resulttype.def) then
+               begin
+                 inc(pushedparasize,4);
+                 cg.a_paramaddr_ref(exprasmlist,left.location.reference,-1);
+                 location_release(exprasmlist,left.location);
+               end
+             else
+               push_value_para(left,inlined,is_cdecl,para_offset,para_alignment);
+           end
+         { filter array constructor with c styled args }
+         else if is_array_constructor(left.resulttype.def) and (nf_cargs in left.flags) then
+           begin
+             { nothing, everything is already pushed }
+           end
+         { in codegen.handleread.. defcoll.data is set to nil }
+         else if assigned(defcoll.paratype.def) and
+                 (defcoll.paratype.def.deftype=formaldef) then
+           begin
+              { allow passing of a constant to a const formaldef }
+              if (defcoll.paratyp=vs_const) and
+                 (left.location.loc=LOC_CONSTANT) then
+                location_force_mem(exprasmlist,left.location);
+
+              { allow @var }
+              inc(pushedparasize,4);
+              if (left.nodetype=addrn) and
+                 (not(nf_procvarload in left.flags)) then
+                begin
+                  if inlined then
+                    begin
+                       reference_reset_base(href,procinfo^.framepointer,para_offset-pushedparasize);
+                       cg.a_load_loc_ref(exprasmlist,left.location,href);
+                    end
+                  else
+                    cg.a_param_loc(exprasmlist,left.location,-1);
+                  location_release(exprasmlist,left.location);
+                end
+              else
+                begin
+                   if not(left.location.loc in [LOC_CREFERENCE,LOC_REFERENCE]) then
+                     CGMessage(type_e_mismatch)
+                   else
+                     begin
+                       if inlined then
+                         begin
+                           tmpreg:=cg.get_scratch_reg_address(exprasmlist);
+                           cg.a_loadaddr_ref_reg(exprasmlist,left.location.reference,tmpreg);
+                           reference_reset_base(href,procinfo^.framepointer,para_offset-pushedparasize);
+                           cg.a_load_reg_ref(exprasmlist,OS_ADDR,tmpreg,href);
+                           cg.free_scratch_reg(exprasmlist,tmpreg);
+                         end
+                       else
+                         cg.a_paramaddr_ref(exprasmlist,left.location.reference,-1);
+                       location_release(exprasmlist,left.location);
+                     end;
+                end;
+           end
+         { handle call by reference parameter }
+         else if (defcoll.paratyp in [vs_var,vs_out]) then
+           begin
+              { get temp for constants }
+              if left.location.loc=LOC_CONSTANT then
+               begin
+                 tg.gettempofsizereference(exprasmlist,left.resulttype.def.size,href);
+                 cg.a_load_loc_ref(exprasmlist,left.location,href);
+                 location_reset(left.location,LOC_REFERENCE,def_cgsize(left.resulttype.def));
+                 left.location.reference:=href;
+               end;
+
+              if (left.location.loc<>LOC_REFERENCE) then
+               begin
+                 { passing self to a var parameter is allowed in
+                   TP and delphi }
+                 if not((left.location.loc=LOC_CREFERENCE) and
+                        (left.nodetype=selfn)) then
+                  internalerror(200106041);
+               end;
+              maybe_push_high;
+              if (defcoll.paratyp=vs_out) and
+                 assigned(defcoll.paratype.def) and
+                 not is_class(defcoll.paratype.def) and
+                 defcoll.paratype.def.needs_inittable then
+                cg.g_finalize(exprasmlist,defcoll.paratype.def,left.location.reference,false);
+              inc(pushedparasize,4);
+              if inlined then
+                begin
+                   tmpreg:=cg.get_scratch_reg_address(exprasmlist);
+                   cg.a_loadaddr_ref_reg(exprasmlist,left.location.reference,tmpreg);
+                   reference_reset_base(href,procinfo^.framepointer,para_offset-pushedparasize);
+                   cg.a_load_reg_ref(exprasmlist,OS_ADDR,tmpreg,href);
+                   cg.free_scratch_reg(exprasmlist,tmpreg);
+                end
+              else
+                cg.a_paramaddr_ref(exprasmlist,left.location.reference,-1);
+              location_release(exprasmlist,left.location);
+           end
+         else
+           begin
+              tempdeftype:=resulttype.def.deftype;
+              if tempdeftype=filedef then
+               CGMessage(cg_e_file_must_call_by_reference);
+              { open array must always push the address, this is needed to
+                also push addr of small open arrays and with cdecl functions (PFV) }
+              if (
+                  assigned(defcoll.paratype.def) and
+                  (is_open_array(defcoll.paratype.def) or
+                   is_array_of_const(defcoll.paratype.def))
+                 ) or
+                 (
+                  push_addr_param(resulttype.def) and
+                  not is_cdecl
+                 ) then
+                begin
+                   if not(left.location.loc in [LOC_CREFERENCE,LOC_REFERENCE]) then
+                    begin
+                      { allow passing nil to a procvardef (methodpointer) }
+                      if (left.nodetype=typeconvn) and
+                         (left.resulttype.def.deftype=procvardef) and
+                         (ttypeconvnode(left).left.nodetype=niln) then
+                       begin
+                         tg.gettempofsizereference(exprasmlist,tcgsize2size[left.location.size],href);
+                         cg.a_load_loc_ref(exprasmlist,left.location,href);
+                         location_reset(left.location,LOC_REFERENCE,left.location.size);
+                         left.location.reference:=href;
+                       end
+                      else
+                       internalerror(200204011);
+                    end;
+
+                   maybe_push_high;
+                   inc(pushedparasize,4);
+                   if inlined then
+                     begin
+                        tmpreg:=cg.get_scratch_reg_address(exprasmlist);
+                        cg.a_loadaddr_ref_reg(exprasmlist,left.location.reference,tmpreg);
+                        reference_reset_base(href,procinfo^.framepointer,para_offset-pushedparasize);
+                        cg.a_load_reg_ref(exprasmlist,OS_ADDR,tmpreg,href);
+                        cg.free_scratch_reg(exprasmlist,tmpreg);
+                     end
+                   else
+                     cg.a_paramaddr_ref(exprasmlist,left.location.reference,-1);
+                   location_release(exprasmlist,left.location);
+                end
+              else
+                begin
+                   push_value_para(left,inlined,is_cdecl,
+                     para_offset,para_alignment);
+                end;
+           end;
+         truelabel:=otlabel;
+         falselabel:=oflabel;
+         { push from right to left }
+         if not push_from_left_to_right and assigned(right) then
+          begin
+            if (nf_varargs_para in flags) then
+              tcallparanode(right).secondcallparan(defcoll,push_from_left_to_right,
+                                                   inlined,is_cdecl,para_alignment,para_offset)
+            else
+              tcallparanode(right).secondcallparan(TParaItem(defcoll.next),push_from_left_to_right,
+                                                   inlined,is_cdecl,para_alignment,para_offset);
+          end;
+      end;
+
+
+{*****************************************************************************
+                             TI386CALLNODE
+*****************************************************************************}
+
+    PROCEDURE tSPARCcallnode.pass_2;
+      var
+         regs_to_push : tregisterset;
+         unusedstate: pointer;
+         pushed : tpushedsaved;
+         funcretref,refcountedtemp : treference;
+         tmpreg : tregister;
+         hregister : tregister;
+         oldpushedparasize : longint;
+         { true if ESI must be loaded again after the subroutine }
+         loadesi : boolean;
+         { true if a virtual method must be called directly }
+         no_virtual_call : boolean;
+         { true if we produce a con- or destrutor in a call }
+         is_con_or_destructor : boolean;
+         { true if a constructor is called again }
+         extended_new : boolean;
+         { adress returned from an I/O-error }
+         iolabel : tasmlabel;
+         { lexlevel count }
+         i : longint;
+         { help reference pointer }
+         href : treference;
+         hrefvmt : treference;
+         hp : tnode;
+         pp : tbinarynode;
+         params : tnode;
+         inlined : boolean;
+         inlinecode : tprocinlinenode;
+         store_parast_fixup,
+         para_alignment,
+         para_offset : longint;
+         cgsize : tcgsize;
+         { instruction for alignement correction }
+{        corr : paicpu;}
+         { we must pop this size also after !! }
+{        must_pop : boolean; }
+         pop_size : longint;
+{$ifdef OPTALIGN}
+         pop_esp : boolean;
+         push_size : longint;
+{$endif OPTALIGN}
+         pop_allowed : boolean;
+         release_tmpreg : boolean;
+         constructorfailed : tasmlabel;
+
+      label
+         dont_call;
+
+      begin
+         extended_new:=false;
+         iolabel:=nil;
+         inlinecode:=nil;
+         inlined:=false;
+         loadesi:=true;
+         no_virtual_call:=false;
+         rg.saveunusedstate(unusedstate);
+
+         { if we allocate the temp. location for ansi- or widestrings }
+         { already here, we avoid later a push/pop                    }
+         if is_widestring(resulttype.def) then
+           begin
+             tg.gettempwidestringreference(exprasmlist,refcountedtemp);
+             cg.g_decrrefcount(exprasmlist,resulttype.def,refcountedtemp);
+           end
+         else if is_ansistring(resulttype.def) then
+           begin
+             tg.gettempansistringreference(exprasmlist,refcountedtemp);
+             cg.g_decrrefcount(exprasmlist,resulttype.def,refcountedtemp);
+           end;
+
+         if (procdefinition.proccalloption in [pocall_cdecl,pocall_cppdecl,pocall_stdcall]) then
+          para_alignment:=4
+         else
+          para_alignment:=aktalignment.paraalign;
+
+         if not assigned(procdefinition) then
+          exit;
+
+         { Deciding whether we may still need the parameters happens next (JM) }
+         if assigned(left) then
+           params:=left.getcopy
+         else params := nil;
+
+         if (procdefinition.proccalloption=pocall_inline) then
+           begin
+              inlined:=true;
+              inlinecode:=tprocinlinenode(right);
+              right:=nil;
+              { set it to the same lexical level as the local symtable, becuase
+                the para's are stored there }
+              tprocdef(procdefinition).parast.symtablelevel:=aktprocdef.localst.symtablelevel;
+              if assigned(params) then
+                inlinecode.para_offset:=tg.gettempofsizepersistant(exprasmlist,inlinecode.para_size);
+              store_parast_fixup:=tprocdef(procdefinition).parast.address_fixup;
+              tprocdef(procdefinition).parast.address_fixup:=inlinecode.para_offset;
+{$ifdef extdebug}
+             Comment(V_debug,
+               'inlined parasymtable is at offset '
+               +tostr(tprocdef(procdefinition).parast.address_fixup));
+             exprasmList.concat(Tai_asm_comment.Create(
+               strpnew('inlined parasymtable is at offset '
+               +tostr(tprocdef(procdefinition).parast.address_fixup))));
+{$endif extdebug}
+           end;
+         { only if no proc var }
+         if inlined or
+            not(assigned(right)) then
+           is_con_or_destructor:=(procdefinition.proctypeoption in [potype_constructor,potype_destructor]);
+         { proc variables destroy all registers }
+         if (inlined or
+            (right=nil)) and
+            { virtual methods too }
+            not(po_virtualmethod in procdefinition.procoptions) then
+           begin
+              if (cs_check_io in aktlocalswitches) and
+                 (po_iocheck in procdefinition.procoptions) and
+                 not(po_iocheck in aktprocdef.procoptions) then
+                begin
+                   getaddrlabel(iolabel);
+                   cg.a_label(exprasmlist,iolabel);
+                end
+              else
+                iolabel:=nil;
+
+              { save all used registers }
+              regs_to_push := tprocdef(procdefinition).usedregisters;
+              rg.saveusedregisters(exprasmlist,pushed,regs_to_push);
+
+              { give used registers through }
+              rg.usedinproc:=rg.usedinproc + tprocdef(procdefinition).usedregisters;
+           end
+         else
+           begin
+              regs_to_push := all_registers;
+              rg.saveusedregisters(exprasmlist,pushed,regs_to_push);
+              rg.usedinproc:=all_registers;
+              { no IO check for methods and PROCEDURE variables }
+              iolabel:=nil;
+           end;
+
+         { generate the code for the parameter and push them }
+         oldpushedparasize:=pushedparasize;
+         pushedparasize:=0;
+         pop_size:=0;
+         { no inc esp for inlined PROCEDURE
+           and for objects constructors PM }
+         if inlined or
+            ((procdefinition.proctypeoption=potype_constructor) and
+            { quick'n'dirty check if it is a class or an object }
+             (resulttype.def.deftype=orddef)) then
+           pop_allowed:=false
+         else
+           pop_allowed:=true;
+         if pop_allowed then
+          begin
+          { Old pushedsize aligned on 4 ? }
+            i:=oldpushedparasize and 3;
+            if i>0 then
+             inc(pop_size,4-i);
+          { This parasize aligned on 4 ? }
+            i:=procdefinition.para_size(para_alignment) and 3;
+            if i>0 then
+             inc(pop_size,4-i);
+          { insert the opcode and update pushedparasize }
+          { never push 4 or more !! }
+            pop_size:=pop_size mod 4;
+            if pop_size>0 then
+             begin
+               inc(pushedparasize,pop_size);
+               emit_const_reg(A_SUB,S_L,pop_size,Stack_Pointer_Reg);
+{$ifdef GDB}
+               if (cs_debuginfo in aktmoduleswitches) and
+                  (exprasmList.first=exprasmList.last) then
+                 exprasmList.concat(Tai_force_line.Create);
+{$endif GDB}
+             end;
+          end;
+{$ifdef OPTALIGN}
+         if pop_allowed and (cs_align in aktglobalswitches) then
+           begin
+              pop_esp:=true;
+              push_size:=procdefinition.para_size(para_alignment);
+              { !!!! here we have to take care of return type, self
+                and nested PROCEDUREs
+              }
+              inc(push_size,12);
+              emit_reg_reg(A_MOV,S_L,Stack_Pointer,R_EDI);
+              if (push_size mod 8)=0 then
+                emit_const_reg(A_AND,S_L,$fffffff8,Stack_Pointer)
+              else
+                begin
+                   emit_const_reg(A_SUB,S_L,push_size,Stack_Pointer);
+                   emit_const_reg(A_AND,S_L,$fffffff8,Stack_Pointer);
+                   emit_const_reg(A_SUB,S_L,push_size,Stack_Pointer);
+                end;
+              emit_reg(A_SAVE,S_L,R_EDI);
+           end
+         else
+           pop_esp:=false;
+{$endif OPTALIGN}
+
+         { Push parameters }
+         if assigned(params) then
+           begin
+              { be found elsewhere }
+              if inlined then
+                para_offset:=tprocdef(procdefinition).parast.address_fixup+
+                  tprocdef(procdefinition).parast.datasize
+              else
+                para_offset:=0;
+              if not(inlined) and
+                 assigned(right) then
+                tcallparanode(params).secondcallparan(TParaItem(tabstractprocdef(right.resulttype.def).Para.first),
+                  (po_leftright in procdefinition.procoptions),inlined,
+                  (procdefinition.proccalloption in [pocall_cdecl,pocall_cppdecl]),
+                  para_alignment,para_offset)
+              else
+                tcallparanode(params).secondcallparan(TParaItem(procdefinition.Para.first),
+                  (po_leftright in procdefinition.procoptions),inlined,
+                  (procdefinition.proccalloption in [pocall_cdecl,pocall_cppdecl]),
+                  para_alignment,para_offset);
+           end;
+
+         { Allocate return value for inlined routines }
+         if inlined then
+           inlinecode.retoffset:=tg.gettempofsizepersistant(exprasmlist,Align(resulttype.def.size,aktalignment.paraalign));
+
+         { Allocate return value when returned in argument }
+         if ret_in_param(resulttype.def) then
+           begin
+             if assigned(funcretrefnode) then
+              begin
+                secondpass(funcretrefnode);
+                if codegenerror then
+                 exit;
+                if (funcretrefnode.location.loc<>LOC_REFERENCE) then
+                 internalerror(200204246);
+                funcretref:=funcretrefnode.location.reference;
+              end
+             else
+              begin
+                if inlined then
+                 begin
+                   reference_reset(funcretref);
+                   funcretref.offset:=tg.gettempofsizepersistant(exprasmlist,resulttype.def.size);
+                   funcretref.base:=procinfo^.framepointer;
+{$ifdef extdebug}
+                   Comment(V_debug,'function return value is at offset '
+                                   +tostr(funcretref.offset));
+                   exprasmlist.concat(tai_asm_comment.create(
+                                       strpnew('function return value is at offset '
+                                               +tostr(funcretref.offset))));
+{$endif extdebug}
+                 end
+                else
+                 tg.gettempofsizereference(exprasmlist,resulttype.def.size,funcretref);
+              end;
+
+             { This must not be counted for C code
+               complex return address is removed from stack
+               by function itself !   }
+{$ifdef OLD_C_STACK}
+             inc(pushedparasize,4); { lets try without it PM }
+{$endif not OLD_C_STACK}
+             if inlined then
+               begin
+                  hregister:=cg.get_scratch_reg_address(exprasmlist);
+                  cg.a_loadaddr_ref_reg(exprasmlist,funcretref,hregister);
+                  reference_reset_base(href,procinfo^.framepointer,inlinecode.retoffset);
+                  cg.a_load_reg_ref(exprasmlist,OS_ADDR,hregister,href);
+                  cg.free_scratch_reg(exprasmlist,hregister);
+               end
+             else
+               cg.a_paramaddr_ref(exprasmlist,funcretref,-1);
+           end;
+
+         { PROCEDURE variable or normal function call ? }
+         if inlined or
+            (right=nil) then
+           begin
+              { Normal function call }
+
+              { overloaded operator has no symtable }
+              { push self }
+              if assigned(symtableproc) and
+                (symtableproc.symtabletype=withsymtable) then
+                begin
+                   { dirty trick to avoid the secondcall below }
+                   methodpointer:=ccallparanode.create(nil,nil);
+                   location_reset(methodpointer.location,LOC_REGISTER,OS_ADDR);
+                   rg.getexplicitregisterint(exprasmlist,R_ESI);
+                   methodpointer.location.register:=R_ESI;
+                   { ARGHHH this is wrong !!!
+                     if we can init from base class for a child
+                     class that the wrong VMT will be
+                     transfered to constructor !! }
+                   methodpointer.resulttype:=
+                     twithnode(twithsymtable(symtableproc).withnode).left.resulttype;
+                   { make a reference }
+                   href:=twithnode(twithsymtable(symtableproc).withnode).withreference;
+                   if ((not(nf_islocal in twithnode(twithsymtable(symtableproc).withnode).flags)) and
+                       (not twithsymtable(symtableproc).direct_with)) or
+                      is_class_or_interface(methodpointer.resulttype.def) then
+                     cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,self_pointer_reg)
+                   else
+                     cg.a_loadaddr_ref_reg(exprasmlist,href,self_pointer_reg);
+                end;
+
+              { push self }
+              if assigned(symtableproc) and
+                ((symtableproc.symtabletype=objectsymtable) or
+                (symtableproc.symtabletype=withsymtable)) then
+                begin
+                   if assigned(methodpointer) then
+                     begin
+                        {
+                        if methodpointer^.resulttype.def=classrefdef then
+                          begin
+                              two possibilities:
+                               1. constructor
+                               2. class method
+
+                          end
+                        else }
+                          begin
+                             case methodpointer.nodetype of
+                               typen:
+                                 begin
+                                    { direct call to inherited method }
+                                    if (po_abstractmethod in procdefinition.procoptions) then
+                                      begin
+                                         CGMessage(cg_e_cant_call_abstract_method);
+                                         goto dont_call;
+                                      end;
+                                    { generate no virtual call }
+                                    no_virtual_call:=true;
+
+                                    if (sp_static in symtableprocentry.symoptions) then
+                                      begin
+                                         { well lets put the VMT address directly into ESI }
+                                         { it is kind of dirty but that is the simplest    }
+                                         { way to accept virtual static functions (PM)     }
+                                         loadesi:=true;
+                                         { if no VMT just use $0 bug0214 PM }
+                                         rg.getexplicitregisterint(exprasmlist,R_ESI);
+                                         if not(oo_has_vmt in tobjectdef(methodpointer.resulttype.def).objectoptions) then
+                                           cg.a_load_const_reg(exprasmlist,OS_ADDR,0,self_pointer_reg)
+                                         else
+                                           begin
+                                             reference_reset_symbol(href,newasmsymbol(tobjectdef(methodpointer.resulttype.def).vmt_mangledname),0);
+                                             cg.a_loadaddr_ref_reg(exprasmlist,href,self_pointer_reg);
+                                           end;
+                                         { emit_reg(A_SAVE,S_L,R_ESI);
+                                           this is done below !! }
+                                      end
+                                    else
+                                      { this is a member call, so ESI isn't modfied }
+                                      loadesi:=false;
+
+                                    { a class destructor needs a flag }
+                                    if is_class(tobjectdef(methodpointer.resulttype.def)) and
+                                       (procdefinition.proctypeoption=potype_destructor) then
+                                      begin
+                                        cg.a_param_const(exprasmlist,OS_ADDR,0,2);
+                                        cg.a_param_reg(exprasmlist,OS_ADDR,self_pointer_reg,1);
+                                      end;
+
+                                    if not(is_con_or_destructor and
+                                           is_class(methodpointer.resulttype.def) and
+                                           (procdefinition.proctypeoption in [potype_constructor,potype_destructor])
+                                          ) then
+                                      cg.a_param_reg(exprasmlist,OS_ADDR,self_pointer_reg,1);
+                                    { if an inherited con- or destructor should be  }
+                                    { called in a con- or destructor then a warning }
+                                    { will be made                                  }
+                                    { con- and destructors need a pointer to the vmt }
+                                    if is_con_or_destructor and
+                                      is_object(methodpointer.resulttype.def) and
+                                      assigned(aktprocdef) then
+                                      begin
+                                         if not(aktprocdef.proctypeoption in
+                                                [potype_constructor,potype_destructor]) then
+                                          CGMessage(cg_w_member_cd_call_from_method);
+                                      end;
+                                    { class destructors get there flag above }
+                                    { constructor flags ?                    }
+                                    if is_con_or_destructor and
+                                      not(
+                                        is_class(methodpointer.resulttype.def) and
+                                        assigned(aktprocdef) and
+                                        (aktprocdef.proctypeoption=potype_destructor)) then
+                                      begin
+                                         { a constructor needs also a flag }
+                                         if is_class(methodpointer.resulttype.def) then
+                                           cg.a_param_const(exprasmlist,OS_ADDR,0,2);
+                                         cg.a_param_const(exprasmlist,OS_ADDR,0,1);
+                                      end;
+                                 end;
+                               hnewn:
+                                 begin
+                                    { extended syntax of new }
+                                    { ESI must be zero }
+                                    rg.getexplicitregisterint(exprasmlist,R_ESI);
+                                    cg.a_load_const_reg(exprasmlist,OS_ADDR,0,self_pointer_reg);
+                                    cg.a_param_reg(exprasmlist,OS_ADDR,self_pointer_reg,2);
+                                    { insert the vmt }
+                                    reference_reset_symbol(href,newasmsymbol(tobjectdef(methodpointer.resulttype.def).vmt_mangledname),0);
+                                    cg.a_paramaddr_ref(exprasmlist,href,1);
+                                    extended_new:=true;
+                                 end;
+                               hdisposen:
+                                 begin
+                                    secondpass(methodpointer);
+
+                                    { destructor with extended syntax called from dispose }
+                                    { hdisposen always deliver LOC_REFERENCE          }
+                                    rg.getexplicitregisterint(exprasmlist,R_ESI);
+                                    emit_ref_reg(A_LEA,S_L,methodpointer.location.reference,R_ESI);
+                                    reference_release(exprasmlist,methodpointer.location.reference);
+                                    cg.a_param_reg(exprasmlist,OS_ADDR,self_pointer_reg,2);
+                                    reference_reset_symbol(href,newasmsymbol(tobjectdef(methodpointer.resulttype.def).vmt_mangledname),0);
+                                    cg.a_paramaddr_ref(exprasmlist,href,1);
+                                 end;
+                               else
+                                 begin
+                                    { call to an instance member }
+                                    if (symtableproc.symtabletype<>withsymtable) then
+                                      begin
+                                         secondpass(methodpointer);
+                                         rg.getexplicitregisterint(exprasmlist,R_ESI);
+                                         case methodpointer.location.loc of
+                                            LOC_CREGISTER,
+                                            LOC_REGISTER:
+                                              begin
+                                                 cg.a_load_reg_reg(exprasmlist,OS_ADDR,methodpointer.location.register,R_ESI);
+                                                 rg.ungetregisterint(exprasmlist,methodpointer.location.register);
+                                              end;
+                                            else
+                                              begin
+                                                 if (methodpointer.resulttype.def.deftype=classrefdef) or
+                                                    is_class_or_interface(methodpointer.resulttype.def) then
+                                                   cg.a_load_ref_reg(exprasmlist,OS_ADDR,methodpointer.location.reference,R_ESI)
+                                                 else
+                                                   cg.a_loadaddr_ref_reg(exprasmlist,methodpointer.location.reference,R_ESI);
+                                                 reference_release(exprasmlist,methodpointer.location.reference);
+                                              end;
+                                         end;
+                                      end;
+                                    { when calling a class method, we have to load ESI with the VMT !
+                                      But, not for a class method via self }
+                                    if not(po_containsself in procdefinition.procoptions) then
+                                      begin
+                                        if (po_classmethod in procdefinition.procoptions) and
+                                           not(methodpointer.resulttype.def.deftype=classrefdef) then
+                                          begin
+                                             { class method needs current VMT }
+                                             rg.getexplicitregisterint(exprasmlist,R_ESI);
+                                             reference_reset_base(href,R_ESI,tprocdef(procdefinition)._class.vmt_offset);
+                                             cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,self_pointer_reg);
+                                          end;
+
+                                        { direct call to destructor: remove data }
+                                        if (procdefinition.proctypeoption=potype_destructor) and
+                                           is_class(methodpointer.resulttype.def) then
+                                          cg.a_param_const(exprasmlist,OS_INT,1,1);
+
+                                        { direct call to class constructor, don't allocate memory }
+                                        if (procdefinition.proctypeoption=potype_constructor) and
+                                           is_class(methodpointer.resulttype.def) then
+                                          begin
+                                             cg.a_param_const(exprasmlist,OS_INT,0,2);
+                                             cg.a_param_const(exprasmlist,OS_INT,0,1);
+                                          end
+                                        else
+                                          begin
+                                             { constructor call via classreference => allocate memory }
+                                             if (procdefinition.proctypeoption=potype_constructor) and
+                                                (methodpointer.resulttype.def.deftype=classrefdef) and
+                                                is_class(tclassrefdef(methodpointer.resulttype.def).pointertype.def) then
+                                               cg.a_param_const(exprasmlist,OS_INT,1,1);
+                                             cg.a_param_reg(exprasmlist,OS_ADDR,self_pointer_reg,1);
+                                          end;
+                                      end;
+
+                                    if is_con_or_destructor then
+                                      begin
+                                         { classes don't get a VMT pointer pushed }
+                                         if is_object(methodpointer.resulttype.def) then
+                                           begin
+                                              if (procdefinition.proctypeoption=potype_constructor) then
+                                                begin
+                                                  { it's no bad idea, to insert the VMT }
+                                                  reference_reset_symbol(href,newasmsymbol(
+                                                     tobjectdef(methodpointer.resulttype.def).vmt_mangledname),0);
+                                                  cg.a_paramaddr_ref(exprasmlist,href,1);
+                                                end
+                                              { destructors haven't to dispose the instance, if this is }
+                                              { a direct call                                           }
+                                              else
+                                                cg.a_param_const(exprasmlist,OS_INT,0,1);
+                                           end;
+                                      end;
+                                 end;
+                             end;
+                          end;
+                     end
+                   else
+                     begin
+                        if (po_classmethod in procdefinition.procoptions) and
+                          not(
+                            assigned(aktprocdef) and
+                            (po_classmethod in aktprocdef.procoptions)
+                          ) then
+                          begin
+                             { class method needs current VMT }
+                             rg.getexplicitregisterint(exprasmlist,R_ESI);
+                             reference_reset_base(href,R_ESI,tprocdef(procdefinition)._class.vmt_offset);
+                             cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,R_ESI);
+                          end
+                        else
+                          begin
+                             { member call, ESI isn't modified }
+                             loadesi:=false;
+                          end;
+                        { direct call to destructor: don't remove data! }
+                        if is_class(procinfo^._class) then
+                          begin
+                             if (procdefinition.proctypeoption=potype_destructor) then
+                               begin
+                                  cg.a_param_const(exprasmlist,OS_INT,0,2);
+                                  cg.a_param_reg(exprasmlist,OS_ADDR,R_ESI,1);
+                               end
+                             else if (procdefinition.proctypeoption=potype_constructor) then
+                               begin
+                                  cg.a_param_const(exprasmlist,OS_INT,0,2);
+                                  cg.a_param_const(exprasmlist,OS_INT,0,1);
+                               end
+                             else
+                               cg.a_param_reg(exprasmlist,OS_ADDR,R_ESI,1);
+                          end
+                        else if is_object(procinfo^._class) then
+                          begin
+                             cg.a_param_reg(exprasmlist,OS_ADDR,R_ESI,1);
+                             if is_con_or_destructor then
+                               begin
+                                  if (procdefinition.proctypeoption=potype_constructor) then
+                                    begin
+                                      { it's no bad idea, to insert the VMT }
+                                      reference_reset_symbol(href,newasmsymbol(procinfo^._class.vmt_mangledname),0);
+                                      cg.a_paramaddr_ref(exprasmlist,href,1);
+                                    end
+                                  { destructors haven't to dispose the instance, if this is }
+                                  { a direct call                                           }
+                                  else
+                                    cg.a_param_const(exprasmlist,OS_INT,0,1);
+                               end;
+                          end
+                        else
+                          Internalerror(200006165);
+                     end;
+                end;
+
+                { call to BeforeDestruction? }
+                if (procdefinition.proctypeoption=potype_destructor) and
+                   assigned(methodpointer) and
+                   (methodpointer.nodetype<>typen) and
+                   is_class(tobjectdef(methodpointer.resulttype.def)) and
+                   (inlined or
+                   (right=nil)) then
+                  begin
+                     cg.a_param_reg(exprasmlist,OS_ADDR,self_pointer_reg,1);
+                     reference_reset_base(href,self_pointer_reg,0);
+                     tmpreg:=cg.get_scratch_reg_address(exprasmlist);
+                     cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,tmpreg);
+                     reference_reset_base(href,tmpreg,72);
+                     cg.a_call_ref(exprasmlist,href);
+                     cg.free_scratch_reg(exprasmlist,tmpreg);
+                  end;
+
+              { push base pointer ?}
+              { never when inlining, since if necessary, the base pointer }
+              { can/will be gottten from the current PROCEDURE's symtable }
+              { (JM)                                                      }
+              if not inlined then
+                if (lexlevel>=normal_function_level) and assigned(tprocdef(procdefinition).parast) and
+                  ((tprocdef(procdefinition).parast.symtablelevel)>normal_function_level) then
+                  begin
+                     { if we call a nested function in a method, we must      }
+                     { push also SELF!                                    }
+                     { THAT'S NOT TRUE, we have to load ESI via frame pointer }
+                     { access                                              }
+                     {
+                       begin
+                          loadesi:=false;
+                          emit_reg(A_SAVE,S_L,R_ESI);
+                       end;
+                     }
+                     if lexlevel=(tprocdef(procdefinition).parast.symtablelevel) then
+                       begin
+                          reference_reset_base(href,procinfo^.framepointer,procinfo^.framepointer_offset);
+                          cg.a_param_ref(exprasmlist,OS_ADDR,href,-1);
+                       end
+                       { this is only true if the difference is one !!
+                         but it cannot be more !! }
+                     else if (lexlevel=(tprocdef(procdefinition).parast.symtablelevel)-1) then
+                       begin
+                          cg.a_param_reg(exprasmlist,OS_ADDR,procinfo^.framepointer,-1);
+                       end
+                     else if (lexlevel>(tprocdef(procdefinition).parast.symtablelevel)) then
+                       begin
+                          hregister:=rg.getregisterint(exprasmlist);
+                          reference_reset_base(href,procinfo^.framepointer,procinfo^.framepointer_offset);
+                          cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,hregister);
+                          for i:=(tprocdef(procdefinition).parast.symtablelevel) to lexlevel-1 do
+                            begin
+                               {we should get the correct frame_pointer_offset at each level
+                               how can we do this !!! }
+                               reference_reset_base(href,hregister,procinfo^.framepointer_offset);
+                               cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,hregister);
+                            end;
+                          cg.a_param_reg(exprasmlist,OS_ADDR,hregister,-1);
+                          rg.ungetregisterint(exprasmlist,hregister);
+                       end
+                     else
+                       internalerror(25000);
+                  end;
+
+              rg.saveregvars(exprasmlist,regs_to_push);
+
+              if (po_virtualmethod in procdefinition.procoptions) and
+                 not(no_virtual_call) then
+                begin
+                   { static functions contain the vmt_address in ESI }
+                   { also class methods                       }
+                   { Here it is quite tricky because it also depends }
+                   { on the methodpointer                        PM }
+                   release_tmpreg:=false;
+                   rg.getexplicitregisterint(exprasmlist,R_ESI);
+                   if assigned(aktprocdef) then
+                     begin
+                       if (((sp_static in aktprocdef.procsym.symoptions) or
+                        (po_classmethod in aktprocdef.procoptions)) and
+                        ((methodpointer=nil) or (methodpointer.nodetype=typen)))
+                        or
+                        (po_staticmethod in procdefinition.procoptions) or
+                        ((procdefinition.proctypeoption=potype_constructor) and
+                        { esi contains the vmt if we call a constructor via a class ref }
+                         assigned(methodpointer) and
+                         (methodpointer.resulttype.def.deftype=classrefdef)
+                        ) or
+                        { is_interface(tprocdef(procdefinition)._class) or }
+                        { ESI is loaded earlier }
+                        (po_classmethod in procdefinition.procoptions) then
+                         begin
+                            reference_reset_base(href,R_ESI,0);
+                         end
+                       else
+                         begin
+                            { this is one point where we need vmt_offset (PM) }
+                            reference_reset_base(href,R_ESI,tprocdef(procdefinition)._class.vmt_offset);
+                            tmpreg:=cg.get_scratch_reg_address(exprasmlist);
+                            cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,tmpreg);
+                            reference_reset_base(href,tmpreg,0);
+                            release_tmpreg:=true;
+                         end;
+                     end
+                   else
+                     { aktprocdef should be assigned, also in main program }
+                     internalerror(12345);
+
+                   if tprocdef(procdefinition).extnumber=-1 then
+                     internalerror(44584);
+
+                   href.offset:=tprocdef(procdefinition)._class.vmtmethodoffset(tprocdef(procdefinition).extnumber);
+                   if not(is_interface(tprocdef(procdefinition)._class)) and
+                      not(is_cppclass(tprocdef(procdefinition)._class)) then
+                     begin
+                        if (cs_check_object in aktlocalswitches) then
+                          begin
+                             reference_reset_symbol(hrefvmt,newasmsymbol(tprocdef(procdefinition)._class.vmt_mangledname),0);
+                             cg.a_paramaddr_ref(exprasmlist,hrefvmt,2);
+                             cg.a_param_reg(exprasmlist,OS_ADDR,href.base,1);
+                             cg.a_call_name(exprasmlist,'FPC_CHECK_OBJECT_EXT');
+                          end
+                        else if (cs_check_range in aktlocalswitches) then
+                          begin
+                             cg.a_param_reg(exprasmlist,OS_ADDR,href.base,1);
+                             cg.a_call_name(exprasmlist,'FPC_CHECK_OBJECT');
+                          end;
+                     end;
+                   cg.a_call_ref(exprasmlist,href);
+                   if release_tmpreg then
+                     cg.free_scratch_reg(exprasmlist,tmpreg);
+                end
+              else if not inlined then
+                begin
+                  { We can call interrupts from within the smae code
+                    by just pushing the flags and CS PM }
+                  if (po_interrupt in procdefinition.procoptions) then
+                    begin
+                        emit_none(A_SAVE{F},S_L);
+                        emit_reg(A_SAVE,S_L,R_CS);
+                    end;
+                  cg.a_call_name(exprasmlist,tprocdef(procdefinition).mangledname);
+                end
+              else { inlined proc }
+                { inlined code is in inlinecode }
+                begin
+                   { process the inlinecode }
+                   secondpass(inlinecode);
+                   { free the args }
+                   if tprocdef(procdefinition).parast.datasize>0 then
+                     tg.ungetpersistanttemp(exprasmlist,tprocdef(procdefinition).parast.address_fixup);
+                end;
+           end
+         else
+           { now PROCEDURE variable case }
+           begin
+              secondpass(right);
+              if (po_interrupt in procdefinition.procoptions) then
+                begin
+                    emit_none(A_SAVE{F},S_L);
+                    emit_reg(A_SAVE,S_L,R_CS);
+                end;
+              { PROCEDURE of object? }
+              if (po_methodpointer in procdefinition.procoptions) then
+                begin
+                   { method pointer can't be in a register }
+                   hregister:=R_NO;
+
+                   { do some hacking if we call a method pointer }
+                   { which is a class member                 }
+                   { else ESI is overwritten !             }
+                   if (right.location.reference.base=R_ESI) or
+                      (right.location.reference.index=R_ESI) then
+                     begin
+                        reference_release(exprasmlist,right.location.reference);
+                        hregister:=cg.get_scratch_reg_address(exprasmlist);
+                        cg.a_load_ref_reg(exprasmlist,OS_ADDR,right.location.reference,hregister);
+                     end;
+
+                   { load self, but not if it's already explicitly pushed }
+                   if not(po_containsself in procdefinition.procoptions) then
+                     begin
+                       { load ESI }
+                       href:=right.location.reference;
+                       inc(href.offset,4);
+                       rg.getexplicitregisterint(exprasmlist,R_ESI);
+                       cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,self_pointer_reg);
+                       { push self pointer }
+                       cg.a_param_reg(exprasmlist,OS_ADDR,self_pointer_reg,-1);
+                     end;
+
+                   rg.saveregvars(exprasmlist,ALL_REGISTERS);
+                   if hregister<>R_NO then
+                     reference_reset_base(href,hregister,0)
+                   else
+                     href:=right.location.reference;
+                   cg.a_call_ref(exprasmlist,href);
+
+                   if hregister<>R_NO then
+                     cg.free_scratch_reg(exprasmlist,hregister);
+                   reference_release(exprasmlist,right.location.reference);
+                end
+              else
+                begin
+                   rg.saveregvars(exprasmlist,ALL_REGISTERS);
+                   case right.location.loc of
+                      LOC_REGISTER,LOC_CREGISTER:
+                        reference_reset_base(href,right.location.register,0);
+                      LOC_REFERENCE,LOC_CREFERENCE :
+                        href:=right.location.reference;
+                      else
+                        internalerror(200203311);
+                   end;
+                   cg.a_call_ref(exprasmlist,href);
+                   location_release(exprasmlist,right.location);
+                end;
+           end;
+
+           { this was only for normal functions
+             displaced here so we also get
+             it to work for procvars PM }
+           if (not inlined) and (po_clearstack in procdefinition.procoptions) then
+             begin
+                { we also add the pop_size which is included in pushedparasize }
+                pop_size:=0;
+                { better than an add on all processors }
+                if pushedparasize=4 then
+                  begin
+                    rg.getexplicitregisterint(exprasmlist,R_EDI);
+                    emit_reg(A_RESTORE,S_L,R_EDI);
+                    rg.ungetregisterint(exprasmlist,R_EDI);
+                  end
+                { the pentium has two pipes and pop reg is pairable }
+                { but the registers must be different!        }
+                else if (pushedparasize=8) and
+                  not(cs_littlesize in aktglobalswitches) and
+                  (aktoptprocessor=ClassP5) and
+                  (procinfo^._class=nil) then
+                    begin
+                       rg.getexplicitregisterint(exprasmlist,R_EDI);
+                       emit_reg(A_RESTORE,S_L,R_EDI);
+                       rg.ungetregisterint(exprasmlist,R_EDI);
+                       exprasmList.concat(Tairegalloc.Alloc(R_ESI));
+                       emit_reg(A_RESTORE,S_L,R_ESI);
+                       exprasmList.concat(Tairegalloc.DeAlloc(R_ESI));
+                    end
+                else if pushedparasize<>0 then
+                  emit_const_reg(A_ADD,S_L,pushedparasize,Stack_Pointer_Reg);
+             end;
+{$ifdef OPTALIGN}
+         if pop_esp then
+           emit_reg(A_RESTORE,S_L,Stack_Pointer);
+{$endif OPTALIGN}
+      dont_call:
+         pushedparasize:=oldpushedparasize;
+         rg.restoreunusedstate(unusedstate);
+{$ifdef TEMPREGDEBUG}
+         testregisters32;
+{$endif TEMPREGDEBUG}
+
+         { a constructor could be a function with boolean result }
+         { if calling constructor called fail we
+           must jump directly to quickexitlabel  PM
+           but only if it is a call of an inherited constructor }
+         if (inlined or
+             (right=nil)) and
+            (procdefinition.proctypeoption=potype_constructor) and
+            assigned(methodpointer) and
+            (methodpointer.nodetype=typen) and
+            (aktprocdef.proctypeoption=potype_constructor) then
+           begin
+             emitjmp(C_Z,faillabel);
+           end;
+
+         { call to AfterConstruction? }
+         if is_class(resulttype.def) and
+           (inlined or
+           (right=nil)) and
+           (procdefinition.proctypeoption=potype_constructor) and
+           assigned(methodpointer) and
+           (methodpointer.nodetype<>typen) then
+           begin
+              getlabel(constructorfailed);
+              emitjmp(C_Z,constructorfailed);
+              cg.a_param_reg(exprasmlist,OS_ADDR,self_pointer_reg,1);
+              reference_reset_base(href,self_pointer_reg,0);
+              tmpreg:=cg.get_scratch_reg_address(exprasmlist);
+              cg.a_load_ref_reg(exprasmlist,OS_ADDR,href,tmpreg);
+              reference_reset_base(href,tmpreg,68);
+              cg.a_call_ref(exprasmlist,href);
+              cg.free_scratch_reg(exprasmlist,tmpreg);
+              exprasmList.concat(Tairegalloc.Alloc(accumulator));
+              cg.a_label(exprasmlist,constructorfailed);
+              cg.a_load_reg_reg(exprasmlist,OS_ADDR,self_pointer_reg,accumulator);
+           end;
+
+         { handle function results }
+         if (not is_void(resulttype.def)) then
+          begin
+            { structured results are easy to handle.... }
+            { needed also when result_no_used !! }
+            if ret_in_param(resulttype.def) then
+             begin
+               location_reset(location,LOC_CREFERENCE,def_cgsize(resulttype.def));
+               location.reference.symbol:=nil;
+               location.reference:=funcretref;
+             end
+            else
+            { ansi/widestrings must be registered, so we can dispose them }
+             if is_ansistring(resulttype.def) or
+                is_widestring(resulttype.def) then
+              begin
+                location_reset(location,LOC_CREFERENCE,OS_ADDR);
+                location.reference:=refcountedtemp;
+                cg.a_reg_alloc(exprasmlist,accumulator);
+                cg.a_load_reg_ref(exprasmlist,OS_ADDR,accumulator,location.reference);
+                cg.a_reg_dealloc(exprasmlist,accumulator);
+              end
+            else
+            { we have only to handle the result if it is used }
+             if (nf_return_value_used in flags) then
+              begin
+                case resulttype.def.deftype of
+                  enumdef,
+                  orddef :
+                    begin
+                      cgsize:=def_cgsize(resulttype.def);
+                      { an object constructor is a function with boolean result }
+                      if (inlined or (right=nil)) and
+                         (procdefinition.proctypeoption=potype_constructor) then
+                       begin
+                         if extended_new then
+                          cgsize:=OS_INT
+                         else
+                          begin
+                            cgsize:=OS_NO;
+                            { this fails if popsize > 0 PM }
+                            location_reset(location,LOC_FLAGS,OS_NO);
+                            location.resflags:=F_NE;
+                          end;
+                       end;
+
+                      if cgsize<>OS_NO then
+                       begin
+                         location_reset(location,LOC_REGISTER,cgsize);
+                         cg.a_reg_alloc(exprasmlist,accumulator);
+                         if cgsize in [OS_64,OS_S64] then
+                          begin
+                            cg.a_reg_alloc(exprasmlist,accumulatorhigh);
+                            if accumulatorhigh in rg.unusedregsint then
+                              begin
+                                 location.registerhigh:=rg.getexplicitregisterint(exprasmlist,accumulatorhigh);
+                                 location.registerlow:=rg.getexplicitregisterint(exprasmlist,accumulator);
+                              end
+                            else
+                              begin
+                                 location.registerhigh:=rg.getexplicitregisterint(exprasmlist,accumulatorhigh);
+                                 location.registerlow:=rg.getexplicitregisterint(exprasmlist,accumulator);
+                              end;
+                            tcg64f32(cg).a_load64_reg_reg(exprasmlist,accumulator,accumulatorhigh,
+                                location.registerlow,location.registerhigh);
+                          end
+                         else
+                          begin
+                            location.register:=rg.getexplicitregisterint(exprasmlist,accumulator);
+                            hregister:=rg.makeregsize(accumulator,cgsize);
+                            location.register:=rg.makeregsize(location.register,cgsize);
+                            cg.a_load_reg_reg(exprasmlist,cgsize,hregister,location.register);
+                          end;
+                       end;
+                    end;
+                  floatdef :
+                    begin
+                      location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
+                      location.register:=R_ST;
+                      inc(trgcpu(rg).fpuvaroffset);
+                    end;
+                  else
+                    begin
+                      location_reset(location,LOC_REGISTER,OS_INT);
+                      location.register:=rg.getexplicitregisterint(exprasmlist,accumulator);
+                      cg.a_load_reg_reg(exprasmlist,OS_INT,accumulator,location.register);
+                    end;
+                end;
+             end;
+          end;
+
+         { perhaps i/o check ? }
+         if iolabel<>nil then
+           begin
+              reference_reset_symbol(href,iolabel,0);
+              cg.a_paramaddr_ref(exprasmlist,href,1);
+              cg.a_call_name(exprasmlist,'FPC_IOCHECK');
+           end;
+         if pop_size>0 then
+           emit_const_reg(A_ADD,S_L,pop_size,Stack_Pointer_Reg);
+
+         { restore registers }
+         rg.restoreusedregisters(exprasmlist,pushed);
+
+         { at last, restore instance pointer (SELF) }
+         if loadesi then
+           cg.g_maybe_loadself(exprasmlist);
+         pp:=tbinarynode(params);
+         while assigned(pp) do
+           begin
+              if assigned(pp.left) then
+                begin
+                  location_freetemp(exprasmlist,pp.left.location);
+                  { process also all nodes of an array of const }
+                  if pp.left.nodetype=arrayconstructorn then
+                    begin
+                      if assigned(tarrayconstructornode(pp.left).left) then
+                       begin
+                         hp:=pp.left;
+                         while assigned(hp) do
+                          begin
+                            location_freetemp(exprasmlist,tarrayconstructornode(hp).left.location);
+                            hp:=tarrayconstructornode(hp).right;
+                          end;
+                       end;
+                    end;
+                end;
+              pp:=tbinarynode(pp.right);
+           end;
+         if inlined then
+           begin
+             tg.ungetpersistanttemp(exprasmlist,inlinecode.retoffset);
+             tprocdef(procdefinition).parast.address_fixup:=store_parast_fixup;
+             right:=inlinecode;
+           end;
+         if assigned(params) then
+           params.free;
+
+         { from now on the result can be freed normally }
+         if inlined and ret_in_param(resulttype.def) then
+           tg.persistanttemptonormal(funcretref.offset);
+
+         { if return value is not used }
+         if (not(nf_return_value_used in flags)) and (not is_void(resulttype.def)) then
+           begin
+              if location.loc in [LOC_CREFERENCE,LOC_REFERENCE] then
+                begin
+                   { data which must be finalized ? }
+                   if (resulttype.def.needs_inittable) then
+                      cg.g_finalize(exprasmlist,resulttype.def,location.reference,false);
+                   { release unused temp }
+                   tg.ungetiftemp(exprasmlist,location.reference)
+                end
+              else if location.loc=LOC_FPUREGISTER then
+                begin
+                  { release FPU stack }
+                  emit_reg(A_FSTP,S_NO,R_ST);
+                  {
+                    dec(trgcpu(rg).fpuvaroffset);
+                    do NOT decrement as the increment before
+                    is not called for unused results PM }
+                end;
+           end;
+      end;
+
+
+
+{*****************************************************************************
+                             TI386PROCINLINENODE
+*****************************************************************************}
+
+
+    PROCEDURE tSPARCprocinlinenode.pass_2;
+       var st : tsymtable;
+           oldprocdef : tprocdef;
+           ps, i : longint;
+           tmpreg: tregister;
+           oldprocinfo : pprocinfo;
+           oldinlining_PROCEDURE,
+           nostackframe,make_global : boolean;
+           inlineentrycode,inlineexitcode : TAAsmoutput;
+           oldexitlabel,oldexit2label,oldquickexitlabel:tasmlabel;
+           oldregstate: pointer;
+{$ifdef GDB}
+           startlabel,endlabel : tasmlabel;
+           pp : pchar;
+           mangled_length  : longint;
+{$endif GDB}
+       begin
+          { deallocate the registers used for the current PROCEDURE's regvars }
+          if assigned(aktprocdef.regvarinfo) then
+            begin
+              with pregvarinfo(aktprocdef.regvarinfo)^ do
+                for i := 1 to maxvarregs do
+                  if assigned(regvars[i]) then
+                    store_regvar(exprasmlist,regvars[i].reg);
+              rg.saveStateForInline(oldregstate);
+              { make sure the register allocator knows what the regvars in the }
+              { inlined code block are (JM)                                    }
+              rg.resetusableregisters;
+              rg.clearregistercount;
+              rg.cleartempgen;
+              if assigned(inlineprocdef.regvarinfo) then
+                with pregvarinfo(inlineprocdef.regvarinfo)^ do
+                  for i := 1 to maxvarregs do
+                    if assigned(regvars[i]) then
+                      begin
+                        tmpreg:=rg.makeregsize(regvars[i].reg,OS_INT);
+                        rg.makeregvar(tmpreg);
+                      end;
+            end;
+          oldinlining_PROCEDURE:=inlining_PROCEDURE;
+          oldexitlabel:=aktexitlabel;
+          oldexit2label:=aktexit2label;
+          oldquickexitlabel:=quickexitlabel;
+          getlabel(aktexitlabel);
+          getlabel(aktexit2label);
+          { we're inlining a PROCEDURE }
+          inlining_PROCEDURE:=true;
+          { save old procinfo }
+          oldprocdef:=aktprocdef;
+          getmem(oldprocinfo,sizeof(tprocinfo));
+          move(procinfo^,oldprocinfo^,sizeof(tprocinfo));
+          { set new procinfo }
+          aktprocdef:=inlineprocdef;
+          procinfo^.return_offset:=retoffset;
+          procinfo^.para_offset:=para_offset;
+          procinfo^.no_fast_exit:=false;
+          { arg space has been filled by the parent secondcall }
+          st:=aktprocdef.localst;
+          { set it to the same lexical level }
+          st.symtablelevel:=oldprocdef.localst.symtablelevel;
+          if st.datasize>0 then
+            begin
+              st.address_fixup:=tg.gettempofsizepersistant(exprasmlist,st.datasize)+st.datasize;
+{$ifdef extdebug}
+              Comment(V_debug,'local symtable is at offset '+tostr(st.address_fixup));
+              exprasmList.concat(Tai_asm_comment.Create(strpnew(
+                'local symtable is at offset '+tostr(st.address_fixup))));
+{$endif extdebug}
+            end;
+          exprasmList.concat(Tai_Marker.Create(InlineStart));
+{$ifdef extdebug}
+          exprasmList.concat(Tai_asm_comment.Create(strpnew('Start of inlined proc')));
+{$endif extdebug}
+{$ifdef GDB}
+          if (cs_debuginfo in aktmoduleswitches) then
+            begin
+              getaddrlabel(startlabel);
+              getaddrlabel(endlabel);
+              cg.a_label(exprasmlist,startlabel);
+              inlineprocdef.localst.symtabletype:=inlinelocalsymtable;
+              inlineprocdef.parast.symtabletype:=inlineparasymtable;
+
+              { Here we must include the para and local symtable info }
+              inlineprocdef.concatstabto(withdebuglist);
+
+              { set it back for safety }
+              inlineprocdef.localst.symtabletype:=localsymtable;
+              inlineprocdef.parast.symtabletype:=parasymtable;
+
+              mangled_length:=length(oldprocdef.mangledname);
+              getmem(pp,mangled_length+50);
+              strpcopy(pp,'192,0,0,'+startlabel.name);
+              if (target_info.use_function_relative_addresses) then
+                begin
+                  strpcopy(strend(pp),'-');
+                  strpcopy(strend(pp),oldprocdef.mangledname);
+                end;
+              withdebugList.concat(Tai_stabn.Create(strnew(pp)));
+            end;
+{$endif GDB}
+          { takes care of local data initialization }
+          inlineentrycode:=TAAsmoutput.Create;
+          inlineexitcode:=TAAsmoutput.Create;
+          ps:=para_size;
+          make_global:=false; { to avoid warning }
+          genentrycode(inlineentrycode,make_global,0,ps,nostackframe,true);
+          if po_assembler in aktprocdef.procoptions then
+            inlineentrycode.insert(Tai_marker.Create(asmblockstart));
+          exprasmList.concatlist(inlineentrycode);
+          secondpass(inlinetree);
+          genexitcode(inlineexitcode,0,false,true);
+          if po_assembler in aktprocdef.procoptions then
+            inlineexitcode.concat(Tai_marker.Create(asmblockend));
+          exprasmList.concatlist(inlineexitcode);
+
+          inlineentrycode.free;
+          inlineexitcode.free;
+{$ifdef extdebug}
+          exprasmList.concat(Tai_asm_comment.Create(strpnew('End of inlined proc')));
+{$endif extdebug}
+          exprasmList.concat(Tai_Marker.Create(InlineEnd));
+
+          {we can free the local data now, reset also the fixup address }
+          if st.datasize>0 then
+            begin
+              tg.ungetpersistanttemp(exprasmlist,st.address_fixup-st.datasize);
+              st.address_fixup:=0;
+            end;
+          { restore procinfo }
+          move(oldprocinfo^,procinfo^,sizeof(tprocinfo));
+          freemem(oldprocinfo,sizeof(tprocinfo));
+{$ifdef GDB}
+          if (cs_debuginfo in aktmoduleswitches) then
+            begin
+              cg.a_label(exprasmlist,endlabel);
+              strpcopy(pp,'224,0,0,'+endlabel.name);
+             if (target_info.use_function_relative_addresses) then
+               begin
+                 strpcopy(strend(pp),'-');
+                 strpcopy(strend(pp),oldprocdef.mangledname);
+               end;
+              withdebugList.concat(Tai_stabn.Create(strnew(pp)));
+              freemem(pp,mangled_length+50);
+            end;
+{$endif GDB}
+          { restore }
+          aktprocdef:=oldprocdef;
+          aktexitlabel:=oldexitlabel;
+          aktexit2label:=oldexit2label;
+          quickexitlabel:=oldquickexitlabel;
+          inlining_PROCEDURE:=oldinlining_PROCEDURE;
+
+          { reallocate the registers used for the current PROCEDURE's regvars, }
+          { since they may have been used and then deallocated in the inlined  }
+          { PROCEDURE (JM)                                                     }
+          if assigned(aktprocdef.regvarinfo) then
+            begin
+              rg.restoreStateAfterInline(oldregstate);
+            end;
+       end;
+
+
+begin
+   ccallparanode:=tSPARCcallparanode;
+   ccallnode:=tSPARCcallnode;
+   cprocinlinenode:=tSPARCprocinlinenode;
+end.
+{
+  $Log$
+  Revision 1.1  2002-08-22 08:30:50  mazen
+  first insertion 2002\08\22
+
+  Revision 1.54  2002/05/20 13:30:40  carl
+  * bugfix of hdisponen (base must be set, not index)
+  * more portability fixes
+
+  Revision 1.53  2002/05/18 13:34:23  peter
+    * readded missing revisions
+
+  Revision 1.52  2002/05/16 19:46:51  carl
+  + defines.inc -> fpcdefs.inc to avoid conflicts if compiling by hand
+  + try to fix temp allocation (still in ifdef)
+  + generic constructor calls
+  + start of tassembler / tmodulebase class cleanup
+
+  Revision 1.50  2002/05/13 19:54:38  peter
+    * removed n386ld and n386util units
+    * maybe_save/maybe_restore added instead of the old maybe_push
+
+  Revision 1.49  2002/05/12 16:53:17  peter
+    * moved entry and exitcode to ncgutil and cgobj
+    * foreach gets extra argument for passing local data to the
+      iterator function
+    * -CR checks also class typecasts at runtime by changing them
+      into as
+    * fixed compiler to cycle with the -CR option
+    * fixed stabs with elf writer, finally the global variables can
+      be watched
+    * removed a lot of routines from cga unit and replaced them by
+      calls to cgobj
+    * u32bit-s32bit updates for and,or,xor nodes. When one element is
+      u32bit then the other is typecasted also to u32bit without giving
+      a rangecheck warning/error.
+    * fixed pascal calling method with reversing also the high tree in
+      the parast, detected by tcalcst3 test
+
+  Revision 1.48  2002/04/25 20:16:40  peter
+    * moved more routines from cga/n386util
+
+  Revision 1.47  2002/04/21 19:02:07  peter
+    * removed newn and disposen nodes, the code is now directly
+      inlined from pexpr
+    * -an option that will write the secondpass nodes to the .s file, this
+      requires EXTDEBUG define to actually write the info
+    * fixed various internal errors and crashes due recent code changes
+
+  Revision 1.46  2002/04/21 15:34:25  carl
+  * changeregsize -> rg.makeregsize
+
+  Revision 1.45  2002/04/15 19:44:21  peter
+    * fixed stackcheck that would be called recursively when a stack
+      error was found
+    * generic changeregsize(reg,size) for SPARC register resizing
+    * removed some more routines from cga unit
+    * fixed returnvalue handling
+    * fixed default stacksize of linux and go32v2, 8kb was a bit small :-)
+
+  Revision 1.44  2002/04/04 19:06:10  peter
+    * removed unused units
+    * use tlocation.size in cg.a_*loc*() routines
+
+  Revision 1.43  2002/04/02 17:11:35  peter
+    * tlocation,treference update
+    * LOC_CONSTANT added for better constant handling
+    * secondadd splitted in multiple routines
+    * location_force_reg added for loading a location to a register
+      of a specified size
+    * secondassignment parses now first the right and then the left node
+      (this is compatible with Kylix). This saves a lot of push/pop especially
+      with string operations
+    * adapted some routines to use the new cg methods
+
+  Revision 1.42  2002/03/31 20:26:38  jonas
+    + a_loadfpu_* and a_loadmm_* methods in tcg
+    * register allocation is now handled by a class and is mostly processor
+      independent (+rgobj.pas and SPARC/rgcpu.pas)
+    * temp allocation is now handled by a class (+tgobj.pas, -SPARC\tgcpu.pas)
+    * some small improvements and fixes to the optimizer
+    * some register allocation fixes
+    * some fpuvaroffset fixes in the unary minus node
+    * push/popusedregisters is now called rg.save/restoreusedregisters and
+      (for SPARC) uses temps instead of push/pop's when using -Op3 (that code is
+      also better optimizable)
+    * fixed and optimized register saving/restoring for new/dispose nodes
+    * LOC_FPU locations now also require their "register" field to be set to
+      R_ST, not R_ST0 (the latter is used for LOC_CFPUREGISTER locations only)
+    - list field removed of the tnode class because it's not used currently
+      and can cause hard-to-find bugs
+
+  Revision 1.41  2002/03/04 19:10:13  peter
+    * removed compiler warnings
+
+}

compiler/sparc/opcode.inc

@@ -0,0 +1,72 @@
+{*****************************************************************************}
+{ File                   : sparcop.pas                                        }
+{ Author                 : Mazen NEIFER                                       }
+{ Project                : Free Pascal Compiler (FPC)                         }
+{ Creation date          : 2002\05\01                                         }
+{ Last modification date : 2002\07\01                                         }
+{ Licence                : GPL                                                }
+{ Bug report             : [email protected]                        }
+{*****************************************************************************}
+A_NONE,
+A_ABCD,
+A_ADD,A_ADDcc,A_ADDX,A_ADDXcc,
+A_AND,A_ANDcc,A_ANDN,A_ADDNcc,
+A_BN,A_BNE,A_BE,A_BG,A_BLE,A_BGE,A_BI,A_BGU,A_BLEU,A_BCC,
+A_BCS,A_BPOS,A_NEG,A_BVC,A_BVS,A_BA,
+A_CALL,
+A_CBccc,
+A_FBN,A_FBU,A_FBG,A_FBUG,A_FBL,A_FBUL,A_FBLG,A_FBNE,
+A_FBE,A_FBUE,A_FBGE,A_FBUGE,A_FBLE,A_FBULE,A_FBO,A_FBA,
+A_FLUSH,
+A_JMPL,
+A_LDSB,A_LDSH,A_LDSTUB,
+A_LDUB,A_LDUH,A_LD,A_LDD,A_LDF,A_LDFSR,A_LDDF,A_LDC,A_LDCSR,A_LDDC,
+A_LDSBA,A_LDSHA,A_LDUBA,A_LDUHA,A_LDA,A_LDDA,
+A_LDSTUBA,
+A_MULScc,
+A_NOP,
+A_OR,A_ORcc,A_ORN,A_ORNcc,
+A_RDASR,A_RDY,A_RDPSR,A_RDWIM,A_RDTBR,
+A_RESTORE,
+A_RET,
+A_SAVE,
+A_SDIV,A_SDIVcc,
+A_SMUL,A_SMULcc,
+A_SETHI,
+A_SLL,A_SRL,A_SRA,
+A_STB,A_STH,A_ST,A_STD,A_STF,A_STDF,A_STFSR,A_STDFQ,
+A_STC,A_STDC,A_STCSR,A_STDCQ,
+A_STBA,A_STHA,A_STA,A_STDA,
+A_SUB,A_SUBcc,A_SUBX,A_SUBXcc,
+A_SWAP,A_SWAPA,A_Ticc,A_TADDcc,A_TSUBcc,A_TADDccTV,A_TSUBccTV,
+A_UDIV,A_UDIVcc,
+A_UMUL,A_UMULcc,
+A_UNMP,
+A_WRASR,A_WRY,A_WRPSR,A_WRWIM,A_WRTBR,
+A_XNOR,A_XNORcc,
+A_XOR,A_XORcc,
+          {Floating-point instructions}
+A_FiTOs,A_FiTOd,A_FiTOq,
+A_FsTOi,A_FdTOi,A_FqTOi,
+A_FsTOd,A_FsTOq,
+A_FdTOs,A_FdTOq,
+A_FqTOd,A_FqTOs,
+A_MOVs,A_NEGs,A_FABSs,
+A_FSQRTs,A_FSQRTd,A_FSQRTq,
+A_FADDs,A_FADDd,A_FADDq,
+A_FSUBs,A_FSUBd,A_FSUBq,
+A_FMULs,A_FMULd,A_FMULQ,
+A_FdMULq,A_FsMULd,
+A_DIVs,A_DIVd,A_FDIVq,
+A_FCMPs,A_FCMPd,A_FCMPq,
+A_FCPop1,A_CPop2,
+          {Synthetic instructions}
+A_btst,A_bset,A_bclr,A_btog,
+A_clr,A_clrb,A_clrh,
+A_CMP,
+A_dec,A_deccc,
+A_inc,A_inccc,
+A_not,
+A_set,
+A_skipz,A_skipnz,
+A_tst

compiler/sparc/prop.inc

@@ -0,0 +1,192 @@
+{*****************************************************************************}
+{ File                   : prop.inc                                           }
+{ Author                 : Mazen NEIFER                                       }
+{ Project                : Free Pascal Compiler (FPC)                         }
+{ Creation date          : 2002\26\26                                         }
+{ Last modification date : 2002\07\01                                         }
+{ Licence                : GPL                                                }
+{ Bug report             : [email protected]                        }
+{*****************************************************************************}
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_MEAX, Ch_WFlags, Ch_None)),
+(Ch: (Ch_MEAX, Ch_WFlags, Ch_None)),
+(Ch: (Ch_MEAX, Ch_WFlags, Ch_None)),
+(Ch: (Ch_MEAX, Ch_WFlags, Ch_None)),
+(Ch: (Ch_Mop2, Ch_Rop1, Ch_RWFlags)),
+(Ch: (Ch_Mop2, Ch_Rop1, Ch_WFlags)),
+(Ch: (Ch_Mop2, Ch_Rop1, Ch_WFlags)),
+(Ch: (Ch_WFlags, Ch_None, Ch_None)),
+(Ch: (Ch_Rop1, Ch_None, Ch_None)),
+(Ch: (Ch_Wop2, Ch_WFlags, Ch_Rop1)),
+(Ch: (Ch_Wop2, Ch_WFlags, Ch_Rop1)),
+(Ch: (Ch_MOp1, Ch_None, Ch_None)),
+(Ch: (Ch_WFlags, Ch_Rop1, Ch_Rop2)),
+(Ch: (Ch_Mop2, Ch_Rop1, Ch_WFlags)),
+(Ch: (Ch_Mop2, Ch_Rop1, Ch_WFlags)),
+(Ch: (Ch_Mop2, Ch_Rop1, Ch_WFlags)),
+(Ch: (Ch_ROp1, Ch_All, Ch_None)),
+(Ch: (Ch_MEAX, Ch_None, Ch_None)),
+(Ch: (Ch_MEAX, Ch_WEDX, Ch_None)),
+(Ch: (Ch_WFlags, Ch_None, Ch_None)),
+(Ch: (Ch_CDirFlag, Ch_None, Ch_None)),
+(Ch: (Ch_WFlags, Ch_None, Ch_None)),
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_WFlags, Ch_None, Ch_None)),
+(Ch: (Ch_ROp1, Ch_ROp2, Ch_WFlags)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_none)),
+(Ch: (Ch_MEAX, Ch_WEDX, Ch_None)),
+(Ch: (Ch_MEAX, Ch_None, Ch_None)),
+(Ch: (Ch_MEAX, Ch_None, Ch_None)),
+(Ch: (Ch_MEAX, Ch_None, Ch_None)),
+(Ch: (Ch_Mop1, Ch_WFlags, Ch_None)),
+(Ch: (Ch_RWEAX, Ch_WEDX, Ch_WFlags)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_RWESP, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_Rop1, Ch_FPU, Ch_None)),
+(Ch: (Ch_Wop1, Ch_FPU, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_RFLAGS, Ch_None)),
+(Ch: (Ch_FPU, Ch_RFLAGS, Ch_None)),
+(Ch: (Ch_FPU, Ch_RFLAGS, Ch_None)),
+(Ch: (Ch_FPU, Ch_RFLAGS, Ch_None)),
+(Ch: (Ch_FPU, Ch_RFLAGS, Ch_None)),
+(Ch: (Ch_FPU, Ch_RFLAGS, Ch_None)),
+(Ch: (Ch_FPU, Ch_RFLAGS, Ch_None)),
+(Ch: (Ch_FPU, Ch_RFLAGS, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_WFLAGS, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_WFLAGS, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_Wop1, Ch_None, Ch_None)),
+(Ch: (Ch_Wop1, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_FPU, Ch_ROp1, Ch_None)),
+(Ch: (Ch_Rop1, Ch_FPU, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_ROp1, Ch_FPU, Ch_None)),
+(Ch: (Ch_ROp1, Ch_FPU, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_Wop1, Ch_None, Ch_None)),
+(Ch: (Ch_Wop1, Ch_None, Ch_None)),
+(Ch: (Ch_Wop1, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_Wop1, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_Wop1, Ch_None, Ch_None)),
+(Ch: (Ch_Wop1, Ch_None, Ch_None)),
+(Ch: (Ch_Wop1, Ch_None, Ch_None)),
+(Ch: (Ch_Wop1, Ch_FPU, Ch_None)),
+(Ch: (Ch_Wop1, Ch_None, Ch_None)),
+(Ch: (Ch_ROp1, Ch_FPU, Ch_None)),
+(Ch: (Ch_ROp1, Ch_FPU, Ch_None)),
+(Ch: (Ch_ROp1, Ch_FPU, Ch_None)),
+(Ch: (Ch_ROp1, Ch_FPU, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_WFLAGS, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_WFLAGS, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_FPU, Ch_None, Ch_None)),
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_RWEAX, Ch_WEDX, Ch_WFlags)),
+(Ch: (Ch_RWEAX, Ch_WEDX, Ch_WFlags)),
+(Ch: (Ch_Wop2, Ch_Rop1, Ch_None)),
+(Ch: (Ch_Mop1, Ch_WFlags, Ch_None)),
+(Ch: (Ch_WMemEDI, Ch_RWEDI, Ch_REDX)),
+(Ch: (Ch_WMemEDI, Ch_RWEDI, Ch_REDX)),
+(Ch: (Ch_WMemEDI, Ch_RWEDI, Ch_REDX)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_RECX, Ch_None, Ch_None)),
+(Ch: (Ch_RECX, Ch_None, Ch_None)),
+(Ch: (Ch_ROp1, Ch_None, Ch_None)),
+(Ch: (Ch_WEAX, Ch_RFlags, Ch_None)),
+(Ch: (Ch_Wop2, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_Wop2, Ch_Rop1, Ch_None)),
+(Ch: (Ch_Wop2, Ch_Rop1, Ch_None)),
+(Ch: (Ch_RWESP, Ch_WEBP, Ch_None)),
+(Ch: (Ch_Wop2, Ch_Rop1, Ch_None)),
+(Ch: (Ch_Wop2, Ch_Rop1, Ch_None)),
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_Wop2, Ch_Rop1, Ch_None)),
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_ROp1, Ch_None, Ch_None)),
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_All, Ch_None, Ch_None)),
+(Ch: (Ch_None, Ch_None, Ch_None)),
+(Ch: (Ch_WEAX, Ch_RWESI, Ch_None)),
+(Ch: (Ch_WEAX, Ch_RWESI, Ch_None)),
+(Ch: (Ch_RWECX, Ch_None, Ch_None))

compiler/sparc/registers.inc

@@ -0,0 +1,50 @@
+{*****************************************************************************}
+{ File                   : registers.inc                                      }
+{ Author                 : Mazen NEIFER                                       }
+{ Project                : Free Pascal Compiler (FPC)                         }
+{ Creation date          : 2002\05\08                                         }
+{ Last modification date : 2002\07\24                                         }
+{ Licence                : GPL                                                }
+{ Bug report             : [email protected]                        }
+{*****************************************************************************}
+R_NO
+{General purpose global registers}
+,R_G0{This register is usually set to zero and used as a scratch register}
+,R_G1,R_G2,R_G3,R_G4,R_G5,R_G6,R_G7
+{General purpose out registers}
+,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_O6
+,R_O7{This register is used to save the address of the last CALL instruction}
+{General purpose local registers}
+,R_L0
+,R_L1{This register is used to save the Program Counter (PC) after a Trap}
+,R_L2{This register is used to save the Program Counter (nPC) after a Trap}
+,R_L3,R_L4,R_L5,R_L6,R_L7
+{General purpose in registers}
+,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_I6,R_I7
+{Floating point registers}
+,R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7
+,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15
+,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23
+,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31
+{Floating point status/"front of queue" registers}
+,R_FSR,R_FQ
+{Coprocessor registers}
+,R_C0,R_C1,R_C2,R_C3,R_C4,R_C5,R_C6,R_C7
+,R_C8,R_C9,R_C10,R_C11,R_C12,R_C13,R_C14,R_C15
+,R_C16,R_C17,R_C18,R_C19,R_C20,R_C21,R_C22,R_C23
+,R_C24,R_C25,R_C26,R_C27,R_C28,R_C29,R_C30,R_C31
+{Coprocessor status/queue registers}
+,R_CSR
+,R_CQ
+{Integer Unit control & status registers}
+,R_PSR{Processor Status Register : informs upon the program status}
+,R_TBR{Trap Base Register : saves the Trap vactor base address}
+,R_WIM{Window Invalid Mask : }
+,R_Y{Multiply/Devide Register : }
+{Ancillary State Registers : these are implementation dependent registers and
+thus, are not specified by the SPARC Reference Manual. I did choose the SUN's
+implementation according to the Assembler Refernce Manual.(MN)}
+,R_ASR0,R_ASR1,R_ASR2,R_ASR3,R_ASR4,R_ASR5,R_ASR6,R_ASR7
+,R_ASR8,R_ASR9,R_ASR10,R_ASR11,R_ASR12,R_ASR13,R_ASR14,R_ASR15
+,R_ASR16,R_ASR17,R_ASR18,R_ASR19,R_ASR20,R_ASR21,R_ASR22,R_ASR23
+,R_ASR24,R_ASR25,R_ASR26,R_ASR27,R_ASR28,R_ASR29,R_ASR30,R_ASR31

compiler/sparc/sparcatts.inc

@@ -0,0 +1,73 @@
+{*****************************************************************************}
+{ File                   : sparcatt.pas                                       }
+{ Author                 : Mazen NEIFER                                       }
+{ Project                : Free Pascal Compiler (FPC)                         }
+{ Creation date          : 2002\05\01                                         }
+{ Last modification date : 2002\07\03                                         }
+{ Licence                : GPL                                                }
+{ Bug report             : [email protected]                        }
+{*****************************************************************************}
+AttSufNONE{A_NONE},
+AttSufNONE{A_ABCD},
+AttSufNONE{A_ADD},AttSufNONE{A_ADDcc},AttSufNONE{A_ADDX},AttSufNONE{A_ADDXcc},
+AttSufNONE{A_AND},AttSufNONE{A_ANDcc},AttSufNONE{A_ANDN},AttSufNONE{A_ADDNcc},
+AttSufNONE{A_BN},AttSufNONE{A_BNE},AttSufNONE{A_BE},AttSufNONE{A_BG},AttSufNONE{A_BLE},AttSufNONE{A_BGE},AttSufNONE{A_BI},AttSufNONE{A_BGU},AttSufNONE{A_BLEU},AttSufNONE{A_BCC},
+AttSufNONE{A_BCS},AttSufNONE{A_BPOS},AttSufNONE{A_NEG},AttSufNONE{A_BVC},AttSufNONE{A_BVS},AttSufNONE{A_BA},
+AttSufNONE{A_CALL},
+AttSufNONE{A_CBccc},
+AttSufNONE{A_FBN},AttSufNONE{A_FBU},AttSufNONE{A_FBG},AttSufNONE{A_FBUG},AttSufNONE{A_FBL},AttSufNONE{A_FBUL},AttSufNONE{A_FBLG},AttSufNONE{A_FBNE},
+AttSufNONE{A_FBE},AttSufNONE{A_FBUE},AttSufNONE{A_FBGE},AttSufNONE{A_FBUGE},AttSufNONE{A_FBLE},AttSufNONE{A_FBULE},AttSufNONE{A_FBO},AttSufNONE{A_FBA},
+AttSufNONE{A_FLUSH},
+AttSufNONE{A_JMPL},
+AttSufNONE{A_LDSB},AttSufNONE{A_LDSH},AttSufNONE{A_LDSTUB},
+AttSufNONE{A_LDUB},AttSufNONE{A_LDUH},AttSufNONE{A_LD},AttSufNONE{A_LDD},AttSufNONE{A_LDF},AttSufNONE{A_LDFSR},AttSufNONE{A_LDDF},AttSufNONE{A_LDC},AttSufNONE{A_LDCSR},AttSufNONE{A_LDDC},
+AttSufNONE{A_LDSBA},AttSufNONE{A_LDSHA},AttSufNONE{A_LDUBA},AttSufNONE{A_LDUHA},AttSufNONE{A_LDA},AttSufNONE{A_LDDA},
+AttSufNONE{A_LDSTUBA},
+AttSufNONE{A_MULScc},
+AttSufNONE{A_NOP},
+AttSufNONE{A_OR},AttSufNONE{A_ORcc},AttSufNONE{A_ORN},AttSufNONE{A_ORNcc},
+AttSufNONE{A_RDASR},AttSufNONE{A_RDY},AttSufNONE{A_RDPSR},AttSufNONE{A_RDWIM},AttSufNONE{A_RDTBR},
+AttSufNONE{A_RESTORE},
+AttSufNONE{A_RET},
+AttSufNONE{A_SAVE},
+AttSufNONE{A_SDIV},AttSufNONE{A_SDIVcc},
+AttSufNONE{A_SMUL},AttSufNONE{A_SMULcc},
+AttSufNONE{A_SETHI},
+AttSufNONE{A_SLL},AttSufNONE{A_SRL},AttSufNONE{A_SRA},
+AttSufNONE{A_STB},AttSufNONE{A_STH},
+AttSufInt{A_ST},AttSufNONE{A_STD},AttSufNONE{A_STF},AttSufNONE{A_STDF},AttSufNONE{A_STFSR},AttSufNONE{A_STDFQ},
+AttSufNONE{A_STC},AttSufNONE{A_STDC},AttSufNONE{A_STCSR},AttSufNONE{A_STDCQ},
+AttSufNONE{A_STBA},AttSufNONE{A_STHA},AttSufNONE{A_STA},AttSufNONE{A_STDA},
+AttSufNONE{A_SUB},AttSufNONE{A_SUBcc},AttSufNONE{A_SUBX},AttSufNONE{A_SUBXcc},
+AttSufNONE{A_SWAP},AttSufNONE{A_SWAPA},AttSufNONE{A_Ticc},AttSufNONE{A_TADDcc},AttSufNONE{A_TSUBcc},AttSufNONE{A_TADDccTV},AttSufNONE{A_TSUBccTV},
+AttSufNONE{A_UDIV},AttSufNONE{A_UDIVcc},
+AttSufNONE{A_UMUL},AttSufNONE{A_UMULcc},
+AttSufNONE{A_UNMP},
+AttSufNONE{A_WRASR},AttSufNONE{A_WRY},AttSufNONE{A_WRPSR},AttSufNONE{A_WRWIM},AttSufNONE{A_WRTBR},
+AttSufNONE{A_XNOR},AttSufNONE{A_XNORcc},
+AttSufNONE{A_XOR},AttSufNONE{A_XORcc},
+          {Floating-point instructions}
+AttSufNONE{A_FiTOs},AttSufNONE{A_FiTOd},AttSufNONE{A_FiTOq},
+AttSufNONE{A_FsTOi},AttSufNONE{A_FdTOi},AttSufNONE{A_FqTOi},
+AttSufNONE{A_FsTOd},AttSufNONE{A_FsTOq},
+AttSufNONE{A_FdTOs},AttSufNONE{A_FdTOq},
+AttSufNONE{A_FqTOd},AttSufNONE{A_FqTOs},
+AttSufNONE{A_MOVs},AttSufNONE{A_NEGs},AttSufNONE{A_FABSs},
+AttSufNONE{A_FSQRTs},AttSufNONE{A_FSQRTd},AttSufNONE{A_FSQRTq},
+AttSufNONE{A_FADDs},AttSufNONE{A_FADDd},AttSufNONE{A_FADDq},
+AttSufNONE{A_FSUBs},AttSufNONE{A_FSUBd},AttSufNONE{A_FSUBq},
+AttSufNONE{A_FMULs},AttSufNONE{A_FMULd},AttSufNONE{A_FMULQ},
+AttSufNONE{A_FdMULq},AttSufNONE{A_FsMULd},
+AttSufNONE{A_DIVs},AttSufNONE{A_DIVd},AttSufNONE{A_FDIVq},
+AttSufNONE{A_FCMPs},AttSufNONE{A_FCMPd},AttSufNONE{A_FCMPq},
+AttSufNONE{A_FCPop1},AttSufNONE{A_CPop2},
+          {Synthetic instructions}
+AttSufNONE{A_btst},AttSufNONE{A_bset},AttSufNONE{A_bclr},AttSufNONE{A_btog},
+AttSufNONE{A_clr},AttSufNONE{A_clrb},AttSufNONE{A_clrh},
+AttSufNONE{A_CMP},
+AttSufNONE{A_dec},AttSufNONE{A_deccc},
+AttSufNONE{A_inc},AttSufNONE{A_inccc},
+AttSufNONE{A_not},
+AttSufNONE{A_set},
+AttSufNONE{A_skipz},AttSufNONE{A_skipnz},
+AttSufNONE{A_tst}

compiler/sparc/sparcins.dat

@@ -0,0 +1,2772 @@
+;*****************************************************************************;
+; File                   : sparcins.dat                                       ;
+; Author                 : Mazen NEIFER                                       ;
+; Company                : IPITEC (ATMEL Corporate)                           ;
+; Creation date          : 2002\04\17                                         ;
+; Last modification date : 2002\04\17                                         ;
+; Licence                : Copyright (C) IPITEC (ATMEL Corporate)             ;
+; Bug report             : [email protected]                        ;
+;*****************************************************************************;
+; Table of assembler instructions for Free Pascal
+; adapted from Netwide Assembler by Peter Vreman for I386 and SPARC by M.NEIFER
+;
+; The Netwide Assembler is copyright (C) 1996 Simon Tatham and
+; Julian Hall. All rights reserved.
+;
+; Layout
+; [OPCODE,attnameX]  (X means suffix in att name)
+; arguments   bytes   flags
+;
+
+[NONE]
+(Ch_None, Ch_None, Ch_None)
+void                  void                            none
+
+[AAA]
+(Ch_MEAX, Ch_WFlags, Ch_None)
+void                  \1\x37                          8086
+
+[AAD,aadX]
+(Ch_MEAX, Ch_WFlags, Ch_None)
+void                  \2\xD5\x0A                      8086
+imm                   \1\xD5\24                       8086,SB
+
+[AAM,aamX]
+(Ch_MEAX, Ch_WFlags, Ch_None)
+void                  \2\xD4\x0A                      8086
+imm                   \1\xD4\24                       8086,SB
+
+[AAS]
+(Ch_MEAX, Ch_WFlags, Ch_None)
+void                  \1\x3F                          8086
+
+[ADC,adcX]
+(Ch_Mop2, Ch_Rop1, Ch_RWFlags)
+mem,reg8              \300\1\x10\101                  8086,SM
+reg8,reg8             \300\1\x10\101                  8086
+mem,reg16             \320\300\1\x11\101              8086,SM
+reg16,reg16           \320\300\1\x11\101              8086
+mem,reg32             \321\300\1\x11\101              386,SM
+reg32,reg32           \321\300\1\x11\101              386
+reg8,mem              \301\1\x12\110                  8086,SM
+reg8,reg8             \301\1\x12\110                  8086
+reg16,mem             \320\301\1\x13\110              8086,SM
+reg16,reg16           \320\301\1\x13\110              8086
+reg32,mem             \321\301\1\x13\110              386,SM
+reg32,reg32           \321\301\1\x13\110              386
+rm16,imm8             \320\300\1\x83\202\15           8086
+rm32,imm8             \321\300\1\x83\202\15           386
+reg_al,imm            \1\x14\21                       8086,SM
+reg_ax,imm            \320\1\x15\31                   8086,SM
+reg_eax,imm           \321\1\x15\41                   386,SM
+rm8,imm               \300\1\x80\202\21               8086,SM
+rm16,imm              \320\300\1\x81\202\31           8086,SM
+rm32,imm              \321\300\1\x81\202\41           386,SM
+mem,imm8              \300\1\x80\202\21               8086,SM
+mem,imm16             \320\300\1\x81\202\31           8086,SM
+mem,imm32             \321\300\1\x81\202\41           386,SM
+
+[ADD,addX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+mem,reg8              \300\17\101                     8086,SM
+reg8,reg8             \300\17\101                     8086
+mem,reg16             \320\300\1\x01\101              8086,SM
+reg16,reg16           \320\300\1\x01\101              8086
+mem,reg32             \321\300\1\x01\101              386,SM
+reg32,reg32           \321\300\1\x01\101              386
+reg8,mem              \301\1\x02\110                  8086,SM
+reg8,reg8             \301\1\x02\110                  8086
+reg16,mem             \320\301\1\x03\110              8086,SM
+reg16,reg16           \320\301\1\x03\110              8086
+reg32,mem             \321\301\1\x03\110              386,SM
+reg32,reg32           \321\301\1\x03\110              386
+rm16,imm8             \320\300\1\x83\200\15           8086
+rm32,imm8             \321\300\1\x83\200\15           386
+reg_al,imm            \1\x04\21                       8086,SM
+reg_ax,imm            \320\1\x05\31                   8086,SM
+reg_eax,imm           \321\1\x05\41                   386,SM
+rm8,imm               \300\1\x80\200\21               8086,SM
+rm16,imm              \320\300\1\x81\200\31           8086,SM
+rm32,imm              \321\300\1\x81\200\41           386,SM
+mem,imm8              \300\1\x80\200\21               8086,SM
+mem,imm16             \320\300\1\x81\200\31           8086,SM
+mem,imm32             \321\300\1\x81\200\41           386,SM
+
+[AND,andX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+mem,reg8              \300\1\x20\101                  8086,SM
+reg8,reg8             \300\1\x20\101                  8086
+mem,reg16             \320\300\1\x21\101              8086,SM
+reg16,reg16           \320\300\1\x21\101              8086
+mem,reg32             \321\300\1\x21\101              386,SM
+reg32,reg32           \321\300\1\x21\101              386
+reg8,mem              \301\1\x22\110                  8086,SM
+reg8,reg8             \301\1\x22\110                  8086
+reg16,mem             \320\301\1\x23\110              8086,SM
+reg16,reg16           \320\301\1\x23\110              8086
+reg32,mem             \321\301\1\x23\110              386,SM
+reg32,reg32           \321\301\1\x23\110              386
+rm16,imm8             \320\300\1\x83\204\15           8086
+rm32,imm8             \321\300\1\x83\204\15           386
+reg_al,imm            \1\x24\21                       8086,SM
+reg_ax,imm            \320\1\x25\31                   8086,SM
+reg_eax,imm           \321\1\x25\41                   386,SM
+rm8,imm               \300\1\x80\204\21               8086,SM
+rm16,imm              \320\300\1\x81\204\31           8086,SM
+rm32,imm              \321\300\1\x81\204\41           386,SM
+mem,imm8              \300\1\x80\204\21               8086,SM
+mem,imm16             \320\300\1\x81\204\31           8086,SM
+mem,imm32             \321\300\1\x81\204\41           386,SM
+
+[ARPL,arplX]
+(Ch_WFlags, Ch_None, Ch_None)
+mem,reg16             \300\1\x63\101                  286,PROT,SM
+reg16,reg16           \300\1\x63\101                  286,PROT
+
+[BOUND,boundX]
+(Ch_Rop1, Ch_None, Ch_None)
+reg16,mem             \320\301\1\x62\110              186
+reg32,mem             \321\301\1\x62\110              386
+
+[BSF,bsfX]
+(Ch_Wop2, Ch_WFlags, Ch_Rop1)
+reg16,mem             \320\301\2\x0F\xBC\110          386,SM
+reg16,reg16           \320\301\2\x0F\xBC\110          386
+reg32,mem             \321\301\2\x0F\xBC\110          386,SM
+reg32,reg32           \321\301\2\x0F\xBC\110          386
+
+[BSR,bsrX]
+(Ch_Wop2, Ch_WFlags, Ch_Rop1)
+reg16,mem             \320\301\2\x0F\xBD\110          386,SM
+reg16,reg16           \320\301\2\x0F\xBD\110          386
+reg32,mem             \321\301\2\x0F\xBD\110          386,SM
+reg32,reg32           \321\301\2\x0F\xBD\110          386
+
+[BSWAP,bswapX]
+(Ch_MOp1, Ch_None, Ch_None)
+reg32                 \321\1\x0F\10\xC8               486
+
+[BT,btX]
+(Ch_WFlags, Ch_Rop1, Ch_Rop2)
+mem,reg16             \320\300\2\x0F\xA3\101          386,SM
+reg16,reg16           \320\300\2\x0F\xA3\101          386
+mem,reg32             \321\300\2\x0F\xA3\101          386,SM
+reg32,reg32           \321\300\2\x0F\xA3\101          386
+rm16,imm              \320\300\2\x0F\xBA\204\25       386,SB
+rm32,imm              \321\300\2\x0F\xBA\204\25       386,SB
+
+[BTC,btcX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+mem,reg16             \320\300\2\x0F\xBB\101          386,SM
+reg16,reg16           \320\300\2\x0F\xBB\101          386
+mem,reg32             \321\300\2\x0F\xBB\101          386,SM
+reg32,reg32           \321\300\2\x0F\xBB\101          386
+rm16,imm              \320\300\2\x0F\xBA\207\25       386,SB
+rm32,imm              \321\300\2\x0F\xBA\207\25       386,SB
+
+[BTR,btrX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+mem,reg16             \320\300\2\x0F\xB3\101          386,SM
+reg16,reg16           \320\300\2\x0F\xB3\101          386
+mem,reg32             \321\300\2\x0F\xB3\101          386,SM
+reg32,reg32           \321\300\2\x0F\xB3\101          386
+rm16,imm              \320\300\2\x0F\xBA\206\25       386,SB
+rm32,imm              \321\300\2\x0F\xBA\206\25       386,SB
+
+[BTS,btsX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+mem,reg16             \320\300\2\x0F\xAB\101          386,SM
+reg16,reg16           \320\300\2\x0F\xAB\101          386
+mem,reg32             \321\300\2\x0F\xAB\101          386,SM
+reg32,reg32           \321\300\2\x0F\xAB\101          386
+rm16,imm              \320\300\2\x0F\xBA\205\25       386,SB
+rm32,imm              \321\300\2\x0F\xBA\205\25       386,SB
+
+[CALL,call]
+; don't know value of any register
+(Ch_ROp1, Ch_All, Ch_None)
+imm                   \322\1\xE8\64                   8086
+imm|near              \322\1\xE8\64                   8086
+imm|far               \322\1\x9A\34\37                8086,ND
+imm16                 \320\1\xE8\64                   8086
+imm16|near            \320\1\xE8\64                   8086
+imm16|far             \320\1\x9A\34\37                8086,ND
+imm32                 \321\1\xE8\64                   8086
+imm32|near            \321\1\xE8\64                   8086
+imm32|far             \321\1\x9A\34\37                8086,ND
+imm:imm               \322\1\x9A\35\30                8086
+imm16:imm             \320\1\x9A\31\30                8086
+imm:imm16             \320\1\x9A\31\30                8086
+imm32:imm             \321\1\x9A\41\30                386
+imm:imm32             \321\1\x9A\41\30                386
+mem|far               \322\300\1\xFF\203              8086
+mem16|far             \320\300\1\xFF\203              8086
+mem32|far             \321\300\1\xFF\203              386
+mem|near              \322\300\1\xFF\202              8086
+mem16|near            \320\300\1\xFF\202              8086
+mem32|near            \321\300\1\xFF\202              386
+reg16                 \320\300\1\xFF\202              8086
+reg32                 \321\300\1\xFF\202              386
+mem                   \322\300\1\xFF\202              8086
+mem16                 \320\300\1\xFF\202              8086
+mem32                 \321\300\1\xFF\202              386
+
+[CBW,cbtw]
+(Ch_MEAX, Ch_None, Ch_None)
+void                  \320\1\x98                      8086
+
+[CDQ,cltd]
+(Ch_MEAX, Ch_WEDX, Ch_None)
+void                  \321\1\x99                      386
+
+[CLC]
+(Ch_WFlags, Ch_None, Ch_None)
+void                  \1\xF8                          8086
+
+[CLD]
+(Ch_CDirFlag, Ch_None, Ch_None)
+void                  \1\xFC                          8086
+
+[CLI]
+(Ch_WFlags, Ch_None, Ch_None)
+void                  \1\xFA                          8086
+
+[CLTS]
+(Ch_None, Ch_None, Ch_None)
+void                  \2\x0F\x06                      286,PRIV
+
+[CMC]
+(Ch_WFlags, Ch_None, Ch_None)
+void                  \1\xF5                          8086
+
+[CMP,cmpX]
+(Ch_ROp1, Ch_ROp2, Ch_WFlags)
+mem,reg8              \300\1\x38\101                  8086,SM
+reg8,reg8             \300\1\x38\101                  8086
+mem,reg16             \320\300\1\x39\101              8086,SM
+reg16,reg16           \320\300\1\x39\101              8086
+mem,reg32             \321\300\1\x39\101              386,SM
+reg32,reg32           \321\300\1\x39\101              386
+reg8,mem              \301\1\x3A\110                  8086,SM
+reg8,reg8             \301\1\x3A\110                  8086
+reg16,mem             \320\301\1\x3B\110              8086,SM
+reg16,reg16           \320\301\1\x3B\110              8086
+reg32,mem             \321\301\1\x3B\110              386,SM
+reg32,reg32           \321\301\1\x3B\110              386
+rm16,imm8             \320\300\1\x83\207\15           8086
+rm32,imm8             \321\300\1\x83\207\15           386
+reg_al,imm            \1\x3C\21                       8086,SM
+reg_ax,imm            \320\1\x3D\31                   8086,SM
+reg_eax,imm           \321\1\x3D\41                   386,SM
+rm8,imm               \300\1\x80\207\21               8086,SM
+rm16,imm              \320\300\1\x81\207\31           8086,SM
+rm32,imm              \321\300\1\x81\207\41           386,SM
+mem,imm8              \300\1\x80\207\21               8086,SM
+mem,imm16             \320\300\1\x81\207\31           8086,SM
+mem,imm32             \321\300\1\x81\207\41           386,SM
+
+[CMPSB]
+(Ch_All, Ch_None, Ch_None)
+void                  \332\1\xA6                      8086
+
+[CMPSD,cmpsl]
+(Ch_All, Ch_None, Ch_None)
+void                  \332\321\1\xA7                  386
+
+[CMPSW]
+(Ch_All, Ch_None, Ch_None)
+void                  \332\320\1\xA7                  8086
+
+[CMPXCHG,cmpxchgX]
+(Ch_All, Ch_None, Ch_None)
+mem,reg8              \300\2\x0F\xB0\101              PENT,SM
+reg8,reg8             \300\2\x0F\xB0\101              PENT
+mem,reg16             \320\300\2\x0F\xB1\101          PENT,SM
+reg16,reg16           \320\300\2\x0F\xB1\101          PENT
+mem,reg32             \321\300\2\x0F\xB1\101          PENT,SM
+reg32,reg32           \321\300\2\x0F\xB1\101          PENT
+
+[CMPXCHG486,cmpxchg486X]
+(Ch_All, Ch_None, Ch_None)
+mem,reg8              \300\2\x0F\xA6\101              486,SM,UNDOC
+reg8,reg8             \300\2\x0F\xA6\101              486,UNDOC
+mem,reg16             \320\300\2\x0F\xA7\101          486,SM,UNDOC
+reg16,reg16           \320\300\2\x0F\xA7\101          486,UNDOC
+mem,reg32             \321\300\2\x0F\xA7\101          486,SM,UNDOC
+reg32,reg32           \321\300\2\x0F\xA7\101          486,UNDOC
+
+[CMPXCHG8B,cmpxchg8bX]
+(Ch_All, Ch_None, Ch_None)
+mem                   \300\2\x0F\xC7\201              PENT
+
+[CPUID]
+(Ch_All, Ch_None, Ch_none)
+void                  \2\x0F\xA2                      PENT
+
+[CWD]
+(Ch_MEAX, Ch_WEDX, Ch_None)
+void                  \320\1\x99                      8086
+
+[CWDE,cwtl]
+(Ch_MEAX, Ch_None, Ch_None)
+void                  \321\1\x98                      386
+
+[DAA]
+(Ch_MEAX, Ch_None, Ch_None)
+void                  \1\x27                          8086
+
+[DAS]
+(Ch_MEAX, Ch_None, Ch_None)
+void                  \1\x2F                          8086
+
+[DEC,decX]
+(Ch_Mop1, Ch_WFlags, Ch_None)
+reg16                 \320\10\x48                     8086
+reg32                 \321\10\x48                     386
+rm8                   \300\1\xFE\201                  8086
+rm16                  \320\300\1\xFF\201              8086
+rm32                  \321\300\1\xFF\201              386
+
+[DIV,divX]
+(Ch_RWEAX, Ch_WEDX, Ch_WFlags)
+rm8                   \300\1\xF6\206                  8086
+rm16                  \320\300\1\xF7\206              8086
+rm32                  \321\300\1\xF7\206              386
+
+[EMMS]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\x0F\x77                      PENT,MMX
+
+[ENTER,enterX]
+(Ch_RWESP, Ch_None, Ch_None)
+imm,imm               \1\xC8\30\25                    186
+
+[F2XM1]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xF0                      8086,FPU
+
+[FABS]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xE1                      8086,FPU
+
+[FADD,faddF]
+(Ch_FPU, Ch_ROp1, Ch_None)
+mem32                 \300\1\xD8\200                  8086,FPU
+mem64                 \300\1\xDC\200                  8086,FPU
+void                  \2\xDE\xC1                      8086,FPU
+fpureg|to             \1\xDC\10\xC0                   8086,FPU
+fpureg,fpu0           \1\xDC\10\xC0                   8086,FPU
+fpureg                \1\xD8\10\xC0                   8086,FPU
+fpu0,fpureg           \1\xD8\11\xC0                   8086,FPU
+
+[FADDP,faddpF]
+(Ch_FPU, Ch_ROp1, Ch_None)
+void                  \2\xDE\xC1                      8086,FPU
+fpureg                \1\xDE\10\xC0                   8086,FPU
+fpureg,fpu0           \1\xDE\10\xC0                   8086,FPU
+
+[FBLD,fbldF]
+(Ch_Rop1, Ch_FPU, Ch_None)
+mem80                 \300\1\xDF\204                  8086,FPU
+mem                   \300\1\xDF\204                  8086,FPU
+
+[FBSTP,fbstpF]
+(Ch_Wop1, Ch_FPU, Ch_None)
+mem80                 \300\1\xDF\206                  8086,FPU
+mem                   \300\1\xDF\206                  8086,FPU
+
+[FCHS]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xE0                      8086,FPU
+
+[FCLEX]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \3\x9B\xDB\xE2                  8086,FPU
+
+[FCMOVB,fcmovbF]
+(Ch_FPU, Ch_RFLAGS, Ch_None)
+void                  \2\xDA\xC1                      P6,FPU
+fpureg                \1\xDA\10\xC0                   P6,FPU
+fpu0,fpureg           \1\xDA\11\xC0                   P6,FPU
+
+[FCMOVBE,fcmovbeF]
+(Ch_FPU, Ch_RFLAGS, Ch_None)
+void                  \2\xDA\xD1                      P6,FPU
+fpureg                \1\xDA\10\xD0                   P6,FPU
+fpu0,fpureg           \1\xDA\11\xD0                   P6,FPU
+
+[FCMOVE,fcmoveF]
+(Ch_FPU, Ch_RFLAGS, Ch_None)
+void                  \2\xDA\xC9                      P6,FPU
+fpureg                \1\xDA\10\xC8                   P6,FPU
+fpu0,fpureg           \1\xDA\11\xC8                   P6,FPU
+
+[FCMOVNB,fcmovnbF]
+(Ch_FPU, Ch_RFLAGS, Ch_None)
+void                  \2\xDB\xC1                      P6,FPU
+fpureg                \1\xDB\10\xC0                   P6,FPU
+fpu0,fpureg           \1\xDB\11\xC0                   P6,FPU
+
+[FCMOVNBE,fcmovnbeF]
+(Ch_FPU, Ch_RFLAGS, Ch_None)
+void                  \2\xDB\xD1                      P6,FPU
+fpureg                \1\xDB\10\xD0                   P6,FPU
+fpu0,fpureg           \1\xDB\11\xD0                   P6,FPU
+
+[FCMOVNE,fcmovneF]
+(Ch_FPU, Ch_RFLAGS, Ch_None)
+void                  \2\xDB\xC9                      P6,FPU
+fpureg                \1\xDB\10\xC8                   P6,FPU
+fpu0,fpureg           \1\xDB\11\xC8                   P6,FPU
+
+[FCMOVNU,fcmovnuF]
+(Ch_FPU, Ch_RFLAGS, Ch_None)
+void                  \2\xDB\xD9                      P6,FPU
+fpureg                \1\xDB\10\xD8                   P6,FPU
+fpu0,fpureg           \1\xDB\11\xD8                   P6,FPU
+
+[FCMOVU,fcmovuF]
+(Ch_FPU, Ch_RFLAGS, Ch_None)
+void                  \2\xDA\xD9                      P6,FPU
+fpureg                \1\xDA\10\xD8                   P6,FPU
+fpu0,fpureg           \1\xDA\11\xD8                   P6,FPU
+
+[FCOM,fcomF]
+(Ch_FPU, Ch_None, Ch_None)
+mem32                 \300\1\xD8\202                  8086,FPU
+mem64                 \300\1\xDC\202                  8086,FPU
+void                  \2\xD8\xD1                      8086,FPU
+fpureg                \1\xD8\10\xD0                   8086,FPU
+fpu0,fpureg           \1\xD8\11\xD0                   8086,FPU
+
+[FCOMI,fcomiF]
+(Ch_WFLAGS, Ch_None, Ch_None)
+void                  \2\xDB\xF1                      P6,FPU
+fpureg                \1\xDB\10\xF0                   P6,FPU
+fpu0,fpureg           \1\xDB\11\xF0                   P6,FPU
+
+[FCOMIP,fcomipF]
+(Ch_FPU, Ch_WFLAGS, Ch_None)
+void                  \2\xDF\xF1                      P6,FPU
+fpureg                \1\xDF\10\xF0                   P6,FPU
+fpu0,fpureg           \1\xDF\11\xF0                   P6,FPU
+
+[FCOMP,fcompF]
+(Ch_FPU, Ch_None, Ch_None)
+mem32                 \300\1\xD8\203                  8086,FPU
+mem64                 \300\1\xDC\203                  8086,FPU
+void                  \2\xD8\xD9                      8086,FPU
+fpureg                \1\xD8\10\xD8                   8086,FPU
+fpu0,fpureg           \1\xD8\11\xD8                   8086,FPU
+
+[FCOMPP]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xDE\xD9                      8086,FPU
+
+[FCOS]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xFF                      386,FPU
+
+[FDECSTP]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xF6                      8086,FPU
+
+[FDISI]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \3\x9B\xDB\xE1                  8086,FPU
+
+[FDIV,fdivF]
+(Ch_FPU, Ch_ROp1, Ch_None)
+mem32                 \300\1\xD8\206                  8086,FPU
+mem64                 \300\1\xDC\206                  8086,FPU
+void                  \2\xDC\xF1                      8086,FPU
+fpureg|to             \1\xDC\10\xF0                   8086,FPU
+fpureg,fpu0           \1\xDC\10\xF0                   8086,FPU
+fpureg                \1\xD8\10\xF0                   8086,FPU
+fpu0,fpureg           \1\xD8\11\xF0                   8086,FPU
+
+[FDIVP,fdivpF]
+(Ch_FPU, Ch_ROp1, Ch_None)
+void                  \2\xDE\xF1                      8086,FPU
+fpureg,fpu0           \1\xDE\10\xF0                   8086,FPU
+fpureg                \1\xDE\10\xF0                   8086,FPU
+
+[FDIVR,fdivrF]
+(Ch_FPU, Ch_ROp1, Ch_None)
+mem32                 \300\1\xD8\207                  8086,FPU
+mem64                 \300\1\xDC\207                  8086,FPU
+void                  \2\xDC\xF9                      8086,FPU
+fpureg|to             \1\xDC\10\xF8                   8086,FPU
+fpureg,fpu0           \1\xDC\10\xF8                   8086,FPU
+fpureg                \1\xD8\10\xF8                   8086,FPU
+fpu0,fpureg           \1\xD8\11\xF8                   8086,FPU
+
+[FDIVRP,fdivrpF]
+(Ch_FPU, Ch_ROp1, Ch_None)
+void                  \2\xDE\xF9                      8086,FPU
+fpureg                \1\xDE\10\xF8                   8086,FPU
+fpureg,fpu0           \1\xDE\10\xF8                   8086,FPU
+
+[FEMMS]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x0E                      PENT,3DNOW
+
+[FENI]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \3\x9B\xDB\xE0                  8086,FPU
+
+[FFREE]
+(Ch_FPU, Ch_None, Ch_None)
+fpureg                \1\xDD\10\xC0                   8086,FPU
+
+[FIADD,fiaddR]
+(Ch_FPU, Ch_ROp1, Ch_None)
+mem16                 \300\1\xDE\200                  8086,FPU
+mem32                 \300\1\xDA\200                  8086,FPU
+
+[FICOM,ficomR]
+(Ch_FPU, Ch_None, Ch_None)
+mem16                 \300\1\xDE\202                  8086,FPU
+mem32                 \300\1\xDA\202                  8086,FPU
+
+[FICOMP,ficompR]
+(Ch_FPU, Ch_None, Ch_None)
+mem16                 \300\1\xDE\203                  8086,FPU
+mem32                 \300\1\xDA\203                  8086,FPU
+
+[FIDIV,fidivR]
+(Ch_FPU, Ch_ROp1, Ch_None)
+mem16                 \300\1\xDE\206                  8086,FPU
+mem32                 \300\1\xDA\206                  8086,FPU
+
+[FIDIVR,fidivrR]
+(Ch_FPU, Ch_ROp1, Ch_None)
+mem16                 \300\1\xDE\207                  8086,FPU
+mem32                 \300\1\xDA\207                  8086,FPU
+
+[FILD,fildR]
+(Ch_FPU, Ch_ROp1, Ch_None)
+mem32                 \300\1\xDB\200                  8086,FPU
+mem16                 \320\300\1\xDF\200              8086,FPU
+mem64                 \300\1\xDF\205                  8086,FPU
+
+[FIMUL,fimulR]
+(Ch_FPU, Ch_ROp1, Ch_None)
+mem16                 \300\1\xDE\201                  8086,FPU
+mem32                 \300\1\xDA\201                  8086,FPU
+
+[FINCSTP]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xF7                      8086,FPU
+
+[FINIT]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \3\x9B\xDB\xE3                  8086,FPU
+
+[FIST,fistR]
+(Ch_Wop1, Ch_None, Ch_None)
+mem32                 \300\1\xDB\202                  8086,FPU
+mem16                 \320\300\1\xDF\202              8086,FPU
+
+[FISTP,fistpR]
+(Ch_Wop1, Ch_None, Ch_None)
+mem32                 \300\1\xDB\203                  8086,FPU
+mem16                 \320\300\1\xDF\203              8086,FPU
+mem64                 \300\1\xDF\207                  8086,FPU
+
+[FISUB,fisubR]
+(Ch_FPU, Ch_ROp1, Ch_None)
+mem16                 \300\1\xDE\204                  8086,FPU
+mem32                 \300\1\xDA\204                  8086,FPU
+
+[FISUBR,fisubrR]
+(Ch_FPU, Ch_ROp1, Ch_None)
+mem16                 \300\1\xDE\205                  8086,FPU
+mem32                 \300\1\xDA\205                  8086,FPU
+
+[FLD,fldF]
+(Ch_Rop1, Ch_FPU, Ch_None)
+mem32                 \300\1\xD9\200                  8086,FPU
+mem64                 \300\1\xDD\200                  8086,FPU
+mem80                 \300\1\xDB\205                  8086,FPU
+fpureg                \1\xD9\10\xC0                   8086,FPU
+
+[FLD1]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xE8                      8086,FPU
+
+[FLDCW,fldcwX]
+(Ch_FPU, Ch_None, Ch_None)
+mem                   \300\1\xD9\205                  8086,FPU,SW
+
+[FLDENV,fldenv]
+(Ch_FPU, Ch_None, Ch_None)
+mem                   \300\1\xD9\204                  8086,FPU
+
+[FLDL2E]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xEA                      8086,FPU
+
+[FLDL2T]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xE9                      8086,FPU
+
+[FLDLG2]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xEC                      8086,FPU
+
+[FLDLN2]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xED                      8086,FPU
+
+[FLDPI]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xEB                      8086,FPU
+
+[FLDZ]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xEE                      8086,FPU
+
+[FMUL,fmulF]
+(Ch_ROp1, Ch_FPU, Ch_None)
+mem32                 \300\1\xD8\201                  8086,FPU
+mem64                 \300\1\xDC\201                  8086,FPU
+void                  \2\xDC\xC9                      8086,FPU
+fpureg|to             \1\xDC\10\xC8                   8086,FPU
+fpureg,fpu0           \1\xDC\10\xC8                   8086,FPU
+fpureg                \1\xD8\10\xC8                   8086,FPU
+fpu0,fpureg           \1\xD8\11\xC8                   8086,FPU
+
+[FMULP,fmulpF]
+(Ch_ROp1, Ch_FPU, Ch_None)
+void                  \2\xDE\xC9                      8086,FPU
+fpureg                \1\xDE\10\xC8                   8086,FPU
+fpureg,fpu0           \1\xDE\10\xC8                   8086,FPU
+
+[FNCLEX]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xDB\xE2                      8086,FPU
+
+[FNDISI]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xDB\xE1                      8086,FPU
+
+[FNENI]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xDB\xE0                      8086,FPU
+
+[FNINIT]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xDB\xE3                      8086,FPU
+
+[FNOP]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xD0                      8086,FPU
+
+[FNSAVE,fnsave]
+(Ch_FPU, Ch_None, Ch_None)
+mem                   \300\1\xDD\206                  8086,FPU
+
+[FNSTCW,fnstcwX]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\1\xD9\207                  8086,FPU,SW
+
+[FNSTENV,fnstenv]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\1\xD9\206                  8086,FPU
+
+[FNSTSW,fnstswX]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\1\xDD\207                  8086,FPU,SW
+reg_ax                \2\xDF\xE0                      286,FPU
+
+[FPATAN]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xF3                      8086,FPU
+
+[FPREM]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xF8                      8086,FPU
+
+[FPREM1]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xF5                      386,FPU
+
+[FPTAN]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xF2                      8086,FPU
+
+[FRNDINT]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xFC                      8086,FPU
+
+[FRSTOR,frstor]
+(Ch_FPU, Ch_None, Ch_None)
+mem                   \300\1\xDD\204                  8086,FPU
+
+[FSAVE,fsave]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\2\x9B\xDD\206              8086,FPU
+
+[FSCALE]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xFD                      8086,FPU
+
+[FSETPM]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xDB\xE4                      286,FPU
+
+[FSIN]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xFE                      386,FPU
+
+[FSINCOS]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xFB                      386,FPU
+
+[FSQRT]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xFA                      8086,FPU
+
+[FST,fstF]
+(Ch_Wop1, Ch_None, Ch_None)
+mem32                 \300\1\xD9\202                  8086,FPU
+mem64                 \300\1\xDD\202                  8086,FPU
+fpureg                \1\xDD\10\xD0                   8086,FPU
+
+[FSTCW,fstcwX]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\2\x9B\xD9\207              8086,FPU,SW
+
+[FSTENV,fstenv]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\2\x9B\xD9\206              8086,FPU
+
+[FSTP,fstpF]
+(Ch_Wop1, Ch_FPU, Ch_None)
+mem32                 \300\1\xD9\203                  8086,FPU
+mem64                 \300\1\xDD\203                  8086,FPU
+mem80                 \300\1\xDB\207                  8086,FPU
+fpureg                \1\xDD\10\xD8                   8086,FPU
+
+[FSTSW,fstswX]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\2\x9B\xDD\207              8086,FPU,SW
+void                  \3\x9B\xDF\xE0                  286,FPU
+reg_ax                \3\x9B\xDF\xE0                  286,FPU
+
+[FSUB,fsubF]
+(Ch_ROp1, Ch_FPU, Ch_None)
+mem32                 \300\1\xD8\204                  8086,FPU
+mem64                 \300\1\xDC\204                  8086,FPU
+void                  \2\xDC\xE1                      8086,FPU
+fpureg|to             \1\xDC\10\xE0                   8086,FPU
+fpureg,fpu0           \1\xDC\10\xE0                   8086,FPU
+fpureg                \1\xD8\10\xE0                   8086,FPU
+fpu0,fpureg           \1\xD8\11\xE0                   8086,FPU
+
+[FSUBP,fsubpF]
+(Ch_ROp1, Ch_FPU, Ch_None)
+void                  \2\xDE\xE1                      8086,FPU
+fpureg                \1\xDE\10\xE0                   8086,FPU
+fpureg,fpu0           \1\xDE\10\xE0                   8086,FPU
+
+[FSUBR,fsubrF]
+(Ch_ROp1, Ch_FPU, Ch_None)
+mem32                 \300\1\xD8\205                  8086,FPU
+mem64                 \300\1\xDC\205                  8086,FPU
+void                  \2\xDC\xE9                      8086,FPU
+fpureg|to             \1\xDC\10\xE8                   8086,FPU
+fpureg,fpu0           \1\xDC\10\xE8                   8086,FPU
+fpureg                \1\xD8\10\xE8                   8086,FPU
+fpu0,fpureg           \1\xD8\11\xE8                   8086,FPU
+
+[FSUBRP,fsubrpF]
+(Ch_ROp1, Ch_FPU, Ch_None)
+void                  \2\xDE\xE9                      8086,FPU
+fpureg                \1\xDE\10\xE8                   8086,FPU
+fpureg,fpu0           \1\xDE\10\xE8                   8086,FPU
+
+[FTST]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xE4                      8086,FPU
+
+[FUCOM,fucomF]
+(Ch_None, Ch_None, Ch_None)
+void                  \2\xDD\xE1                      386,FPU
+fpureg                \1\xDD\10\xE0                   386,FPU
+fpu0,fpureg           \1\xDD\11\xE0                   386,FPU
+
+[FUCOMI,fucomiF]
+(Ch_WFLAGS, Ch_None, Ch_None)
+void                  \2\xDB\xE9                      P6,FPU
+fpureg                \1\xDB\10\xE8                   P6,FPU
+fpu0,fpureg           \1\xDB\11\xE8                   P6,FPU
+
+[FUCOMIP,fucomipF]
+(Ch_FPU, Ch_WFLAGS, Ch_None)
+void                  \2\xDF\xE9                      P6,FPU
+fpureg                \1\xDF\10\xE8                   P6,FPU
+fpu0,fpureg           \1\xDF\11\xE8                   P6,FPU
+
+[FUCOMP,fucompF]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xDD\xE9                      386,FPU
+fpureg                \1\xDD\10\xE8                   386,FPU
+fpu0,fpureg           \1\xDD\11\xE8                   386,FPU
+
+[FUCOMPP]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xDA\xE9                      386,FPU
+
+[FWAIT]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \1\x9B                          8086,FPU
+
+[FXAM]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xE5                      8086,FPU
+
+[FXCH,fxchF]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xC9                      8086,FPU
+fpureg                \1\xD9\10\xC8                   8086,FPU
+fpureg,fpu0           \1\xD9\10\xC8                   8086,FPU
+fpu0,fpureg           \1\xD9\11\xC8                   8086,FPU
+
+[FXTRACT]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xF4                      8086,FPU
+
+[FYL2X]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xF1                      8086,FPU
+
+[FYL2XP1]
+(Ch_FPU, Ch_None, Ch_None)
+void                  \2\xD9\xF9                      8086,FPU
+
+[HLT]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\xF4                          8086,PRIV
+
+[IBTS,ibtsX]
+(Ch_All, Ch_None, Ch_None)
+mem,reg16             \320\300\2\x0F\xA7\101          386,SW,UNDOC,ND
+reg16,reg16           \320\300\2\x0F\xA7\101          386,UNDOC,ND
+mem,reg32             \321\300\2\x0F\xA7\101          386,SD,UNDOC,ND
+reg32,reg32           \321\300\2\x0F\xA7\101          386,UNDOC,ND
+
+[ICEBP]
+(Ch_All, Ch_None, Ch_None)
+void                  \1\xF1                          386,ND
+
+[IDIV,idivX]
+(Ch_RWEAX, Ch_WEDX, Ch_WFlags)
+rm8                   \300\1\xF6\207                  8086
+rm16                  \320\300\1\xF7\207              8086
+rm32                  \321\300\1\xF7\207              386
+
+[IMUL,imulX]
+(Ch_RWEAX, Ch_WEDX, Ch_WFlags)
+rm8                   \300\1\xF6\205                  8086
+rm16                  \320\300\1\xF7\205              8086
+rm32                  \321\300\1\xF7\205              386
+reg16,mem             \320\301\2\x0F\xAF\110          386,SM
+reg16,reg16           \320\301\2\x0F\xAF\110          386
+reg32,mem             \321\301\2\x0F\xAF\110          386,SM
+reg32,reg32           \321\301\2\x0F\xAF\110          386
+reg16,mem,imm8        \320\301\1\x6B\110\16           286,SM
+reg16,reg16,imm8      \320\301\1\x6B\110\16           286
+reg16,mem,imm         \320\301\1\x69\110\32           286,SM
+reg16,reg16,imm       \320\301\1\x69\110\32           286,SM
+reg32,mem,imm8        \321\301\1\x6B\110\16           386,SM
+reg32,reg32,imm8      \321\301\1\x6B\110\16           386
+reg32,mem,imm         \321\301\1\x69\110\42           386,SM
+reg32,reg32,imm       \321\301\1\x69\110\42           386,SM
+reg16,imm8            \320\1\x6B\100\15               286
+reg16,imm             \320\1\x69\100\31               286,SM
+reg32,imm8            \321\1\x6B\100\15               386
+reg32,imm             \321\1\x69\100\41               386,SM
+
+[IN,inX]
+(Ch_Wop2, Ch_Rop1, Ch_None)
+reg_al,imm            \1\xE4\25                       8086,SB
+reg_ax,imm            \320\1\xE5\25                   8086,SB
+reg_eax,imm           \321\1\xE5\25                   386,SB
+reg_al,reg_dx         \1\xEC                          8086
+reg_ax,reg_dx         \320\1\xED                      8086
+reg_eax,reg_dx        \321\1\xED                      386
+
+[INC,incX]
+(Ch_Mop1, Ch_WFlags, Ch_None)
+reg16                 \320\10\x40                     8086
+reg32                 \321\10\x40                     386
+rm8                   \300\1\xFE\200                  8086
+rm16                  \320\300\1\xFF\200              8086
+rm32                  \321\300\1\xFF\200              386
+
+[INSB]
+(Ch_WMemEDI, Ch_RWEDI, Ch_REDX)
+void                  \1\x6C                          186
+
+[INSD,insl]
+(Ch_WMemEDI, Ch_RWEDI, Ch_REDX)
+void                  \321\1\x6D                      386
+
+[INSW]
+(Ch_WMemEDI, Ch_RWEDI, Ch_REDX)
+void                  \320\1\x6D                      186
+
+[INT]
+(Ch_All, Ch_None, Ch_None)
+imm                   \1\xCD\24                       8086,SB
+
+[INT01]
+(Ch_All, Ch_None, Ch_None)
+void                  \1\xF1                          386,ND
+
+[INT1]
+(Ch_All, Ch_None, Ch_None)
+void                  \1\xF1                          386
+
+[INT03]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\xCC                          8086,ND
+
+[INT3]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\xCC                          8086
+
+[INTO]
+(Ch_All, Ch_None, Ch_None)
+void                  \1\xCE                          8086
+
+[INVD]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x08                      486,PRIV
+
+[INVLPG,invlpgX]
+(Ch_All, Ch_None, Ch_None)
+mem                   \300\2\x0F\x01\207              486,PRIV
+
+[IRET]
+(Ch_All, Ch_None, Ch_None)
+void                  \322\1\xCF                      8086
+
+[IRETD,iret]
+(Ch_All, Ch_None, Ch_None)
+void                  \321\1\xCF                      386
+
+[IRETW]
+(Ch_All, Ch_None, Ch_None)
+void                  \320\1\xCF                      8086
+
+[JCXZ]
+(Ch_RECX, Ch_None, Ch_None)
+imm                   \320\1\xE3\50                   8086
+
+[JECXZ]
+(Ch_RECX, Ch_None, Ch_None)
+imm                   \321\1\xE3\50                   386
+
+[JMP,jmpX]
+(Ch_ROp1, Ch_None, Ch_None)
+imm|short             \1\xEB\50                       8086
+imm                   \322\1\xE9\64                   8086,PASS2
+imm|near              \322\1\xE9\64                   8086,ND,PASS2
+imm|far               \322\1\xEA\34\37                8086,ND
+imm16                 \320\1\xE9\64                   8086,PASS2
+imm16|near            \320\1\xE9\64                   8086,ND,PASS2
+imm16|far             \320\1\xEA\34\37                8086,ND,PASS2
+imm32                 \321\1\xE9\64                   8086,PASS2
+imm32|near            \321\1\xE9\64                   8086,ND,PASS2
+imm32|far             \321\1\xEA\34\37                8086,ND,PASS2
+imm:imm               \322\1\xEA\35\30                8086
+imm16:imm             \320\1\xEA\31\30                8086
+imm:imm16             \320\1\xEA\31\30                8086
+imm32:imm             \321\1\xEA\41\30                386
+imm:imm32             \321\1\xEA\41\30                386
+mem|far               \322\300\1\xFF\205              8086
+mem16|far             \320\300\1\xFF\205              8086
+mem32|far             \321\300\1\xFF\205              386
+mem|near              \322\300\1\xFF\204              8086
+mem16|near            \320\300\1\xFF\204              8086
+mem32|near            \321\300\1\xFF\204              386
+reg16                 \320\300\1\xFF\204              8086
+reg32                 \321\300\1\xFF\204              386
+mem                   \322\300\1\xFF\204              8086
+mem16                 \320\300\1\xFF\204              8086
+mem32                 \321\300\1\xFF\204              386
+
+[LAHF]
+(Ch_WEAX, Ch_RFlags, Ch_None)
+void                  \1\x9F                          8086
+
+[LAR,larX]
+(Ch_Wop2, Ch_None, Ch_None)
+reg16,mem             \320\301\2\x0F\x02\110          286,PROT,SM
+reg16,reg16           \320\301\2\x0F\x02\110          286,PROT
+reg32,mem             \321\301\2\x0F\x02\110          286,PROT,SM
+reg32,reg32           \321\301\2\x0F\x02\110          286,PROT
+
+[LCALL,lcall]
+; don't know value of any register
+(Ch_All, Ch_None, Ch_None)
+mem|far               \322\300\1\xFF\203              8086
+mem16|far             \320\300\1\xFF\203              8086
+mem32|far             \321\300\1\xFF\203              386
+mem|near              \322\300\1\xFF\202              8086
+mem16|near            \320\300\1\xFF\202              8086
+mem32|near            \321\300\1\xFF\202              386
+reg16                 \320\300\1\xFF\202              8086
+reg32                 \321\300\1\xFF\202              386
+mem                   \322\300\1\xFF\202              8086
+mem16                 \320\300\1\xFF\202              8086
+mem32                 \321\300\1\xFF\202              386
+
+[LDS,ldsX]
+(Ch_Wop2, Ch_Rop1, Ch_None)
+reg16,mem             \320\301\1\xC5\110              8086
+reg32,mem             \321\301\1\xC5\110              8086
+
+[LEA,leaX]
+(Ch_Wop2, Ch_Rop1, Ch_None)
+reg16,mem             \320\301\1\x8D\110              8086
+reg32,mem             \321\301\1\x8D\110              8086
+reg32,imm32           \321\301\1\x8D\110              8086
+
+[LEAVE]
+(Ch_RWESP, Ch_WEBP, Ch_None)
+void                  \1\xC9                          186
+
+[LES,lesX]
+(Ch_Wop2, Ch_Rop1, Ch_None)
+reg16,mem             \320\301\1\xC4\110              8086
+reg32,mem             \321\301\1\xC4\110              8086
+
+[LFS,lfsX]
+(Ch_Wop2, Ch_Rop1, Ch_None)
+reg16,mem             \320\301\2\x0F\xB4\110          386
+reg32,mem             \321\301\2\x0F\xB4\110          386
+
+[LGDT,lgdtX]
+(Ch_None, Ch_None, Ch_None)
+mem                   \300\2\x0F\x01\202              286,PRIV
+
+[LGS,lgsX]
+(Ch_Wop2, Ch_Rop1, Ch_None)
+reg16,mem             \320\301\2\x0F\xB5\110          386
+reg32,mem             \321\301\2\x0F\xB5\110          386
+
+[LIDT,lidtX]
+(Ch_None, Ch_None, Ch_None)
+mem                   \300\2\x0F\x01\203              286,PRIV
+
+[LJMP,ljmp]
+(Ch_ROp1, Ch_None, Ch_None)
+mem|far               \322\300\1\xFF\205              8086
+mem16|far             \320\300\1\xFF\205              8086
+mem32|far             \321\300\1\xFF\205              386
+mem|near              \322\300\1\xFF\204              8086
+mem16|near            \320\300\1\xFF\204              8086
+mem32|near            \321\300\1\xFF\204              386
+reg16                 \320\300\1\xFF\204              8086
+reg32                 \321\300\1\xFF\204              386
+mem                   \322\300\1\xFF\204              8086
+mem16                 \320\300\1\xFF\204              8086
+mem32                 \321\300\1\xFF\204              386
+
+[LLDT,lldtX]
+(Ch_None, Ch_None, Ch_None)
+mem                   \300\1\x0F\17\202               286,PROT,PRIV
+mem16                 \300\1\x0F\17\202               286,PROT,PRIV
+reg16                 \300\1\x0F\17\202               286,PROT,PRIV
+
+[LMSW,lmswX]
+(Ch_None, Ch_None, Ch_None)
+mem                   \300\2\x0F\x01\206              286,PRIV
+mem16                 \300\2\x0F\x01\206              286,PRIV
+reg16                 \300\2\x0F\x01\206              286,PRIV
+
+[LOADALL]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x07                      386,UNDOC
+
+[LOADALL286]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x05                      286,UNDOC
+
+[LOCK]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\xF0                          8086,PRE
+
+[LODSB]
+(Ch_WEAX, Ch_RWESI, Ch_None)
+void                  \1\xAC                          8086
+
+[LODSD,lodsl]
+(Ch_WEAX, Ch_RWESI, Ch_None)
+void                  \321\1\xAD                      386
+
+[LODSW]
+(Ch_WEAX, Ch_RWESI, Ch_None)
+void                  \320\1\xAD                      8086
+
+[LOOP]
+(Ch_RWECX, Ch_None, Ch_None)
+imm                   \312\1\xE2\50                   8086
+imm,reg_cx            \310\1\xE2\50                   8086
+imm,reg_ecx           \311\1\xE2\50                   386
+
+[LOOPE]
+(Ch_RWECX, Ch_RFlags, Ch_None)
+imm                   \312\1\xE1\50                   8086
+imm,reg_cx            \310\1\xE1\50                   8086
+imm,reg_ecx           \311\1\xE1\50                   386
+
+[LOOPNE]
+(Ch_RWECX, Ch_RFlags, Ch_None)
+imm                   \312\1\xE0\50                   8086
+imm,reg_cx            \310\1\xE0\50                   8086
+imm,reg_ecx           \311\1\xE0\50                   386
+
+[LOOPNZ]
+(Ch_RWECX, Ch_RFlags, Ch_None)
+imm                   \312\1\xE0\50                   8086
+imm,reg_cx            \310\1\xE0\50                   8086
+imm,reg_ecx           \311\1\xE0\50                   386
+
+[LOOPZ]
+(Ch_RWECX, Ch_RFlags, Ch_None)
+imm                   \312\1\xE1\50                   8086
+imm,reg_cx            \310\1\xE1\50                   8086
+imm,reg_ecx           \311\1\xE1\50                   386
+
+[LSL,lslX]
+(Ch_Wop2, Ch_WFlags, Ch_None)
+reg16,mem             \320\301\2\x0F\x03\110          286,PROT,SM
+reg16,reg16           \320\301\2\x0F\x03\110          286,PROT
+reg32,mem             \321\301\2\x0F\x03\110          286,PROT,SM
+reg32,reg32           \321\301\2\x0F\x03\110          286,PROT
+
+[LSS,lssX]
+(Ch_Wop2, Ch_ROP1, Ch_None)
+reg16,mem             \320\301\2\x0F\xB2\110          386
+reg32,mem             \321\301\2\x0F\xB2\110          386
+
+[LTR,ltrX]
+(Ch_None, Ch_None, Ch_None)
+mem                   \300\1\x0F\17\203               286,PROT,PRIV
+mem16                 \300\1\x0F\17\203               286,PROT,PRIV
+reg16                 \300\1\x0F\17\203               286,PROT,PRIV
+
+[MOV,movX]
+(Ch_Wop2, Ch_Rop1, Ch_None)
+mem,reg_cs            \320\300\1\x8C\201              8086,SM
+mem,reg_dess          \320\300\1\x8C\101              8086,SM
+mem,reg_fsgs          \320\300\1\x8C\101              386,SM
+reg16,reg_cs          \320\300\1\x8C\201              8086
+reg16,reg_dess        \320\300\1\x8C\101              8086
+reg16,reg_fsgs        \320\300\1\x8C\101              386
+rm32,reg_cs           \321\300\1\x8C\201              8086
+rm32,reg_dess         \321\300\1\x8C\101              8086
+rm32,reg_fsgs         \321\300\1\x8C\101              386
+reg_dess,mem          \320\301\1\x8E\110              8086,SM
+reg_fsgs,mem          \320\301\1\x8E\110              386,SM
+reg_dess,reg16        \320\301\1\x8E\110              8086
+reg_fsgs,reg16        \320\301\1\x8E\110              386
+reg_dess,rm32         \321\301\1\x8E\110              8086
+reg_fsgs,rm32         \321\301\1\x8E\110              386
+reg_al,mem_offs       \301\1\xA0\35                   8086,SM
+reg_ax,mem_offs       \301\320\1\xA1\35               8086,SM
+reg_eax,mem_offs      \301\321\1\xA1\35               386,SM
+mem_offs,reg_al       \300\1\xA2\34                   8086,SM
+mem_offs,reg_ax       \300\320\1\xA3\34               8086,SM
+mem_offs,reg_eax      \300\321\1\xA3\34               386,SM
+reg32,reg_cr4         \2\x0F\x20\204                  PENT,PRIV
+reg32,reg_creg        \2\x0F\x20\101                  386,PRIV
+reg32,reg_dreg        \2\x0F\x21\101                  386,PRIV
+reg32,reg_treg        \2\x0F\x24\101                  386,PRIV
+reg_cr4,reg32         \2\x0F\x22\214                  PENT,PRIV
+reg_creg,reg32        \2\x0F\x22\110                  386,PRIV
+reg_dreg,reg32        \2\x0F\x23\110                  386,PRIV
+reg_treg,reg32        \2\x0F\x26\110                  386,PRIV
+mem,reg8              \300\1\x88\101                  8086,SM
+reg8,reg8             \300\1\x88\101                  8086
+mem,reg16             \320\300\1\x89\101              8086,SM
+reg16,reg16           \320\300\1\x89\101              8086
+mem,reg32             \321\300\1\x89\101              386,SM
+reg32,reg32           \321\300\1\x89\101              386
+reg8,mem              \301\1\x8A\110                  8086,SM
+reg8,reg8             \301\1\x8A\110                  8086
+reg16,mem             \320\301\1\x8B\110              8086,SM
+reg16,reg16           \320\301\1\x8B\110              8086
+reg32,mem             \321\301\1\x8B\110              386,SM
+reg32,reg32           \321\301\1\x8B\110              386
+reg8,imm              \10\xB0\21                      8086,SM
+reg16,imm             \320\10\xB8\31                  8086,SM
+reg32,imm             \321\10\xB8\41                  386,SM
+rm8,imm               \300\1\xC6\200\21               8086,SM
+rm16,imm              \320\300\1\xC7\200\31           8086,SM
+rm32,imm              \321\300\1\xC7\200\41           386,SM
+mem,imm8              \300\1\xC6\200\21               8086,SM
+mem,imm16             \320\300\1\xC7\200\31           8086,SM
+mem,imm32             \321\300\1\xC7\200\41           386,SM
+
+[MOVD,movd]
+(Ch_Rop1, Ch_Wop2, Ch_None)
+mmxreg,mem            \301\2\x0F\x6E\110              PENT,MMX,SD
+mmxreg,reg32          \2\x0F\x6E\110                  PENT,MMX
+mem,mmxreg            \300\2\x0F\x7E\101              PENT,MMX,SD
+reg32,mmxreg          \2\x0F\x7E\101                  PENT,MMX
+
+[MOVQ,movq]
+(Ch_Rop1, Ch_Wop2, Ch_None)
+mmxreg,mem            \301\2\x0F\x6F\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x6F\110                  PENT,MMX
+mem,mmxreg            \300\2\x0F\x7F\101              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x7F\101                  PENT,MMX
+
+[MOVSB]
+(Ch_All, Ch_Rop1, Ch_None)
+void                  \1\xA4                          8086
+
+[MOVSD,movsl]
+(Ch_All, Ch_None, Ch_None)
+void                  \321\1\xA5                      386
+
+[MOVSW]
+(Ch_All, Ch_None, Ch_None)
+void                  \320\1\xA5                      8086
+
+[MOVSX,movsX]
+(Ch_Wop2, Ch_Rop1, Ch_None)
+reg16,mem             \320\301\2\x0F\xBE\110          386,SB
+reg16,reg8            \320\301\2\x0F\xBE\110          386
+reg32,rm8             \321\301\2\x0F\xBE\110          386
+reg32,rm16            \321\301\2\x0F\xBF\110          386
+
+[MOVZX,movzX]
+(Ch_Wop2, Ch_Rop1, Ch_None)
+reg16,mem             \320\301\2\x0F\xB6\110          386,SB
+reg16,reg8            \320\301\2\x0F\xB6\110          386
+reg32,rm8             \321\301\2\x0F\xB6\110          386
+reg32,rm16            \321\301\2\x0F\xB7\110          386
+
+[MUL,mulX]
+(Ch_RWEAX, Ch_WEDX, Ch_WFlags)
+rm8                   \300\1\xF6\204                  8086
+rm16                  \320\300\1\xF7\204              8086
+rm32                  \321\300\1\xF7\204              386
+
+[NEG,negX]
+(Ch_Mop1, Ch_None, Ch_None)
+rm8                   \300\1\xF6\203                  8086
+rm16                  \320\300\1\xF7\203              8086
+rm32                  \321\300\1\xF7\203              386
+
+[NOP]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\x90                          8086
+
+[NOT,notX]
+(Ch_Mop1, Ch_WFlags, Ch_None)
+rm8                   \300\1\xF6\202                  8086
+rm16                  \320\300\1\xF7\202              8086
+rm32                  \321\300\1\xF7\202              386
+
+[OR,orX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+mem,reg8              \300\1\x08\101                  8086,SM
+reg8,reg8             \300\1\x08\101                  8086
+mem,reg16             \320\300\1\x09\101              8086,SM
+reg16,reg16           \320\300\1\x09\101              8086
+mem,reg32             \321\300\1\x09\101              386,SM
+reg32,reg32           \321\300\1\x09\101              386
+reg8,mem              \301\1\x0A\110                  8086,SM
+reg8,reg8             \301\1\x0A\110                  8086
+reg16,mem             \320\301\1\x0B\110              8086,SM
+reg16,reg16           \320\301\1\x0B\110              8086
+reg32,mem             \321\301\1\x0B\110              386,SM
+reg32,reg32           \321\301\1\x0B\110              386
+rm16,imm8             \320\300\1\x83\201\15           8086
+rm32,imm8             \321\300\1\x83\201\15           386
+reg_al,imm            \1\x0C\21                       8086,SM
+reg_ax,imm            \320\1\x0D\31                   8086,SM
+reg_eax,imm           \321\1\x0D\41                   386,SM
+rm8,imm               \300\1\x80\201\21               8086,SM
+rm16,imm              \320\300\1\x81\201\31           8086,SM
+rm32,imm              \321\300\1\x81\201\41           386,SM
+mem,imm8              \300\1\x80\201\21               8086,SM
+mem,imm16             \320\300\1\x81\201\31           8086,SM
+mem,imm32             \321\300\1\x81\201\41           386,SM
+
+[OUT,outX]
+(Ch_Rop1, Ch_Rop2, Ch_None)
+imm,reg_al            \1\xE6\24                       8086,SB
+imm,reg_ax            \320\1\xE7\24                   8086,SB
+imm,reg_eax           \321\1\xE7\24                   386,SB
+reg_dx,reg_al         \1\xEE                          8086
+reg_dx,reg_ax         \320\1\xEF                      8086
+reg_dx,reg_eax        \321\1\xEF                      386
+
+[OUTSB]
+(Ch_All, Ch_None, Ch_None)
+void                  \1\x6E                          186
+
+[OUTSD,outsl]
+(Ch_All, Ch_None, Ch_None)
+void                  \321\1\x6F                      386
+
+[OUTSW]
+(Ch_All, Ch_None, Ch_None)
+void                  \320\1\x6F                      186
+
+[PACKSSDW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x6B\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x6B\110                  PENT,MMX
+
+[PACKSSWB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x63\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x63\110                  PENT,MMX
+
+[PACKUSWB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x67\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x67\110                  PENT,MMX
+
+[PADDB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xFC\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xFC\110                  PENT,MMX
+
+[PADDD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xFE\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xFE\110                  PENT,MMX
+
+[PADDSB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xEC\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xEC\110                  PENT,MMX
+
+[PADDSIW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x51\110              PENT,MMX,SM,CYRIX
+mmxreg,mmxreg         \2\x0F\x51\110                  PENT,MMX,CYRIX
+
+[PADDSW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xED\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xED\110                  PENT,MMX
+
+[PADDUSB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xDC\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xDC\110                  PENT,MMX
+
+[PADDUSW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xDD\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xDD\110                  PENT,MMX
+
+[PADDW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xFD\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xFD\110                  PENT,MMX
+
+[PAND]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xDB\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xDB\110                  PENT,MMX
+
+[PANDN]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xDF\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xDF\110                  PENT,MMX
+
+[PAVEB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x50\110              PENT,MMX,SM,CYRIX
+mmxreg,mmxreg         \2\x0F\x50\110                  PENT,MMX,CYRIX
+
+[PAVGUSB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xBF       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xBF           PENT,3DNOW
+
+[PCMPEQB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x74\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x74\110                  PENT,MMX
+
+[PCMPEQD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x76\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x76\110                  PENT,MMX
+
+[PCMPEQW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x75\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x75\110                  PENT,MMX
+
+[PCMPGTB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x64\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x64\110                  PENT,MMX
+
+[PCMPGTD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x66\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x66\110                  PENT,MMX
+
+[PCMPGTW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x65\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x65\110                  PENT,MMX
+
+[PDISTIB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x54\110              PENT,MMX,SM,CYRIX
+
+[PF2ID]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x1D       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x1D           PENT,3DNOW
+
+[PFACC]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xAE       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xAE           PENT,3DNOW
+
+[PFADD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x9E       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x9E           PENT,3DNOW
+
+[PFCMPEQ]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xB0       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xB0           PENT,3DNOW
+
+[PFCMPGE]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x90       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x90           PENT,3DNOW
+
+[PFCMPGT]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xA0       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xA0           PENT,3DNOW
+
+[PFMAX]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xA4       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xA4           PENT,3DNOW
+
+[PFMIN]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x94       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x94           PENT,3DNOW
+
+[PFMUL]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xB4       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xB4           PENT,3DNOW
+
+[PFRCP]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x96       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x96           PENT,3DNOW
+
+[PFRCPIT1]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xA6       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xA6           PENT,3DNOW
+
+[PFRCPIT2]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xB6       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xB6           PENT,3DNOW
+
+[PFRSQIT1]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xA7       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xA7           PENT,3DNOW
+
+[PFRSQRT]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x97       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x97           PENT,3DNOW
+
+[PFSUB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x9A       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x9A           PENT,3DNOW
+
+[PFSUBR]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xAA       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xAA           PENT,3DNOW
+
+[PI2FD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x0D       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x0D           PENT,3DNOW
+
+[PMACHRIW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x5E\110              PENT,MMX,SM,CYRIX
+
+[PMADDWD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xF5\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xF5\110                  PENT,MMX
+
+[PMAGW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x52\110              PENT,MMX,SM,CYRIX
+mmxreg,mmxreg         \2\x0F\x52\110                  PENT,MMX,CYRIX
+
+[PMULHRIW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x5D\110              PENT,MMX,SM,CYRIX
+mmxreg,mmxreg         \2\x0F\x5D\110                  PENT,MMX,CYRIX
+
+[PMULHRWA]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\1\xB7        PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\1\xB7            PENT,3DNOW
+
+[PMULHRWC]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x59\110              PENT,MMX,SM,CYRIX
+mmxreg,mmxreg         \2\x0F\x59\110                  PENT,MMX,CYRIX
+
+[PMULHW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xE5\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xE5\110                  PENT,MMX
+
+[PMULLW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xD5\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xD5\110                  PENT,MMX
+
+[PMVGEZB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x5C\110              PENT,MMX,SM,CYRIX
+
+[PMVLZB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x5B\110              PENT,MMX,SM,CYRIX
+
+[PMVNZB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x5A\110              PENT,MMX,SM,CYRIX
+
+[PMVZB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x58\110              PENT,MMX,SM,CYRIX
+
+[POP,popX]
+(Ch_Wop1, Ch_RWESP, Ch_None)
+reg16                 \320\10\x58                     8086
+reg32                 \321\10\x58                     386
+rm16                  \320\300\1\x8F\200              8086
+rm32                  \321\300\1\x8F\200              386
+reg_cs                \1\x0F                          8086,UNDOC,ND
+reg_dess              \4                              8086
+reg_fsgs              \1\x0F\5                        386
+
+[POPA,popaX]
+(Ch_All, Ch_None, Ch_None)
+void                  \322\1\x61                      186
+
+[POPAD,popal]
+(Ch_All, Ch_None, Ch_None)
+void                  \321\1\x61                      386
+
+[POPAW]
+(Ch_All, Ch_None, Ch_None)
+void                  \320\1\x61                      186
+
+[POPF]
+(Ch_RWESP, Ch_WFlags, Ch_None)
+void                  \322\1\x9D                      186
+
+[POPFD,popfl]
+(Ch_RWESP, Ch_WFlags, Ch_None)
+void                  \321\1\x9D                      386
+
+[POPFW]
+(Ch_RWESP, Ch_WFLAGS, Ch_None)
+void                  \320\1\x9D                      186
+
+[POR]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xEB\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xEB\110                  PENT,MMX
+
+[PREFETCH,prefetchX]
+(Ch_All, Ch_None, Ch_None)
+mem                   \2\x0F\x0D\200                  PENT,3DNOW,SM
+
+[PREFETCHW,prefetchwX]
+(Ch_All, Ch_None, Ch_None)
+mem                   \2\x0F\x0D\201                  PENT,3DNOW,SM
+
+[PSLLD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xF2\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xF2\110                  PENT,MMX
+mmxreg,imm            \2\x0F\x72\206\25               PENT,MMX
+
+[PSLLQ]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xF3\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xF3\110                  PENT,MMX
+mmxreg,imm            \2\x0F\x73\206\25               PENT,MMX
+
+[PSLLW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xF1\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xF1\110                  PENT,MMX
+mmxreg,imm            \2\x0F\x71\206\25               PENT,MMX
+
+[PSRAD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xE2\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xE2\110                  PENT,MMX
+mmxreg,imm            \2\x0F\x72\204\25               PENT,MMX
+
+[PSRAW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xE1\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xE1\110                  PENT,MMX
+mmxreg,imm            \2\x0F\x71\204\25               PENT,MMX
+
+[PSRLD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xD2\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xD2\110                  PENT,MMX
+mmxreg,imm            \2\x0F\x72\202\25               PENT,MMX
+
+[PSRLQ]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xD3\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xD3\110                  PENT,MMX
+mmxreg,imm            \2\x0F\x73\202\25               PENT,MMX
+
+[PSRLW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xD1\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xD1\110                  PENT,MMX
+mmxreg,imm            \2\x0F\x71\202\25               PENT,MMX
+
+[PSUBB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xF8\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xF8\110                  PENT,MMX
+
+[PSUBD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xFA\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xFA\110                  PENT,MMX
+
+[PSUBSB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xE8\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xE8\110                  PENT,MMX
+
+[PSUBSIW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x55\110              PENT,MMX,SM,CYRIX
+mmxreg,mmxreg         \2\x0F\x55\110                  PENT,MMX,CYRIX
+
+[PSUBSW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xE9\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xE9\110                  PENT,MMX
+
+[PSUBUSB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xD8\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xD8\110                  PENT,MMX
+
+[PSUBUSW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xD9\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xD9\110                  PENT,MMX
+
+[PSUBW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xF9\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xF9\110                  PENT,MMX
+
+[PUNPCKHBW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x68\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x68\110                  PENT,MMX
+
+[PUNPCKHDQ]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x6A\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x6A\110                  PENT,MMX
+
+[PUNPCKHWD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x69\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x69\110                  PENT,MMX
+
+[PUNPCKLBW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x60\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x60\110                  PENT,MMX
+
+[PUNPCKLDQ]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x62\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x62\110                  PENT,MMX
+
+[PUNPCKLWD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x61\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\x61\110                  PENT,MMX
+
+[PUSH,pushX]
+(Ch_Rop1, Ch_RWESP, Ch_None)
+reg16                 \320\10\x50                     8086
+reg32                 \321\10\x50                     386
+rm16                  \320\300\1\xFF\206              8086
+rm32                  \321\300\1\xFF\206              386
+reg_fsgs              \1\x0F\7                        386
+reg_sreg              \6                              8086
+imm8                  \1\x6A\14                       286
+imm16                 \320\1\x68\30                   286
+imm32                 \321\1\x68\40                   386
+
+[PUSHA,pushaX]
+(Ch_All, Ch_None, Ch_None)
+void                  \322\1\x60                      186
+
+[PUSHAD,pushal]
+(Ch_All, Ch_None, Ch_None)
+void                  \321\1\x60                      386
+
+[PUSHAW]
+(Ch_All, Ch_None, Ch_None)
+void                  \320\1\x60                      186
+
+[PUSHF]
+(Ch_RWESP, Ch_RFlags, Ch_None)
+void                  \322\1\x9C                      186
+
+[PUSHFD,pushfl]
+(Ch_RWESP, Ch_RFlags, Ch_None)
+void                  \321\1\x9C                      386
+
+[PUSHFW]
+(Ch_RWESP, Ch_RFLAGS, Ch_None)
+void                  \320\1\x9C                      186
+
+[PXOR]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\xEF\110              PENT,MMX,SM
+mmxreg,mmxreg         \2\x0F\xEF\110                  PENT,MMX
+
+[RCL,rclX]
+(Ch_Mop2, Ch_Rop1, Ch_RWFlags)
+rm8,unity             \300\1\xD0\202                  8086
+rm8,reg_cl            \300\1\xD2\202                  8086
+rm8,imm               \300\1\xC0\202\25               186,SB
+rm16,unity            \320\300\1\xD1\202              8086
+rm16,reg_cl           \320\300\1\xD3\202              8086
+rm16,imm              \320\300\1\xC1\202\25           186,SB
+rm32,unity            \321\300\1\xD1\202              386
+rm32,reg_cl           \321\300\1\xD3\202              386
+rm32,imm              \321\300\1\xC1\202\25           386,SB
+
+[RCR,rcrX]
+(Ch_Mop2, Ch_Rop1, Ch_RWFlags)
+rm8,unity             \300\1\xD0\203                  8086
+rm8,reg_cl            \300\1\xD2\203                  8086
+rm8,imm               \300\1\xC0\203\25               186,SB
+rm16,unity            \320\300\1\xD1\203              8086
+rm16,reg_cl           \320\300\1\xD3\203              8086
+rm16,imm              \320\300\1\xC1\203\25           186,SB
+rm32,unity            \321\300\1\xD1\203              386
+rm32,reg_cl           \321\300\1\xD3\203              386
+rm32,imm              \321\300\1\xC1\203\25           386,SB
+
+[RDSHR]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x36                      P6,CYRIX,SMM
+
+[RDMSR]
+(Ch_WEAX, Ch_WEDX, Ch_None)
+void                  \2\x0F\x32                      PENT,PRIV
+
+[RDPMC]
+(Ch_WEAX, Ch_WEDX, Ch_None)
+void                  \2\x0F\x33                      P6
+
+[RDTSC]
+(Ch_WEAX, Ch_WEDX, Ch_None)
+void                  \2\x0F\x31                      PENT
+
+[REP]
+(Ch_RWECX, Ch_RWFlags, Ch_None)
+void                  \1\xF3                          8086,PRE
+
+[REPE]
+(Ch_RWECX, Ch_RWFlags, Ch_None)
+void                  \1\xF3                          8086,PRE
+
+[REPNE]
+(Ch_RWECX, Ch_RWFlags, Ch_None)
+void                  \1\xF2                          8086,PRE
+
+[REPNZ]
+(Ch_RWECX, Ch_RWFLAGS, Ch_None)
+void                  \1\xF2                          8086,PRE
+
+[REPZ]
+(Ch_RWECX, Ch_RWFLAGS, Ch_None)
+void                  \1\xF3                          8086,PRE
+
+[RET]
+(Ch_All, Ch_None, Ch_None)
+void                  \1\xC3                          8086
+imm                   \1\xC2\30                       8086,SW
+
+[RETF,lret]
+(Ch_All, Ch_None, Ch_None)
+void                  \1\xCB                          8086
+imm                   \1\xCA\30                       8086,SW
+
+[RETN,ret]
+(Ch_All, Ch_None, Ch_None)
+void                  \1\xC3                          8086
+imm                   \1\xC2\30                       8086,SW
+
+[ROL,rolX]
+(Ch_Mop2, Ch_Rop1, Ch_RWFlags)
+rm8,unity             \300\1\xD0\200                  8086
+rm8,reg_cl            \300\1\xD2\200                  8086
+rm8,imm               \300\1\xC0\200\25               186,SB
+rm16,unity            \320\300\1\xD1\200              8086
+rm16,reg_cl           \320\300\1\xD3\200              8086
+rm16,imm              \320\300\1\xC1\200\25           186,SB
+rm32,unity            \321\300\1\xD1\200              386
+rm32,reg_cl           \321\300\1\xD3\200              386
+rm32,imm              \321\300\1\xC1\200\25           386,SB
+
+[ROR,rorX]
+(Ch_Mop2, Ch_Rop1, Ch_RWFlags)
+rm8,unity             \300\1\xD0\201                  8086
+rm8,reg_cl            \300\1\xD2\201                  8086
+rm8,imm               \300\1\xC0\201\25               186,SB
+rm16,unity            \320\300\1\xD1\201              8086
+rm16,reg_cl           \320\300\1\xD3\201              8086
+rm16,imm              \320\300\1\xC1\201\25           186,SB
+rm32,unity            \321\300\1\xD1\201              386
+rm32,reg_cl           \321\300\1\xD3\201              386
+rm32,imm              \321\300\1\xC1\201\25           386,SB
+
+[RSDC]
+(Ch_All, Ch_None, Ch_None)
+reg_sreg,mem80        \301\2\x0F\x79\101              486,CYRIX,SMM
+
+[RSLDT]
+(Ch_All, Ch_None, Ch_None)
+mem80                 \300\2\x0F\x7B\200              486,CYRIX,SMM
+
+[RSM]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\xAA                      PENT,SMM
+
+[SAHF]
+(Ch_WFlags, Ch_REAX, Ch_None)
+void                  \1\x9E                          8086
+
+[SAL,salX]
+(Ch_Mop2, Ch_Rop1, Ch_RWFlags)
+rm8,unity             \300\1\xD0\204                  8086,ND
+rm8,reg_cl            \300\1\xD2\204                  8086,ND
+rm8,imm               \300\1\xC0\204\25               186,ND,SB
+rm16,unity            \320\300\1\xD1\204              8086,ND
+rm16,reg_cl           \320\300\1\xD3\204              8086,ND
+rm16,imm              \320\300\1\xC1\204\25           186,ND,SB
+rm32,unity            \321\300\1\xD1\204              386,ND
+rm32,reg_cl           \321\300\1\xD3\204              386,ND
+rm32,imm              \321\300\1\xC1\204\25           386,ND,SB
+
+[SALC]
+(Ch_WEAX, Ch_RFLAGS, Ch_None)
+void                  \1\xD6                          8086,UNDOC
+
+[SAR,sarX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+rm8,unity             \300\1\xD0\207                  8086
+rm8,reg_cl            \300\1\xD2\207                  8086
+rm8,imm               \300\1\xC0\207\25               186,SB
+rm16,unity            \320\300\1\xD1\207              8086
+rm16,reg_cl           \320\300\1\xD3\207              8086
+rm16,imm              \320\300\1\xC1\207\25           186,SB
+rm32,unity            \321\300\1\xD1\207              386
+rm32,reg_cl           \321\300\1\xD3\207              386
+rm32,imm              \321\300\1\xC1\207\25           386,SB
+
+[SBB,sbbX]
+(Ch_Mop2, Ch_Rop1, Ch_RWFlags)
+mem,reg8              \300\1\x18\101                  8086,SM
+reg8,reg8             \300\1\x18\101                  8086
+mem,reg16             \320\300\1\x19\101              8086,SM
+reg16,reg16           \320\300\1\x19\101              8086
+mem,reg32             \321\300\1\x19\101              386,SM
+reg32,reg32           \321\300\1\x19\101              386
+reg8,mem              \301\1\x1A\110                  8086,SM
+reg8,reg8             \301\1\x1A\110                  8086
+reg16,mem             \320\301\1\x1B\110              8086,SM
+reg16,reg16           \320\301\1\x1B\110              8086
+reg32,mem             \321\301\1\x1B\110              386,SM
+reg32,reg32           \321\301\1\x1B\110              386
+rm16,imm8             \320\300\1\x83\203\15           8086
+rm32,imm8             \321\300\1\x83\203\15           8086
+reg_al,imm            \1\x1C\21                       8086,SM
+reg_ax,imm            \320\1\x1D\31                   8086,SM
+reg_eax,imm           \321\1\x1D\41                   386,SM
+rm8,imm               \300\1\x80\203\21               8086,SM
+rm16,imm              \320\300\1\x81\203\31           8086,SM
+rm32,imm              \321\300\1\x81\203\41           386,SM
+mem,imm8              \300\1\x80\203\21               8086,SM
+mem,imm16             \320\300\1\x81\203\31           8086,SM
+mem,imm32             \321\300\1\x81\203\41           386,SM
+
+[SCASB]
+(Ch_All, Ch_None, Ch_None)
+void                  \332\1\xAE                      8086
+
+[SCASD,scasl]
+(Ch_All, Ch_None, Ch_None)
+void                  \332\321\1\xAF                  386
+
+[SCASW]
+(Ch_All, Ch_None, Ch_None)
+void                  \332\320\1\xAF                  8086
+
+[SEGCS,cs]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\x2E                          8086,PRE
+
+[SEGDS,ds]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\x3E                          8086,PRE
+
+[SEGES,es]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\x26                          8086,PRE
+
+[SEGFS,fs]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\x64                          8086,PRE
+
+[SEGGS,gs]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\x65                          8086,PRE
+
+[SEGSS,ss]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\x36                          8086,PRE
+
+[SGDT]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\2\x0F\x01\200              286
+
+[SHL,shlX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+rm8,unity             \300\1\xD0\204                  8086
+rm8,reg_cl            \300\1\xD2\204                  8086
+rm8,imm               \300\1\xC0\204\25               186,SB
+rm16,unity            \320\300\1\xD1\204              8086
+rm16,reg_cl           \320\300\1\xD3\204              8086
+rm16,imm              \320\300\1\xC1\204\25           186,SW
+rm32,unity            \321\300\1\xD1\204              386
+rm32,reg_cl           \321\300\1\xD3\204              386
+rm32,imm              \321\300\1\xC1\204\25           386,SD
+
+[SHLD,shldX]
+(Ch_MOp3, Ch_RWFlags, Ch_Rop2)
+mem,reg16,imm         \300\320\2\x0F\xA4\101\26       386,SM2,SB,AR2
+reg16,reg16,imm       \300\320\2\x0F\xA4\101\26       386,SM2,SB,AR2
+mem,reg32,imm         \300\321\2\x0F\xA4\101\26       386,SM2,SB,AR2
+reg32,reg32,imm       \300\321\2\x0F\xA4\101\26       386,SM2,SB,AR2
+mem,reg16,reg_cl      \300\320\2\x0F\xA5\101          386,SM
+reg16,reg16,reg_cl    \300\320\2\x0F\xA5\101          386
+mem,reg32,reg_cl      \300\321\2\x0F\xA5\101          386,SM
+reg32,reg32,reg_cl    \300\321\2\x0F\xA5\101          386
+
+[SHR,shrX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+rm8,unity             \300\1\xD0\205                  8086
+rm8,reg_cl            \300\1\xD2\205                  8086
+rm8,imm               \300\1\xC0\205\25               186,SB
+rm16,unity            \320\300\1\xD1\205              8086
+rm16,reg_cl           \320\300\1\xD3\205              8086
+rm16,imm              \320\300\1\xC1\205\25           186,SW
+rm32,unity            \321\300\1\xD1\205              386
+rm32,reg_cl           \321\300\1\xD3\205              386
+rm32,imm              \321\300\1\xC1\205\25           386,SD
+
+[SHRD,shrdX]
+(Ch_MOp3, Ch_RWFlags, Ch_Rop2)
+mem,reg16,imm         \300\320\2\x0F\xAC\101\26       386,SM2,SB,AR2
+reg16,reg16,imm       \300\320\2\x0F\xAC\101\26       386,SM2,SB,AR2
+mem,reg32,imm         \300\321\2\x0F\xAC\101\26       386,SM2,SB,AR2
+reg32,reg32,imm       \300\321\2\x0F\xAC\101\26       386,SM2,SB,AR2
+mem,reg16,reg_cl      \300\320\2\x0F\xAD\101          386,SM
+reg16,reg16,reg_cl    \300\320\2\x0F\xAD\101          386
+mem,reg32,reg_cl      \300\321\2\x0F\xAD\101          386,SM
+reg32,reg32,reg_cl    \300\321\2\x0F\xAD\101          386
+
+[SIDT,sidtX]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\2\x0F\x01\201              286
+
+[SLDT,sldtX]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\1\x0F\17\200               286
+mem16                 \300\1\x0F\17\200               286
+reg16                 \300\1\x0F\17\200               286
+
+[SMI]
+(Ch_All, Ch_None, Ch_None)
+void                  \1\xF1                          386,UNDOC
+
+[SMINT]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x38                      P6,CYRIX
+
+[SMINTOLD]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x7E                      486,CYRIX,ND
+
+[SMSW,smswX]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\2\x0F\x01\204              286
+mem16                 \300\2\x0F\x01\204              286
+reg16                 \300\2\x0F\x01\204              286
+
+[STC]
+(Ch_WFlags, Ch_None, Ch_None)
+void                  \1\xF9                          8086
+
+[STD]
+(Ch_SDirFlag, Ch_None, Ch_None)
+void                  \1\xFD                          8086
+
+[STI]
+(Ch_WFlags, Ch_None, Ch_None)
+void                  \1\xFB                          8086
+
+[STOSB]
+(Ch_REAX, Ch_WMemEDI, Ch_RWEDI)
+void                  \1\xAA                          8086
+
+[STOSD,stosl]
+(Ch_REAX, Ch_WMemEDI, Ch_RWEDI)
+void                  \321\1\xAB                      386
+
+[STOSW]
+(Ch_REAX, Ch_WMemEDI, Ch_RWEDI)
+void                  \320\1\xAB                      8086
+
+[STR,strX]
+(Ch_Wop1, Ch_None, Ch_None)
+mem                   \300\1\x0F\17\201               286,PROT
+mem16                 \300\1\x0F\17\201               286,PROT
+reg16                 \300\1\x0F\17\201               286,PROT
+
+[SUB,subX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+mem,reg8              \300\1\x28\101                  8086,SM
+reg8,reg8             \300\1\x28\101                  8086
+mem,reg16             \320\300\1\x29\101              8086,SM
+reg16,reg16           \320\300\1\x29\101              8086
+mem,reg32             \321\300\1\x29\101              386,SM
+reg32,reg32           \321\300\1\x29\101              386
+reg8,mem              \301\1\x2A\110                  8086,SM
+reg8,reg8             \301\1\x2A\110                  8086
+reg16,mem             \320\301\1\x2B\110              8086,SM
+reg16,reg16           \320\301\1\x2B\110              8086
+reg32,mem             \321\301\1\x2B\110              386,SM
+reg32,reg32           \321\301\1\x2B\110              386
+rm16,imm8             \320\300\1\x83\205\15           8086
+rm32,imm8             \321\300\1\x83\205\15           386
+reg_al,imm            \1\x2C\21                       8086,SM
+reg_ax,imm            \320\1\x2D\31                   8086,SM
+reg_eax,imm           \321\1\x2D\41                   386,SM
+rm8,imm               \300\1\x80\205\21               8086,SM
+rm16,imm              \320\300\1\x81\205\31           8086,SM
+rm32,imm              \321\300\1\x81\205\41           386,SM
+mem,imm8              \300\1\x80\205\21               8086,SM
+mem,imm16             \320\300\1\x81\205\31           8086,SM
+mem,imm32             \321\300\1\x81\205\41           386,SM
+
+[SVDC,svdcX]
+(Ch_All, Ch_None, Ch_None)
+mem80,reg_sreg        \300\2\x0F\x78\101              486,CYRIX,SMM
+
+[SVLDT,svldtX]
+(Ch_All, Ch_None, Ch_None)
+mem80                 \300\2\x0F\x7A\200              486,CYRIX,SMM
+
+[SVTS,svtsX]
+(Ch_All, Ch_None, Ch_None)
+mem80                 \300\2\x0F\x7C\200              486,CYRIX,SMM
+
+[SYSCALL]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x05                      P6,AMD
+
+[SYSENTER]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x34                      P6
+
+[SYSEXIT]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x36                      P6,PRIV
+
+[SYSRET]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x07                      P6,PRIV,AMD
+
+[TEST,testX]
+(Ch_WFlags, Ch_Rop1, Ch_Rop2)
+mem,reg8              \300\1\x84\101                  8086,SM
+reg8,reg8             \300\1\x84\101                  8086
+mem,reg16             \320\300\1\x85\101              8086,SM
+reg16,reg16           \320\300\1\x85\101              8086
+mem,reg32             \321\300\1\x85\101              386,SM
+reg32,reg32           \321\300\1\x85\101              386
+reg8,mem              \301\1\x84\110                  8086,SM
+reg16,mem             \320\301\1\x85\110              8086,SM
+reg32,mem             \321\301\1\x85\110              386,SM
+reg_al,imm            \1\xA8\21                       8086,SM
+reg_ax,imm            \320\1\xA9\31                   8086,SM
+reg_eax,imm           \321\1\xA9\41                   386,SM
+rm8,imm               \300\1\xF6\200\21               8086,SM
+rm16,imm              \320\300\1\xF7\200\31           8086,SM
+rm32,imm              \321\300\1\xF7\200\41           386,SM
+mem,imm8              \300\1\xF6\200\21               8086,SM
+mem,imm16             \320\300\1\xF7\200\31           8086,SM
+mem,imm32             \321\300\1\xF7\200\41           386,SM
+
+[UD1]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\xB9                      286,UNDOC
+
+[UD2]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x0B                      286
+
+[UMOV,umovX]
+(Ch_All, Ch_None, Ch_None)
+mem,reg8              \300\2\x0F\x10\101              386,UNDOC,SM
+reg8,reg8             \300\2\x0F\x10\101              386,UNDOC
+mem,reg16             \320\300\2\x0F\x11\101          386,UNDOC,SM
+reg16,reg16           \320\300\2\x0F\x11\101          386,UNDOC
+mem,reg32             \321\300\2\x0F\x11\101          386,UNDOC,SM
+reg32,reg32           \321\300\2\x0F\x11\101          386,UNDOC
+reg8,mem              \301\2\x0F\x12\110              386,UNDOC,SM
+reg8,reg8             \301\2\x0F\x12\110              386,UNDOC
+reg16,mem             \320\301\2\x0F\x13\110          386,UNDOC,SM
+reg16,reg16           \320\301\2\x0F\x13\110          386,UNDOC
+reg32,mem             \321\301\2\x0F\x13\110          386,UNDOC,SM
+reg32,reg32           \321\301\2\x0F\x13\110          386,UNDOC
+
+[VERR,verrX]
+(Ch_WFlags, Ch_None, Ch_None)
+mem                   \300\1\x0F\17\204               286,PROT
+mem16                 \300\1\x0F\17\204               286,PROT
+reg16                 \300\1\x0F\17\204               286,PROT
+
+[VERW]
+(Ch_WFlags, Ch_None, Ch_None)
+mem                   \300\1\x0F\17\205               286,PROT
+mem16                 \300\1\x0F\17\205               286,PROT
+reg16                 \300\1\x0F\17\205               286,PROT
+
+[WAIT]
+(Ch_None, Ch_None, Ch_None)
+void                  \1\x9B                          8086
+
+[WBINVD]
+(Ch_None, Ch_None, Ch_None)
+void                  \2\x0F\x09                      486,PRIV
+
+[WRSHR]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x37                      P6,CYRIX,SMM
+
+[WRMSR]
+(Ch_All, Ch_None, Ch_None)
+void                  \2\x0F\x30                      PENT,PRIV
+
+[XADD,xaddX]
+(Ch_All, Ch_None, Ch_None)
+mem,reg8              \300\2\x0F\xC0\101              486,SM
+reg8,reg8             \300\2\x0F\xC0\101              486
+mem,reg16             \320\300\2\x0F\xC1\101          486,SM
+reg16,reg16           \320\300\2\x0F\xC1\101          486
+mem,reg32             \321\300\2\x0F\xC1\101          486,SM
+reg32,reg32           \321\300\2\x0F\xC1\101          486
+
+[XBTS,xbtsX]
+(Ch_All, Ch_None, Ch_None)
+reg16,mem             \320\301\2\x0F\xA6\110          386,SW,UNDOC,ND
+reg16,reg16           \320\301\2\x0F\xA6\110          386,UNDOC,ND
+reg32,mem             \321\301\2\x0F\xA6\110          386,SD,UNDOC,ND
+reg32,reg32           \321\301\2\x0F\xA6\110          386,UNDOC,ND
+
+[XCHG,xchgX]
+(Ch_RWop1, Ch_RWop2, Ch_None)
+reg_ax,reg16          \320\11\x90                     8086
+reg_eax,reg32         \321\11\x90                     386
+reg16,reg_ax          \320\10\x90                     8086
+reg32,reg_eax         \321\10\x90                     386
+reg8,mem              \301\1\x86\110                  8086,SM
+reg8,reg8             \301\1\x86\110                  8086
+reg16,mem             \320\301\1\x87\110              8086,SM
+reg16,reg16           \320\301\1\x87\110              8086
+reg32,mem             \321\301\1\x87\110              386,SM
+reg32,reg32           \321\301\1\x87\110              386
+mem,reg8              \300\1\x86\101                  8086,SM
+reg8,reg8             \300\1\x86\101                  8086
+mem,reg16             \320\300\1\x87\101              8086,SM
+reg16,reg16           \320\300\1\x87\101              8086
+mem,reg32             \321\300\1\x87\101              386,SM
+reg32,reg32           \321\300\1\x87\101              386
+
+[XLAT]
+(Ch_WEAX, Ch_REBX, Ch_None)
+void                  \1\xD7                          8086
+
+[XLATB]
+(Ch_WEAX, Ch_REBX, Ch_None)
+void                  \1\xD7                          8086
+
+[XOR,xorX]
+(Ch_Mop2, Ch_Rop1, Ch_WFlags)
+mem,reg8              \300\1\x30\101                  8086,SM
+reg8,reg8             \300\1\x30\101                  8086
+mem,reg16             \320\300\1\x31\101              8086,SM
+reg16,reg16           \320\300\1\x31\101              8086
+mem,reg32             \321\300\1\x31\101              386,SM
+reg32,reg32           \321\300\1\x31\101              386
+reg8,mem              \301\1\x32\110                  8086,SM
+reg8,reg8             \301\1\x32\110                  8086
+reg16,mem             \320\301\1\x33\110              8086,SM
+reg16,reg16           \320\301\1\x33\110              8086
+reg32,mem             \321\301\1\x33\110              386,SM
+reg32,reg32           \321\301\1\x33\110              386
+rm16,imm8             \320\300\1\x83\206\15           8086
+rm32,imm8             \321\300\1\x83\206\15           386
+reg_al,imm            \1\x34\21                       8086,SM
+reg_ax,imm            \320\1\x35\31                   8086,SM
+reg_eax,imm           \321\1\x35\41                   386,SM
+rm8,imm               \300\1\x80\206\21               8086,SM
+rm16,imm              \320\300\1\x81\206\31           8086,SM
+rm32,imm              \321\300\1\x81\206\41           386,SM
+mem,imm8              \300\1\x80\206\21               8086,SM
+mem,imm16             \320\300\1\x81\206\31           8086,SM
+mem,imm32             \321\300\1\x81\206\41           386,SM
+
+[CMOVcc,cmovCCX]
+(Ch_ROp1, Ch_WOp2, Ch_RFLAGS)
+reg16,mem             \320\301\1\x0F\330\x40\110      P6,SM
+reg16,reg16           \320\301\1\x0F\330\x40\110      P6
+reg32,mem             \321\301\1\x0F\330\x40\110      P6,SM
+reg32,reg32           \321\301\1\x0F\330\x40\110      P6
+
+[Jcc]
+(Ch_None, Ch_None, Ch_None)
+imm|near              \322\1\x0F\330\x80\64           386,PASS2
+imm16|near            \320\1\x0F\330\x80\64           386,PASS2
+imm32|near            \321\1\x0F\330\x80\64           386,PASS2
+imm                   \330\x70\50                     8086
+imm|short             \330\x70\50                     8086,ND
+
+[SETcc,setCCX]
+(Ch_RFLAGS, Ch_WOp1, Ch_None)
+mem                   \300\1\x0F\330\x90\200          386,SB
+reg8                  \300\1\x0F\330\x90\200          386
+
+;
+; Katmai Streaming SIMD instructions (SSE -- a.k.a. KNI, XMM, MMX2)
+;
+
+[ADDPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\x58\110          KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\x58\110              KATMAI,SSE
+
+[ADDSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x58\110          KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x58\110              KATMAI,SSE
+
+[ANDNPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x55\110              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x55\110                  KATMAI,SSE
+
+[ANDPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x54\110              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x54\110                  KATMAI,SSE
+
+[CMPEQPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\xC2\110\1\x00    KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\xC2\110\1\x00        KATMAI,SSE
+
+[CMPEQSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\xC2\110\1\x00    KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\xC2\110\1\x00        KATMAI,SSE
+
+[CMPLEPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\xC2\110\1\x02    KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\xC2\110\1\x02        KATMAI,SSE
+
+[CMPLESS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\xC2\110\1\x02    KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\xC2\110\1\x02        KATMAI,SSE
+
+[CMPLTPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\xC2\110\1\x01    KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\xC2\110\1\x01        KATMAI,SSE
+
+[CMPLTSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\xC2\110\1\x01    KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\xC2\110\1\x01        KATMAI,SSE
+
+[CMPNEQPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\xC2\110\1\x04    KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\xC2\110\1\x04        KATMAI,SSE
+
+[CMPNEQSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\xC2\110\1\x04    KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\xC2\110\1\x04        KATMAI,SSE
+
+[CMPNLEPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\xC2\110\1\x06    KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\xC2\110\1\x06        KATMAI,SSE
+
+[CMPNLESS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\xC2\110\1\x06    KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\xC2\110\1\x06        KATMAI,SSE
+
+[CMPNLTPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\xC2\110\1\x05    KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\xC2\110\1\x05        KATMAI,SSE
+
+[CMPNLTSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\xC2\110\1\x05    KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\xC2\110\1\x05        KATMAI,SSE
+
+[CMPORDPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\xC2\110\1\x07    KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\xC2\110\1\x07        KATMAI,SSE
+
+[CMPORDSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\xC2\110\1\x07    KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\xC2\110\1\x07        KATMAI,SSE
+
+[CMPUNORDPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\xC2\110\1\x03    KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\xC2\110\1\x03        KATMAI,SSE
+
+[CMPUNORDSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\xC2\110\1\x03    KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\xC2\110\1\x03        KATMAI,SSE
+
+;
+; CMPPS/CMPSS must come after the specific ops; that way the disassembler will find the
+; specific ops first and only disassemble illegal ones as cmpps.
+;
+
+[CMPPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem,imm        \301\331\2\x0F\xC2\110\22       KATMAI,SSE,SB,AR2
+xmmreg,xmmreg,imm     \331\2\x0F\xC2\110\22           KATMAI,SSE,SB,AR2
+
+[CMPSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem,imm        \301\333\2\x0F\xC2\110\22       KATMAI,SSE,SB,AR2
+xmmreg,xmmreg,imm     \333\2\x0F\xC2\110\22           KATMAI,SSE,SB,AR2
+
+[COMISS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x2F\110              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x2F\110                  KATMAI,SSE
+
+[CVTPI2PS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\x2A\110          KATMAI,SSE,MMX
+xmmreg,mmxreg         \331\2\x0F\x2A\110              KATMAI,SSE,MMX
+
+[CVTPS2PI]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\331\2\x0F\x2D\110          KATMAI,SSE,MMX
+mmxreg,xmmreg         \331\2\x0F\x2D\110              KATMAI,SSE,MMX
+
+[CVTSI2SS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x2A\110          KATMAI,SSE,SD,AR1
+xmmreg,reg32          \333\2\x0F\x2A\110              KATMAI,SSE
+
+[CVTSS2SI]
+(Ch_All, Ch_None, Ch_None)
+reg32,mem             \301\333\2\x0F\x2D\110          KATMAI,SSE
+reg32,xmmreg          \333\2\x0F\x2D\110              KATMAI,SSE
+
+[CVTTPS2PI]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\331\2\x0F\x2C\110          KATMAI,SSE,MMX
+mmxreg,xmmreg         \331\2\x0F\x2C\110              KATMAI,SSE,MMX
+
+[CVTTSS2SI]
+(Ch_All, Ch_None, Ch_None)
+reg32,mem             \301\333\2\x0F\x2C\110          KATMAI,SSE
+reg32,xmmreg          \333\2\x0F\x2C\110              KATMAI,SSE
+
+[DIVPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\x5E\110          KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\x5E\110              KATMAI,SSE
+
+[DIVSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x5E\110          KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x5E\110              KATMAI,SSE
+
+[LDMXCSR]
+(Ch_All, Ch_None, Ch_None)
+mem                   \300\2\x0F\xAE\202              KATMAI,SSE,SD
+
+[MAXPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\x5F\110          KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\x5F\110              KATMAI,SSE
+
+[MAXSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x5F\110          KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x5F\110              KATMAI,SSE
+
+[MINPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\x5D\110          KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\x5D\110              KATMAI,SSE
+
+[MINSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x5D\110          KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x5D\110              KATMAI,SSE
+
+[MOVAPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x28\110              KATMAI,SSE
+mem,xmmreg            \300\2\x0F\x29\101              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x28\110                  KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x29\101                  KATMAI,SSE
+
+[MOVHPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x16\110              KATMAI,SSE
+mem,xmmreg            \300\2\x0F\x17\101              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x16\101                  KATMAI,SSE,ND
+
+[MOVLHPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,xmmreg         \2\x0F\x16\110                  KATMAI,SSE
+
+[MOVLPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x12\110              KATMAI,SSE
+mem,xmmreg            \300\2\x0F\x13\101              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x12\101                  KATMAI,SSE,ND
+
+[MOVHLPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,xmmreg         \2\x0F\x12\110                  KATMAI,SSE
+
+[MOVMSKPS]
+(Ch_All, Ch_None, Ch_None)
+reg32,xmmreg          \2\x0F\x50\110                  KATMAI,SSE
+
+[MOVNTPS]
+(Ch_All, Ch_None, Ch_None)
+mem,xmmreg            \2\x0F\x2B\101                  KATMAI,SSE
+
+[MOVSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x10\110          KATMAI,SSE
+mem,xmmreg            \300\333\2\x0F\x11\101          KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x10\110              KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x11\101              KATMAI,SSE
+
+[MOVUPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\x10\110          KATMAI,SSE
+mem,xmmreg            \300\331\2\x0F\x11\101          KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\x10\110              KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\x11\101              KATMAI,SSE
+
+[MULPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x59\110              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x59\110                  KATMAI,SSE
+
+[MULSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x59\110          KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x59\110              KATMAI,SSE
+
+[ORPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x56\110              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x56\110                  KATMAI,SSE
+
+[RCPPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\x53\110          KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\x53\110              KATMAI,SSE
+
+[RCPSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x53\110          KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x53\110              KATMAI,SSE
+
+[RSQRTPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\x52\110          KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\x52\110              KATMAI,SSE
+
+[RSQRTSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x52\110          KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x52\110              KATMAI,SSE
+
+[SHUFPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem,imm        \301\2\x0F\xC6\110\22           KATMAI,SSE,SB,AR2
+xmmreg,xmmreg,imm     \2\x0F\xC6\110\22               KATMAI,SSE,SB,AR2
+
+[SQRTPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\x51\110          KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\x51\110              KATMAI,SSE
+
+[SQRTSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x51\110          KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x51\110              KATMAI,SSE
+
+[STMXCSR]
+(Ch_All, Ch_None, Ch_None)
+mem                   \300\2\x0F\xAE\203              KATMAI,SSE,SD
+
+[SUBPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\331\2\x0F\x5C\110          KATMAI,SSE
+xmmreg,xmmreg         \331\2\x0F\x5C\110              KATMAI,SSE
+
+[SUBSS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\333\2\x0F\x5C\110          KATMAI,SSE
+xmmreg,xmmreg         \333\2\x0F\x5C\110              KATMAI,SSE
+
+[UCOMISS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x2E\110              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x2E\110                  KATMAI,SSE
+
+[UNPCKHPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x15\110              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x15\110                  KATMAI,SSE
+
+[UNPCKLPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x14\110              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x14\110                  KATMAI,SSE
+
+[XORPS]
+(Ch_All, Ch_None, Ch_None)
+xmmreg,mem            \301\2\x0F\x57\110              KATMAI,SSE
+xmmreg,xmmreg         \2\x0F\x57\110                  KATMAI,SSE
+
+;
+; Introduced in Dechutes but necessary for SSE support
+;
+
+[FXRSTOR]
+(Ch_All, Ch_None, Ch_None)
+mem                   \300\2\x0F\xAE\201              P6,SSE,FPU
+
+[FXSAVE]
+(Ch_All, Ch_None, Ch_None)
+mem                   \300\2\x0F\xAE\200              P6,SSE,FPU
+
+;
+; These instructions aren't SSE-specific; they are generic memory operations
+; and work even if CR4.OSFXFR == 0
+;
+
+[PREFETCHNTA]
+(Ch_All, Ch_None, Ch_None)
+mem                   \300\2\x0F\x18\200              KATMAI
+
+[PREFETCHT0]
+(Ch_All, Ch_None, Ch_None)
+mem                   \300\2\x0F\x18\201              KATMAI
+
+[PREFETCHT1]
+(Ch_All, Ch_None, Ch_None)
+mem                   \300\2\x0F\x18\202              KATMAI
+
+[PREFETCHT2]
+(Ch_All, Ch_None, Ch_None)
+mem                   \300\2\x0F\x18\203              KATMAI
+
+[SFENCE]
+(Ch_All, Ch_None, Ch_None)
+void                  \3\x0F\xAE\xF8                  KATMAI
+
+;
+; New MMX instructions introduced in Katmai
+;
+
+[MASKMOVQ]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mmxreg         \2\x0F\xF7\110                  KATMAI,MMX
+
+[MOVNTQ]
+(Ch_All, Ch_None, Ch_None)
+mem,mmxreg            \2\x0F\xE7\101                  KATMAI,MMX,SM
+
+[PAVGB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mmxreg         \2\x0F\xE0\110                  KATMAI,MMX
+mmxreg,mem            \301\2\x0F\xE0\110              KATMAI,MMX,SM
+
+[PAVGW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mmxreg         \2\x0F\xE3\110                  KATMAI,MMX
+mmxreg,mem            \301\2\x0F\xE3\110              KATMAI,MMX,SM
+
+[PEXTRW]
+(Ch_All, Ch_None, Ch_None)
+reg32,mmxreg,imm      \2\x0F\xC5\110\22               KATMAI,MMX,SB,AR2
+
+[PINSRW]
+(Ch_All, Ch_None, Ch_None)
+; PINSRW is documented as using a reg32, but it's really using only 16 bit
+; -- accept either, but be truthful in disassembly
+mmxreg,reg16,imm      \2\x0F\xC4\110\22               KATMAI,MMX,SB,AR2
+mmxreg,reg32,imm      \2\x0F\xC4\110\22               KATMAI,MMX,SB,AR2,ND
+mmxreg,mem,imm        \301\2\x0F\xC4\110\22           KATMAI,MMX,SB,AR2
+mmxreg,mem16,imm      \301\2\x0F\xC4\110\22           KATMAI,MMX,SB,AR2,ND
+
+[PMAXSW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mmxreg         \2\x0F\xEE\110                  KATMAI,MMX
+mmxreg,mem            \301\2\x0F\xEE\110              KATMAI,MMX,SM
+
+[PMAXUB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mmxreg         \2\x0F\xDE\110                  KATMAI,MMX
+mmxreg,mem            \301\2\x0F\xDE\110              KATMAI,MMX,SM
+
+[PMINSW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mmxreg         \2\x0F\xEA\110                  KATMAI,MMX
+mmxreg,mem            \301\2\x0F\xEA\110              KATMAI,MMX,SM
+
+[PMINUB]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mmxreg         \2\x0F\xDA\110                  KATMAI,MMX
+mmxreg,mem            \301\2\x0F\xDA\110              KATMAI,MMX,SM
+
+[PMOVMSKB]
+(Ch_All, Ch_None, Ch_None)
+reg32,mmxreg          \2\x0F\xD7\110                  KATMAI,MMX
+
+[PMULHUW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mmxreg         \2\x0F\xE4\110                  KATMAI,MMX
+mmxreg,mem            \301\2\x0F\xE4\110              KATMAI,MMX,SM
+
+[PSADBW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mmxreg         \2\x0F\xF6\110                  KATMAI,MMX
+mmxreg,mem            \301\2\x0F\xF6\110              KATMAI,MMX,SM
+
+[PSHUFW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mmxreg,imm     \2\x0F\x70\110\22               KATMAI,MMX,SB,AR2
+mmxreg,mem,imm        \301\2\x0F\x70\110\22           KATMAI,MMX,SM2,SB,AR2
+
+;
+; New K7 Instructions
+;
+
+[PFNACC]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x8A       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x8A           PENT,3DNOW
+
+[PFPNACC]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x8E       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x8E           PENT,3DNOW
+
+[PI2FW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x0C       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x0C           PENT,3DNOW
+
+[PF2IW]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\x1C       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\x1C           PENT,3DNOW
+
+[PSWAPD]
+(Ch_All, Ch_None, Ch_None)
+mmxreg,mem            \301\2\x0F\x0F\110\01\xBB       PENT,3DNOW,SM
+mmxreg,mmxreg         \2\x0F\x0F\110\01\xBB           PENT,3DNOW,SM
+
+[FFREEP]
+(Ch_All, Ch_None, Ch_None)
+fpureg                \1\xDF\10\xC0                   PENT,3DNOW,FPU

compiler/sparc/sparcint.inc

@@ -0,0 +1,65 @@
+{ don't edit, this file is generated from sparcins.dat }
+          'NONE',
+          'ABCD',
+          'ADD','ADDcc','ADDX','ADDXcc',
+          'AND','ANDcc','ANDN','ADDNcc',
+          'BN','BNE','BE','BG','BLE','BGE','BI','BGU','BLEU','BCC',
+          'BCS','BPOS','NEG','BVC','BVS','BA',
+          'CALL',
+          'CBccc',
+          'FBN','FBU','FBG','FBUG','FBL','FBUL','FBLG','FBNE',
+          'FBE','FBUE','FBGE','FBUGE','FBLE','FBULE','FBO','FBA',
+          'FLUSH',
+          'JMPL',
+          'LDSB','LDSH','LDSTUB',
+          'LDUB','LDUH','LD','LDD','LDF','LDFSR','LDDF','LDC','LDCSR','LDDC',
+          'LDSBA','LDSHA','LDUBA','LDUHA','LDA','LDDA',
+          'LDSTUBA',
+          'MULScc',
+          'NOP',
+          'OR','ORcc','ORN','ORNcc',
+          'RDASR','RDY','RDPSR','RDWIM','RDTBR',
+          'RESTORE',
+          'RETT',
+          'SAVE',
+          'SDIV','SDIVcc',
+          'SMUL','SMULcc',
+          'SETHI',
+          'SLL','SRL','SRA',
+          'STB','STH','ST','STD','STF','STDF','STFSR','STDFQ',
+          'STC','STDC','STCSR','STDCQ',
+          'STBA','STHA','STA','STDA',
+          'SUB','SUBcc','SUBX','SUBXcc',
+          'SWAP','SWAPA','Ticc','TADDcc','TSUBcc','TADDccTV','TSUBccTV',
+          'UDIV','UDIVcc',
+          'UMUL','UMULcc',
+          'UNMP',
+          'WRASR','WRY','WRPSR','WRWIM','WRTBR',
+          'XNOR','XNORcc',
+          'XOR','XORcc',
+          {Floating-point instructions}
+          'FiTOs','FiTOd','FiTOq',
+          'FsTOi','FdTOi','FqTOi',
+          'FsTOd','FsTOq',
+          'FdTOs','FdTOq',
+          'FqTOd','FqTOs',
+          'MOVs','NEGs','FABSs',
+          'FSQRTs','FSQRTd','FSQRTq',
+          'FADDs','FADDd','FADDq',
+          'FSUBs','FSUBd','FSUBq',
+          'FMULs','FMULd','FMULQ',
+          'FdMULq','FsMULd',
+          'DIVs','DIVd','FDIVq',
+          'FCMPs','FCMPd','FCMPq',
+          'FCPop1','CPop2',
+          {Synthetic instructions}
+          'btst','bset','bclr','btog',
+          'clr','clrb','clrh',
+          'cmp',
+          'dec','deccc',
+          'inc','inccc',
+          'mov',
+          'not',
+          'set',
+          'skipz','skipnz',
+          'tst'

compiler/sparc/strregs.inc

@@ -0,0 +1,39 @@
+{*****************************************************************************}
+{ File                   : strregs.inc                                        }
+{ Author                 : Mazen NEIFER                                       }
+{ Project                : Free Pascal Compiler (FPC)                         }
+{ Creation date          : 2002\05\08                                         }
+{ Last modification date : 2002\06\01                                         }
+{ Licence                : GPL                                                }
+{ Bug report             : [email protected]                        }
+{*****************************************************************************}
+'NO',
+  {General purpose global registers}
+'G0','G1','G2','G3','G4','G5','G6','G7',
+  {General purpose out registers}
+'O0','O1','O2','O3','O4','O5','O6','O7',
+  {General purpose local registers}
+'L0','L1','L2','L3','L4','L5','L6','L7',
+  {General purpose in registers}
+'I0','I1','I2','I3','I4','I5','I6','I7',
+  {Floating point registers}
+'F0','F1','F2','F3','F4','F5','F6','F7',
+'F8','F9','F10','F11','F12','F13','F14','F15',
+'F16','F17','F18','F19','F20','F21','F22','F23',
+'F24','F25','F26','F27','F28','F29','F30','F31',
+  {Floating point status/"front of queue" registers}
+'FSR','FQ',
+  {Coprocessor registers}
+'C0','C1','C2','C3','C4','C5','C6','C7',
+'C8','C9','C10','C11','C12','C13','C14','C15',
+'C16','C17','C18','C19','C20','C21','C22','C23',
+'C24','C25','C26','C27','C28','C29','C30','C31',
+  {Coprocessor status/queue registers}
+'CSR','CQ',
+  {"Program status"/"Trap vactor base address register"/"Window invalid mask"/Y registers}
+'PSR','TBR','WIM','Y',
+  {Ancillary state registers}
+'ASR0','ASR1','ASR2','ASR3','ASR4','ASR5','ASR6','ASR7',
+'ASR8','ASR9','ASR10','ASR11','ASR12','ASR13','ASR14','ASR15',
+'ASR16','ASR17','ASR18','ASR19','ASR20','ASR21','ASR22','ASR23',
+'ASR24','ASR25','ASR26','ASR27','ASR28','ASR29','ASR30','ASR31'

compiler/sparc/tgcpu.pas

@@ -0,0 +1,749 @@
+{
+    $Id$
+    Copyright (C) 1998-2000 by Florian Klaempfl
+
+    This unit handles the temporary variables stuff for i386
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+unit tgcpu;
+
+{$INCLUDE fpcdefs.inc}
+
+interface
+
+    uses
+       globals,
+       cgbase,verbose,aasm,
+       node,
+       cpubase,cpuasm
+       ;
+
+    type
+       tregisterset = set of tregister;
+
+       tpushed = array[R_EAX..R_MM6] of boolean;
+       tsaved = array[R_EAX..R_MM6] of longint;
+
+    const
+       usablereg32 : byte = 4;
+
+       { this value is used in tsaved, if the register isn't saved }
+       reg_not_saved = $7fffffff;
+{$ifdef SUPPORT_MMX}
+       usableregmmx : byte = 8;
+{$endif SUPPORT_MMX}
+
+    var
+       { tries to hold the amount of times which the current tree is processed  }
+       t_times : longint;
+
+{$ifdef TEMPREGDEBUG}
+    procedure testregisters32;
+{$endif TEMPREGDEBUG}
+    function getregisterint : tregister;
+    function getaddressregister: tregister;
+    procedure ungetregister32(r : tregister);
+    { tries to allocate the passed register, if possible }
+    function getexplicitregister32(r : tregister) : tregister;
+{$ifdef SUPPORT_MMX}
+    function getregistermmx : tregister;
+    procedure ungetregistermmx(r : tregister);
+{$endif SUPPORT_MMX}
+
+    function isaddressregister(reg: tregister): boolean;
+
+    procedure ungetregister(r : tregister);
+
+    procedure cleartempgen;
+    procedure del_reference(const ref : treference);
+    procedure del_locref(const location : tlocation);
+    procedure del_location(const l : tlocation);
+
+    { pushs and restores registers }
+    procedure pushusedregisters(var pushed : tpushed;b : byte);
+    procedure popusedregisters(const pushed : tpushed);
+
+    { saves register variables (restoring happens automatically (JM) }
+    procedure saveregvars(b: byte);
+
+    { saves and restores used registers to temp. values }
+    procedure saveusedregisters(var saved : tsaved;b : byte);
+    procedure restoreusedregisters(const saved : tsaved);
+
+    { increments the push count of all registers in b}
+    procedure incrementregisterpushed(b : byte);
+
+    procedure clearregistercount;
+    procedure resetusableregisters;
+
+    { corrects the fpu stack register by ofs }
+    function correct_fpuregister(r : tregister;ofs : byte) : tregister;
+
+    type
+{$ifdef SUPPORT_MMX}
+       regvar_longintarray = array[R_EAX..R_MM6] of longint;
+       regvar_booleanarray = array[R_EAX..R_MM6] of boolean;
+       regvar_ptreearray = array[R_EAX..R_MM6] of tnode;
+{$else SUPPORT_MMX}
+       regvar_longintarray = array[R_EAX..R_EDI] of longint;
+       regvar_booleanarray = array[R_EAX..R_EDI] of boolean;
+       regvar_ptreearray = array[R_EAX..R_EDI] of tnode;
+{$endif SUPPORT_MMX}
+
+    var
+       unused,usableregs : tregisterset;
+       c_usableregs : longint;
+
+       { uses only 1 byte while a set uses in FPC 32 bytes }
+       usedinproc : byte;
+
+       fpuvaroffset : byte;
+
+       { count, how much a register must be pushed if it is used as register }
+       { variable                                                           }
+       reg_pushes : regvar_longintarray;
+       is_reg_var : regvar_booleanarray;
+       regvar_loaded: regvar_booleanarray;
+
+{$ifdef TEMPREGDEBUG}
+       reg_user   : regvar_ptreearray;
+       reg_releaser : regvar_ptreearray;
+{$endif TEMPREGDEBUG}
+
+
+implementation
+
+    uses
+      globtype,temp_gen,tainst,regvars;
+
+    procedure incrementregisterpushed(b : byte);
+
+      var
+         regi : tregister;
+
+      begin
+         for regi:=R_EAX to R_EDI do
+           begin
+              if (b and ($80 shr word(regi)))<>0 then
+                inc(reg_pushes[regi],t_times*2);
+           end;
+      end;
+
+    procedure pushusedregisters(var pushed : tpushed;b : byte);
+
+      var
+         r : tregister;
+{$ifdef SUPPORT_MMX}
+         hr : preference;
+{$endif}
+      begin
+         usedinproc:=usedinproc or b;
+         for r:=R_EAX to R_EBX do
+           begin
+              pushed[r]:=false;
+              { if the register is used by the calling subroutine    }
+              if ((b and ($80 shr byte(r)))<>0) then
+                begin
+                  { and is present in use }
+                  if not is_reg_var[r] then
+                    if not(r in unused) then
+                     begin
+                        { then save it }
+                        exprasmlist.concat(Taicpu.Op_reg(A_PUSH,S_L,r));
+
+                        { here was a big problem  !!!!!}
+                        { you cannot do that for a register that is
+                        globally assigned to a var
+                        this also means that you must push it much more
+                        often, but there must be a better way
+                        maybe by putting the value back to the stack !! }
+                        if not(is_reg_var[r]) then
+                          begin
+                            unused:=unused+[r];
+{$ifdef TEMPREGDEBUG}
+                            inc(usablereg32);
+{$endif TEMPREGDEBUG}
+                          end;
+                        pushed[r]:=true;
+                     end;
+                end;
+           end;
+{$ifdef SUPPORT_MMX}
+         for r:=R_MM0 to R_MM6 do
+           begin
+              pushed[r]:=false;
+              { if the mmx register is in use, save it }
+              if not(r in unused) then
+                begin
+                   exprasmList.concat(Taicpu.Op_const_reg(A_SUB,S_L,8,R_ESP));
+                   new(hr);
+                   reset_reference(hr^);
+                   hr^.base:=R_ESP;
+                   exprasmList.concat(Taicpu.Op_reg_ref(A_MOVQ,S_NO,r,hr));
+                   if not(is_reg_var[r]) then
+                     begin
+                       unused:=unused+[r];
+{$ifdef TEMPREGDEBUG}
+                       inc(usableregmmx);
+{$endif TEMPREGDEBUG}
+                     end;
+                   pushed[r]:=true;
+                end;
+           end;
+{$endif SUPPORT_MMX}
+{$ifdef TEMPREGDEBUG}
+        testregisters32;
+{$endif TEMPREGDEBUG}
+      end;
+
+
+    procedure saveregvars(b: byte);
+
+      var
+         r : tregister;
+
+      begin
+         if not(cs_regalloc in aktglobalswitches) then
+           exit;
+         for r:=R_EAX to R_EBX do
+           { if the register is used by the calling subroutine    }
+           if ((b and ($80 shr byte(r)))<>0) and is_reg_var[r] then
+             store_regvar(exprasmlist,r)
+      end;
+
+
+    procedure saveusedregisters(var saved : tsaved;b : byte);
+
+      var
+         r : tregister;
+         hr : treference;
+
+      begin
+         usedinproc:=usedinproc or b;
+         for r:=R_EAX to R_EBX do
+           begin
+              saved[r]:=reg_not_saved;
+              { if the register is used by the calling subroutine    }
+              if ((b and ($80 shr byte(r)))<>0) then
+                begin
+                   { and is present in use }
+                   if not(r in unused) then
+                     begin
+                        { then save it }
+                        gettempofsizereference(4,hr);
+                        saved[r]:=hr.offset;
+                        exprasmList.concat(Taicpu.Op_reg_ref(A_MOV,S_L,r,newreference(hr)));
+                        { here was a big problem  !!!!!}
+                        { you cannot do that for a register that is
+                        globally assigned to a var
+                        this also means that you must push it much more
+                        often, but there must be a better way
+                        maybe by putting the value back to the stack !! }
+                        if not(is_reg_var[r]) then
+                          begin
+                            unused:=unused+[r];
+{$ifdef TEMPREGDEBUG}
+                            inc(usablereg32);
+{$endif TEMPREGDEBUG}
+                          end;
+                     end;
+                end;
+           end;
+{$ifdef SUPPORT_MMX}
+         for r:=R_MM0 to R_MM6 do
+           begin
+              saved[r]:=reg_not_saved;
+              { if the mmx register is in use, save it }
+              if not(r in unused) then
+                begin
+                   gettempofsizereference(8,hr);
+                   exprasmList.concat(Taicpu.Op_reg_ref(A_MOVQ,S_NO,r,newreference(hr)));
+                   if not(is_reg_var[r]) then
+                     begin
+                       unused:=unused+[r];
+{$ifdef TEMPREGDEBUG}
+                       inc(usableregmmx);
+{$endif TEMPREGDEBUG}
+                     end;
+                   saved[r]:=hr.offset;
+                end;
+           end;
+{$endif SUPPORT_MMX}
+{$ifdef TEMPREGDEBUG}
+        testregisters32;
+{$endif TEMPREGDEBUG}
+      end;
+
+    procedure popusedregisters(const pushed : tpushed);
+
+      var
+         r : tregister;
+{$ifdef SUPPORT_MMX}
+         hr : preference;
+{$endif SUPPORT_MMX}
+      begin
+         { restore in reverse order: }
+{$ifdef SUPPORT_MMX}
+         for r:=R_MM6 downto R_MM0 do
+           begin
+              if pushed[r] then
+                begin
+                   new(hr);
+                   reset_reference(hr^);
+                   hr^.base:=R_ESP;
+                   exprasmList.concat(Taicpu.Op_ref_reg(
+                     A_MOVQ,S_NO,hr,r));
+                   exprasmList.concat(Taicpu.Op_const_reg(
+                     A_ADD,S_L,8,R_ESP));
+                   unused:=unused-[r];
+{$ifdef TEMPREGDEBUG}
+                   dec(usableregmmx);
+{$endif TEMPREGDEBUG}
+                end;
+           end;
+{$endif SUPPORT_MMX}
+         for r:=R_EBX downto R_EAX do
+           if pushed[r] then
+             begin
+                exprasmList.concat(Taicpu.Op_reg(A_POP,S_L,r));
+{$ifdef TEMPREGDEBUG}
+                if not (r in unused) then
+                  { internalerror(10)
+                    in cg386cal we always restore regs
+                    that appear as used
+                    due to a unused tmep storage PM }
+                else
+                  dec(usablereg32);
+{$endif TEMPREGDEBUG}
+                unused:=unused-[r];
+             end;
+{$ifdef TEMPREGDEBUG}
+        testregisters32;
+{$endif TEMPREGDEBUG}
+      end;
+
+    procedure restoreusedregisters(const saved : tsaved);
+      var
+         r : tregister;
+         hr : treference;
+
+      begin
+         { restore in reverse order: }
+{$ifdef SUPPORT_MMX}
+         for r:=R_MM6 downto R_MM0 do
+           begin
+              if saved[r]<>reg_not_saved then
+                begin
+                   reset_reference(hr);
+                   hr.base:=frame_pointer;
+                   hr.offset:=saved[r];
+                   exprasmList.concat(Taicpu.Op_ref_reg(
+                     A_MOVQ,S_NO,newreference(hr),r));
+                   unused:=unused-[r];
+{$ifdef TEMPREGDEBUG}
+                   dec(usableregmmx);
+{$endif TEMPREGDEBUG}
+                   ungetiftemp(hr);
+                end;
+           end;
+{$endif SUPPORT_MMX}
+         for r:=R_EBX downto R_EAX do
+           if saved[r]<>reg_not_saved then
+             begin
+                reset_reference(hr);
+                hr.base:=frame_pointer;
+                hr.offset:=saved[r];
+                exprasmList.concat(Taicpu.Op_ref_reg(A_MOV,S_L,newreference(hr),r));
+{$ifdef TEMPREGDEBUG}
+                if not (r in unused) then
+                  internalerror(10)
+                else
+                  dec(usablereg32);
+{$endif TEMPREGDEBUG}
+                unused:=unused-[r];
+                ungetiftemp(hr);
+             end;
+{$ifdef TEMPREGDEBUG}
+        testregisters32;
+{$endif TEMPREGDEBUG}
+      end;
+
+    procedure ungetregister(r : tregister);
+
+      begin
+         if r in [R_EAX,R_ECX,R_EDX,R_EBX,R_ESP,R_EBP,R_ESI,R_EDI] then
+           ungetregister32(r)
+          else if r in [R_AX,R_CX,R_DX,R_BX,R_SP,R_BP,R_SI,R_DI] then
+           ungetregister32(reg16toreg32(r))
+         else if r in [R_AL,R_BL,R_CL,R_DL] then
+           ungetregister32(reg8toreg32(r))
+{$ifdef SUPPORT_MMX}
+         else if r in [R_MM0..R_MM6] then
+           ungetregistermmx(r)
+{$endif SUPPORT_MMX}
+         else internalerror(18);
+      end;
+
+    procedure ungetregister32(r : tregister);
+
+      begin
+         if (r = R_EDI) or
+            ((not assigned(procinfo^._class)) and (r = R_ESI)) then
+           begin
+             exprasmList.concat(Tairegalloc.DeAlloc(r));
+             exit;
+           end;
+         if cs_regalloc in aktglobalswitches then
+           begin
+              { takes much time }
+              if not(r in usableregs) then
+                exit;
+              unused:=unused+[r];
+              inc(usablereg32);
+           end
+         else
+           begin
+              if not(r in [R_EAX,R_EBX,R_ECX,R_EDX]) then
+                exit;
+{$ifdef TEMPREGDEBUG}
+                if (r in unused) then
+{$ifdef EXTTEMPREGDEBUG}
+                  begin
+                    Comment(V_Debug,'register freed twice '+reg2str(r));
+                    testregisters32;
+                    exit;
+                  end
+{$else EXTTEMPREGDEBUG}
+                  exit
+{$endif EXTTEMPREGDEBUG}
+                else
+{$endif TEMPREGDEBUG}
+                  inc(usablereg32);
+              unused:=unused+[r];
+{$ifdef TEMPREGDEBUG}
+              reg_releaser[r]:=curptree^;
+{$endif TEMPREGDEBUG}
+           end;
+         exprasmList.concat(Tairegalloc.DeAlloc(r));
+{$ifdef TEMPREGDEBUG}
+        testregisters32;
+{$endif TEMPREGDEBUG}
+      end;
+
+{$ifdef SUPPORT_MMX}
+    function getregistermmx : tregister;
+
+      var
+         r : tregister;
+
+      begin
+         dec(usableregmmx);
+         for r:=R_MM0 to R_MM6 do
+           if r in unused then
+             begin
+                unused:=unused-[r];
+                usedinproc:=usedinproc or ($80 shr byte(R_EAX));
+                getregistermmx:=r;
+                exit;
+             end;
+         internalerror(10);
+      end;
+
+    procedure ungetregistermmx(r : tregister);
+
+      begin
+         if cs_regalloc in aktglobalswitches then
+           begin
+              { takes much time }
+              if not(r in usableregs) then
+                exit;
+              unused:=unused+[r];
+              inc(usableregmmx);
+           end
+         else
+           begin
+              unused:=unused+[r];
+              inc(usableregmmx);
+           end;
+      end;
+{$endif SUPPORT_MMX}
+
+    function isaddressregister(reg: tregister): boolean;
+
+      begin
+        isaddressregister := true;
+      end;
+
+    procedure del_reference(const ref : treference);
+
+      begin
+         if ref.is_immediate then
+           exit;
+         ungetregister32(ref.base);
+         ungetregister32(ref.index);
+      end;
+
+
+    procedure del_locref(const location : tlocation);
+      begin
+         if (location.loc<>loc_mem) and (location.loc<>loc_reference) then
+           exit;
+         if location.reference.is_immediate then
+           exit;
+         ungetregister32(location.reference.base);
+         ungetregister32(location.reference.index);
+      end;
+
+
+    procedure del_location(const l : tlocation);
+      begin
+        case l.loc of
+          LOC_REGISTER :
+            ungetregister(l.register);
+          LOC_MEM,LOC_REFERENCE :
+            del_reference(l.reference);
+        end;
+      end;
+
+
+{$ifdef TEMPREGDEBUG}
+    procedure testregisters32;
+     var test : byte;
+       begin
+         test:=0;
+         if R_EAX in unused then
+           inc(test);
+         if R_EBX in unused then
+           inc(test);
+         if R_ECX in unused then
+           inc(test);
+         if R_EDX in unused then
+           inc(test);
+         if test<>usablereg32 then
+           internalerror(10);
+       end;
+{$endif TEMPREGDEBUG}
+
+    function getregisterint : tregister;
+      begin
+         if usablereg32=0 then
+           internalerror(10);
+{$ifdef TEMPREGDEBUG}
+         if curptree^^.usableregs-usablereg32>curptree^^.registers32 then
+           internalerror(10);
+{$endif TEMPREGDEBUG}
+{$ifdef EXTTEMPREGDEBUG}
+         if curptree^^.usableregs-usablereg32>curptree^^.reallyusedregs then
+           curptree^^.reallyusedregs:=curptree^^.usableregs-usablereg32;
+{$endif EXTTEMPREGDEBUG}
+         dec(usablereg32);
+         if R_EAX in unused then
+           begin
+              unused:=unused-[R_EAX];
+              usedinproc:=usedinproc or ($80 shr byte(R_EAX));
+              getregisterint:=R_EAX;
+{$ifdef TEMPREGDEBUG}
+              reg_user[R_EAX]:=curptree^;
+{$endif TEMPREGDEBUG}
+              exprasmList.concat(Tairegalloc.Alloc(R_EAX));
+           end
+         else if R_EDX in unused then
+           begin
+              unused:=unused-[R_EDX];
+              usedinproc:=usedinproc or ($80 shr byte(R_EDX));
+              getregisterint:=R_EDX;
+{$ifdef TEMPREGDEBUG}
+              reg_user[R_EDX]:=curptree^;
+{$endif TEMPREGDEBUG}
+              exprasmList.concat(Tairegalloc.Alloc(R_EDX));
+           end
+         else if R_EBX in unused then
+           begin
+              unused:=unused-[R_EBX];
+              usedinproc:=usedinproc or ($80 shr byte(R_EBX));
+              getregisterint:=R_EBX;
+{$ifdef TEMPREGDEBUG}
+              reg_user[R_EBX]:=curptree^;
+{$endif TEMPREGDEBUG}
+              exprasmList.concat(Tairegalloc.Alloc(R_EBX));
+           end
+         else if R_ECX in unused then
+           begin
+              unused:=unused-[R_ECX];
+              usedinproc:=usedinproc or ($80 shr byte(R_ECX));
+              getregisterint:=R_ECX;
+{$ifdef TEMPREGDEBUG}
+              reg_user[R_ECX]:=curptree^;
+{$endif TEMPREGDEBUG}
+              exprasmList.concat(Tairegalloc.Alloc(R_ECX));
+           end
+         else internalerror(10);
+{$ifdef TEMPREGDEBUG}
+         testregisters32;
+{$endif TEMPREGDEBUG}
+      end;
+
+
+    function getaddressregister: tregister;
+
+      begin
+        getaddressregister := getregisterint;
+      end;
+
+    function getexplicitregister32(r : tregister) : tregister;
+
+      begin
+         if r in [R_ESI,R_EDI] then
+           begin
+             exprasmList.concat(Tairegalloc.Alloc(r));
+             getexplicitregister32 := r;
+             exit;
+           end;
+         if r in unused then
+           begin
+              dec(usablereg32);
+{$ifdef TEMPREGDEBUG}
+              if curptree^^.usableregs-usablereg32>curptree^^.registers32 then
+                internalerror(10);
+              reg_user[r]:=curptree^;
+{$endif TEMPREGDEBUG}
+              unused:=unused-[r];
+              usedinproc:=usedinproc or ($80 shr byte(r));
+              exprasmList.concat(Tairegalloc.Alloc(r));
+              getexplicitregister32:=r;
+{$ifdef TEMPREGDEBUG}
+         testregisters32;
+{$endif TEMPREGDEBUG}
+           end
+         else
+           getexplicitregister32:=getregisterint;
+      end;
+
+    procedure cleartempgen;
+
+      begin
+         unused:=usableregs;
+         usablereg32:=c_usableregs;
+         {fpuvaroffset:=0;
+          this must only be resetted at each procedure
+          compilation start PM }
+      end;
+
+
+   procedure clearregistercount;
+      var
+        regi : tregister;
+      begin
+{$ifdef SUPPORT_MMX}
+         for regi:=R_EAX to R_MM6 do
+           begin
+              reg_pushes[regi]:=0;
+              is_reg_var[regi]:=false;
+           end;
+{$else SUPPORT_MMX}
+         for regi:=R_EAX to R_EDI do
+           begin
+              reg_pushes[regi]:=0;
+              is_reg_var[regi]:=false;
+           end;
+{$endif SUPPORT_MMX}
+      end;
+
+   function correct_fpuregister(r : tregister;ofs : byte) : tregister;
+
+     begin
+        correct_fpuregister:=tregister(longint(r)+ofs);
+     end;
+
+   procedure resetusableregisters;
+      begin
+{$ifdef SUPPORT_MMX}
+        usableregs:=[R_EAX,R_EBX,R_ECX,R_EDX,R_MM0..R_MM6];
+        c_usableregs:=4;
+        usableregmmx:=8;
+{$else}
+        usableregs:=[R_EAX,R_EBX,R_ECX,R_EDX];
+        c_usableregs:=4;
+{$endif SUPPORT_MMX}
+        fillchar(regvar_loaded,sizeof(regvar_loaded),false);
+        fillchar(is_reg_var,sizeof(is_reg_var),false);
+        fpuvaroffset:=0;
+      end;
+
+begin
+  resetusableregisters;
+end.
+{
+  $Log$
+  Revision 1.1  2002-08-22 08:30:50  mazen
+  first insertion 2002\08\22
+
+  Revision 1.8  2001/12/31 09:53:16  jonas
+    * changed remaining "getregister32" calls to "getregisterint"
+
+  Revision 1.7  2001/12/29 15:29:59  jonas
+    * powerpc/cgcpu.pas compiles :)
+    * several powerpc-related fixes
+    * cpuasm unit is now based on common tainst unit
+    + nppcmat unit for powerpc (almost complete)
+
+  Revision 1.5  2001/08/26 13:37:03  florian
+    * some cg reorganisation
+    * some PPC updates
+
+  Revision 1.4  2001/04/13 01:22:21  peter
+    * symtable change to classes
+    * range check generation and errors fixed, make cycle DEBUG=1 works
+    * memory leaks fixed
+
+  Revision 1.3  2000/12/25 00:07:34  peter
+    + new tlinkedlist class (merge of old tstringqueue,tcontainer and
+      tlinkedlist objects)
+
+  Revision 1.2  2000/12/05 11:44:34  jonas
+    + new integer regvar handling, should be much more efficient
+
+  Revision 1.1  2000/11/29 00:30:51  florian
+    * unused units removed from uses clause
+    * some changes for widestrings
+
+  Revision 1.9  2000/10/31 22:30:13  peter
+    * merged asm result patch part 2
+
+  Revision 1.8  2000/10/14 10:14:56  peter
+    * moehrendorf oct 2000 rewrite
+
+  Revision 1.7  2000/09/30 16:08:46  peter
+    * more cg11 updates
+
+  Revision 1.6  2000/09/24 15:06:32  peter
+    * use defines.inc
+
+  Revision 1.5  2000/08/27 16:11:55  peter
+    * moved some util functions from globals,cobjects to cutils
+    * splitted files into finput,fmodule
+
+  Revision 1.4  2000/08/05 13:32:39  peter
+    * fixed build prob without support_mmx
+
+  Revision 1.3  2000/08/04 05:09:49  jonas
+    * forgot to commit :( (part of regvar changes)
+
+  Revision 1.2  2000/07/13 11:32:52  michael
+  + removed logs
+}