* register names fixed

git-svn-id: branches/z80@35670 -

compiler/utils/mkz80reg.pp

@@ -15,6 +15,9 @@
 {$mode objfpc}
 program mkz80reg;
 
+uses
+  sysutils;
+
 const Version = '1.00';
       max_regcount = 200;
 
@@ -24,8 +27,6 @@ var s : string;
     regcount:byte;
     regcount_bsstart:byte;
     names,
-    regtypes,
-    supregs,
     numbers,
     stdnames,
     stabs,dwarf : array[0..max_regcount-1] of string[63];
@@ -168,9 +169,7 @@ begin
         i:=1;
         names[regcount]:=readstr;
         readcomma;
-        regtypes[regcount]:=readstr;
-        readcomma;
-        supregs[regcount]:=readstr;
+        numbers[regcount]:=readstr;
         readcomma;
         stdnames[regcount]:=readstr;
         readcomma;
@@ -178,13 +177,12 @@ begin
         readcomma;
         dwarf[regcount]:=readstr;
         { Create register number }
-        if supregs[regcount][1]<>'$' then
+        if numbers[regcount][1]<>'$' then
           begin
             writeln('Missing $ before number, at line ',line);
             writeln('Line: "',s,'"');
             halt(1);
           end;
-        numbers[regcount]:=regtypes[regcount]+'0000'+copy(supregs[regcount],2,255);
         if i<length(s) then
           begin
             writeln('Extra chars at end of line, at line ',line);
@@ -234,7 +232,7 @@ begin
         end
       else
         first:=false;
-      writeln(supfile,'RS_',names[i],' = ',supregs[i],';');
+      writeln(supfile,'RS_',names[i],' = ',StrToInt(numbers[i]) and $ff,';');
       writeln(confile,'NR_'+names[i],' = ','tregister(',numbers[i],')',';');
       write(numfile,'tregister(',numbers[i],')');
       write(stdfile,'''',stdnames[i],'''');

compiler/z80/cgcpu.pas

@@ -133,9 +133,7 @@ unit cgcpu;
       begin
         inherited init_register_allocators;
         rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
-            [RS_R18,RS_R19,RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
-             RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,
-             RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17],first_int_imreg,[]);
+            [RS_BC,RS_DE,RS_HL],first_int_imreg,[]);
       end;
 
 
@@ -784,37 +782,37 @@ unit cgcpu;
              end;
            OP_ADD:
              begin
-               curvalue:=a and mask;
-               if curvalue=0 then
-                 list.concat(taicpu.op_reg_reg(A_ADD,reg,NR_R1))
-               else if (curvalue=1) and (tcgsize2size[size]=1) then
-                 list.concat(taicpu.op_reg(A_INC,reg))
-               else
-                 begin
-                   tmpreg:=getintregister(list,OS_8);
-                   a_load_const_reg(list,OS_8,curvalue,tmpreg);
-                   list.concat(taicpu.op_reg_reg(A_ADD,reg,tmpreg));
-                 end;
-               if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
-                 begin
-                   for i:=2 to tcgsize2size[size] do
-                     begin
-                       NextReg;
-                       mask:=mask shl 8;
-                       inc(shift,8);
-                       curvalue:=(qword(a) and mask) shr shift;
-                       { decrease pressure on upper half of registers by using ADC ...,R1 instead
-                         of ADD ...,0 }
-                       if curvalue=0 then
-                         list.concat(taicpu.op_reg_reg(A_ADC,reg,NR_R1))
-                       else
-                         begin
-                           tmpreg:=getintregister(list,OS_8);
-                           a_load_const_reg(list,OS_8,curvalue,tmpreg);
-                           list.concat(taicpu.op_reg_reg(A_ADC,reg,tmpreg));
-                         end;
-                     end;
-                 end;
+               //curvalue:=a and mask;
+               //if curvalue=0 then
+               //  list.concat(taicpu.op_reg_reg(A_ADD,reg,NR_R1))
+               //else if (curvalue=1) and (tcgsize2size[size]=1) then
+               //  list.concat(taicpu.op_reg(A_INC,reg))
+               //else
+               //  begin
+               //    tmpreg:=getintregister(list,OS_8);
+               //    a_load_const_reg(list,OS_8,curvalue,tmpreg);
+               //    list.concat(taicpu.op_reg_reg(A_ADD,reg,tmpreg));
+               //  end;
+               //if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
+               //  begin
+               //    for i:=2 to tcgsize2size[size] do
+               //      begin
+               //        NextReg;
+               //        mask:=mask shl 8;
+               //        inc(shift,8);
+               //        curvalue:=(qword(a) and mask) shr shift;
+               //        { decrease pressure on upper half of registers by using ADC ...,R1 instead
+               //          of ADD ...,0 }
+               //        if curvalue=0 then
+               //          list.concat(taicpu.op_reg_reg(A_ADC,reg,NR_R1))
+               //        else
+               //          begin
+               //            tmpreg:=getintregister(list,OS_8);
+               //            a_load_const_reg(list,OS_8,curvalue,tmpreg);
+               //            list.concat(taicpu.op_reg_reg(A_ADC,reg,tmpreg));
+               //          end;
+               //      end;
+               //  end;
              end;
          else
            begin
@@ -861,19 +859,19 @@ unit cgcpu;
          shift:=0;
          for i:=1 to tcgsize2size[size] do
            begin
-             if ((qword(a) and mask) shr shift)=0 then
-               emit_mov(list,reg,NR_R1)
-             else
-               begin
-                 getcpuregister(list,NR_R26);
-                 list.concat(taicpu.op_reg_const(A_LDI,NR_R26,(qword(a) and mask) shr shift));
-                 a_load_reg_reg(list,OS_8,OS_8,NR_R26,reg);
-                 ungetcpuregister(list,NR_R26);
-               end;
-
-             mask:=mask shl 8;
-             inc(shift,8);
-             reg:=GetNextReg(reg);
+             //if ((qword(a) and mask) shr shift)=0 then
+             //  emit_mov(list,reg,NR_R1)
+             //else
+             //  begin
+             //    getcpuregister(list,NR_R26);
+             //    list.concat(taicpu.op_reg_const(A_LDI,NR_R26,(qword(a) and mask) shr shift));
+             //    a_load_reg_reg(list,OS_8,OS_8,NR_R26,reg);
+             //    ungetcpuregister(list,NR_R26);
+             //  end;
+             //
+             //mask:=mask shl 8;
+             //inc(shift,8);
+             //reg:=GetNextReg(reg);
            end;
        end;
 
@@ -1606,9 +1604,9 @@ unit cgcpu;
         else
         }
           begin
-            list.concat(taicpu.op_reg_const(A_LDI,reg,1));
-            a_jmp_flags(list,f,l);
-            emit_mov(list,reg,NR_R1);
+            //list.concat(taicpu.op_reg_const(A_LDI,reg,1));
+            //a_jmp_flags(list,f,l);
+            //emit_mov(list,reg,NR_R1);
           end;
         cg.a_label(list,l);
       end;
@@ -1767,46 +1765,46 @@ unit cgcpu;
         { every byte counts for avr, so if a subroutine is marked as non-returning, we do
           not generate any exit code, so we really trust the noreturn directive
         }
-        if po_noreturn in current_procinfo.procdef.procoptions then
-          exit;
-        if po_interrupt in current_procinfo.procdef.procoptions then
-          begin
-            regs:=rg[R_INTREGISTER].used_in_proc;
-            if current_procinfo.framepointer<>NR_NO then
-              begin
-                regs:=regs+[RS_R28,RS_R29];
-                LocalSize:=current_procinfo.calc_stackframe_size;
-                a_adjust_sp(list,LocalSize);
-              end;
-
-            { Reload SREG }
-            regs:=regs+[RS_R0];
-
-            list.concat(taicpu.op_reg(A_POP, NR_R0));
-            list.concat(taicpu.op_const_reg(A_OUT, $3F, NR_R0));
-
-            for reg:=RS_R0 to RS_R31 do
-              if reg in regs then
-                list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
-
-            list.concat(taicpu.op_none(A_RETI));
-          end
-        else if not(nostackframe) then
-          begin
-            regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
-            if current_procinfo.framepointer<>NR_NO then
-              begin
-                regs:=regs+[RS_R28,RS_R29];
-                LocalSize:=current_procinfo.calc_stackframe_size;
-                a_adjust_sp(list,LocalSize);
-              end;
-            for reg:=RS_R0 to RS_R31 do
-              if reg in regs then
-                list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
-            list.concat(taicpu.op_none(A_RET));
-          end
-        else
-          list.concat(taicpu.op_none(A_RET));
+        //if po_noreturn in current_procinfo.procdef.procoptions then
+        //  exit;
+        //if po_interrupt in current_procinfo.procdef.procoptions then
+        //  begin
+        //    regs:=rg[R_INTREGISTER].used_in_proc;
+        //    if current_procinfo.framepointer<>NR_NO then
+        //      begin
+        //        regs:=regs+[RS_R28,RS_R29];
+        //        LocalSize:=current_procinfo.calc_stackframe_size;
+        //        a_adjust_sp(list,LocalSize);
+        //      end;
+        //
+        //    { Reload SREG }
+        //    regs:=regs+[RS_R0];
+        //
+        //    list.concat(taicpu.op_reg(A_POP, NR_R0));
+        //    list.concat(taicpu.op_const_reg(A_OUT, $3F, NR_R0));
+        //
+        //    for reg:=RS_R0 to RS_R31 do
+        //      if reg in regs then
+        //        list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
+        //
+        //    list.concat(taicpu.op_none(A_RETI));
+        //  end
+        //else if not(nostackframe) then
+        //  begin
+        //    regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
+        //    if current_procinfo.framepointer<>NR_NO then
+        //      begin
+        //        regs:=regs+[RS_R28,RS_R29];
+        //        LocalSize:=current_procinfo.calc_stackframe_size;
+        //        a_adjust_sp(list,LocalSize);
+        //      end;
+        //    for reg:=RS_R0 to RS_R31 do
+        //      if reg in regs then
+        //        list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
+        //    list.concat(taicpu.op_none(A_RET));
+        //  end
+        //else
+        //  list.concat(taicpu.op_none(A_RET));
       end;
 
 

compiler/z80/cpubase.pas

@@ -85,19 +85,8 @@ unit cpubase;
       { Available Registers }
       {$i rz80con.inc}
 
-      NR_XLO = NR_R26;
-      NR_XHI = NR_R27;
-      NR_YLO = NR_R28;
-      NR_YHI = NR_R29;
-      NR_ZLO = NR_R30;
-      NR_ZHI = NR_R31;
-
-      NIO_SREG = $3f;
-      NIO_SP_LO = $3d;
-      NIO_SP_HI = $3e;
-
       { Integer Super registers first and last }
-      first_int_supreg = RS_R0;
+      first_int_supreg = RS_A;
       first_int_imreg = $20;
 
       { Float Super register first and last }
@@ -122,7 +111,7 @@ unit cpubase;
         {$i rz80dwa.inc}
       );
       { registers which may be destroyed by calls }
-      VOLATILE_INTREGISTERS = [RS_R0,RS_R1,RS_R18..RS_R27,RS_R30,RS_R31];
+      VOLATILE_INTREGISTERS = [RS_A,RS_BC,RS_DE,RS_HL];
       VOLATILE_FPUREGISTERS = [];
 
     type
@@ -190,21 +179,13 @@ unit cpubase;
 *****************************************************************************}
 
     const
-      firstsaveintreg = RS_R4;
-      lastsaveintreg  = RS_R10;
+      firstsaveintreg = RS_INVALID;
+      lastsaveintreg  = RS_INVALID;
       firstsavefpureg = RS_INVALID;
       lastsavefpureg  = RS_INVALID;
       firstsavemmreg  = RS_INVALID;
       lastsavemmreg   = RS_INVALID;
 
-      maxvarregs = 7;
-      varregs : Array [1..maxvarregs] of tsuperregister =
-                (RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,RS_R10);
-
-      maxfpuvarregs = 1;
-      fpuvarregs : Array [1..maxfpuvarregs] of tsuperregister =
-                (RS_INVALID);
-
 {*****************************************************************************
                           Default generic sizes
 *****************************************************************************}
@@ -229,25 +210,25 @@ unit cpubase;
 *****************************************************************************}
 
       { Stack pointer register }
-      NR_STACK_POINTER_REG = NR_R13;
-      RS_STACK_POINTER_REG = RS_R13;
+      NR_STACK_POINTER_REG = NR_SP;
+      RS_STACK_POINTER_REG = RS_SP;
       { Frame pointer register }
-      RS_FRAME_POINTER_REG = RS_R28;
-      NR_FRAME_POINTER_REG = NR_R28;
+      RS_FRAME_POINTER_REG = RS_IX;
+      NR_FRAME_POINTER_REG = NR_IX;
       { Register for addressing absolute data in a position independant way,
         such as in PIC code. The exact meaning is ABI specific. For
         further information look at GCC source : PIC_OFFSET_TABLE_REGNUM
       }
-      NR_PIC_OFFSET_REG = NR_R9;
+      NR_PIC_OFFSET_REG = NR_INVALID;
       { Results are returned in this register (32-bit values) }
-      NR_FUNCTION_RETURN_REG = NR_R24;
-      RS_FUNCTION_RETURN_REG = RS_R24;
+      NR_FUNCTION_RETURN_REG = NR_HL;
+      RS_FUNCTION_RETURN_REG = RS_HL;
       { Low part of 64bit return value }
-      NR_FUNCTION_RETURN64_LOW_REG = NR_R22;
-      RS_FUNCTION_RETURN64_LOW_REG = RS_R22;
+      NR_FUNCTION_RETURN64_LOW_REG = NR_HL;
+      RS_FUNCTION_RETURN64_LOW_REG = RS_HL;
       { High part of 64bit return value }
-      NR_FUNCTION_RETURN64_HIGH_REG = NR_R1;
-      RS_FUNCTION_RETURN64_HIGH_REG = RS_R1;
+      NR_FUNCTION_RETURN64_HIGH_REG = NR_BC;
+      RS_FUNCTION_RETURN64_HIGH_REG = RS_BC;
       { The value returned from a function is available in this register }
       NR_FUNCTION_RESULT_REG = NR_FUNCTION_RETURN_REG;
       RS_FUNCTION_RESULT_REG = RS_FUNCTION_RETURN_REG;
@@ -267,8 +248,8 @@ unit cpubase;
       { Offset where the parent framepointer is pushed }
       PARENT_FRAMEPOINTER_OFFSET = 0;
 
-      NR_DEFAULTFLAGS = NR_SREG;
-      RS_DEFAULTFLAGS = RS_SREG;
+      NR_DEFAULTFLAGS = NR_F;
+      RS_DEFAULTFLAGS = RS_F;
 
 {*****************************************************************************
                        GCC /ABI linking information

compiler/z80/cpupara.pas

@@ -167,7 +167,7 @@ unit cpupara;
             result:=not(def.size in [1,2,4]);
           }
           else
-            if (def.size > 8) then
+            if def.size>4 then
               result:=true
             else
               result:=inherited ret_in_param(def,pd);
@@ -177,7 +177,7 @@ unit cpupara;
 
     procedure tcpuparamanager.init_values(var curintreg, curfloatreg, curmmreg: tsuperregister; var cur_stack_offset: aword);
       begin
-        curintreg:=RS_R25;
+        curintreg:=RS_HL;
         curfloatreg:=RS_INVALID;
         curmmreg:=RS_INVALID;
         cur_stack_offset:=0;
@@ -204,7 +204,7 @@ unit cpupara;
         begin
           { In case of po_delphi_nested_cc, the parent frame pointer
             is always passed on the stack. }
-           if (nextintreg>RS_R9) and
+           if (nextintreg<>RS_HL) and
               (not(vo_is_parentfp in hp.varoptions) or
                not(po_delphi_nested_cc in p.procoptions)) then
              begin
@@ -247,7 +247,7 @@ unit cpupara;
                 paraloc:=hp.paraloc[side].add_location;
                 { hack: the paraloc must be valid, but is not actually used }
                 paraloc^.loc:=LOC_REGISTER;
-                paraloc^.register:=NR_R25;
+                paraloc^.register:=NR_HL;
                 paraloc^.size:=OS_ADDR;
                 paraloc^.def:=voidpointertype;
                 break;
@@ -301,11 +301,11 @@ unit cpupara;
                    by adding paralen mod 2, make the size even
                  }
                  nextintreg:=curintreg-(paralen+(paralen mod 2))+1;
-                 if nextintreg>=RS_R8 then
+                 if nextintreg>=RS_HL then
                    curintreg:=nextintreg-1
                  else
                    begin
-                     curintreg:=RS_R7;
+                     curintreg:=RS_HL;
                      loc:=LOC_REFERENCE;
                    end;
                end;
@@ -336,7 +336,7 @@ unit cpupara;
                  case loc of
                     LOC_REGISTER:
                       begin
-                        if nextintreg>=RS_R8 then
+                        if nextintreg>=RS_HL then
                           begin
                             paraloc^.loc:=LOC_REGISTER;
                             paraloc^.size:=OS_8;
@@ -456,47 +456,48 @@ unit cpupara;
         else
           begin
             case retcgsize of
-              OS_64,OS_S64:
-                begin
-                  for reg:=NR_R18 to NR_R25 do
-                    begin
-                      paraloc^.loc:=LOC_REGISTER;
-                      paraloc^.register:=reg;
-                      paraloc^.size:=OS_8;
-                      paraloc^.def:=u8inttype;
-                      if reg<>NR_R25 then
-                        paraloc:=result.add_location;
-                    end;
-                end;
               OS_32,OS_S32:
                 begin
-                  for reg:=NR_R22 to NR_R25 do
-                    begin
-                      paraloc^.loc:=LOC_REGISTER;
-                      paraloc^.register:=reg;
-                      paraloc^.size:=OS_8;
-                      paraloc^.def:=u8inttype;
-                      if reg<>NR_R25 then
-                        paraloc:=result.add_location;
-                    end;
+                  paraloc^.loc:=LOC_REGISTER;
+                  paraloc^.register:=NR_L;
+                  paraloc^.size:=OS_8;
+                  paraloc^.def:=u8inttype;
+
+                  paraloc:=result.add_location;
+                  paraloc^.loc:=LOC_REGISTER;
+                  paraloc^.register:=NR_H;
+                  paraloc^.size:=OS_8;
+                  paraloc^.def:=u8inttype;
+
+                  paraloc:=result.add_location;
+                  paraloc^.loc:=LOC_REGISTER;
+                  paraloc^.register:=NR_C;
+                  paraloc^.size:=OS_8;
+                  paraloc^.def:=u8inttype;
+
+                  paraloc:=result.add_location;
+                  paraloc^.loc:=LOC_REGISTER;
+                  paraloc^.register:=NR_B;
+                  paraloc^.size:=OS_8;
+                  paraloc^.def:=u8inttype;
                 end;
               OS_16,OS_S16:
                 begin
                   paraloc^.loc:=LOC_REGISTER;
-                  paraloc^.register:=NR_R24;
+                  paraloc^.register:=NR_L;
                   paraloc^.size:=OS_8;
                   paraloc^.def:=u8inttype;
 
                   paraloc:=result.add_location;
                   paraloc^.loc:=LOC_REGISTER;
-                  paraloc^.register:=NR_R25;
+                  paraloc^.register:=NR_H;
                   paraloc^.size:=OS_8;
                   paraloc^.def:=u8inttype;
                 end;
               OS_8,OS_S8:
                 begin
                   paraloc^.loc:=LOC_REGISTER;
-                  paraloc^.register:=NR_R24;
+                  paraloc^.register:=NR_HL;
                   paraloc^.size:=OS_8;
                   paraloc^.def:=u8inttype;
                 end;

compiler/z80/rgcpu.pas

@@ -95,20 +95,22 @@ unit rgcpu;
         helplist : TAsmList;
         hreg     : tregister;
       begin
-        if abs(spilltemp.offset)>63 then
+        if abs(spilltemp.offset)>127 then
           begin
-            helplist:=TAsmList.create;
-
-            helplist.concat(taicpu.op_reg_const(A_LDI,NR_R26,lo(word(spilltemp.offset))));
-            helplist.concat(taicpu.op_reg_const(A_LDI,NR_R27,hi(word(spilltemp.offset))));
-            helplist.concat(taicpu.op_reg_reg(A_ADD,NR_R26,spilltemp.base));
-            helplist.concat(taicpu.op_reg_reg(A_ADC,NR_R27,GetNextReg(spilltemp.base)));
-
-            reference_reset_base(tmpref,NR_R26,0,1,[]);
-            helpins:=spilling_create_load(tmpref,tempreg);
-            helplist.concat(helpins);
-            list.insertlistafter(pos,helplist);
-            helplist.free;
+            Internalerror(2017032701);
+//
+//            helplist:=TAsmList.create;
+//
+//            helplist.concat(taicpu.op_reg_const(A_LDI,NR_R26,lo(word(spilltemp.offset))));
+//            helplist.concat(taicpu.op_reg_const(A_LDI,NR_R27,hi(word(spilltemp.offset))));
+//            helplist.concat(taicpu.op_reg_reg(A_ADD,NR_R26,spilltemp.base));
+//            helplist.concat(taicpu.op_reg_reg(A_ADC,NR_R27,GetNextReg(spilltemp.base)));
+//
+//            reference_reset_base(tmpref,NR_R26,0,1,[]);
+//            helpins:=spilling_create_load(tmpref,tempreg);
+//            helplist.concat(helpins);
+//            list.insertlistafter(pos,helplist);
+//            helplist.free;
           end
         else
           inherited;
@@ -121,19 +123,21 @@ unit rgcpu;
         helplist : TAsmList;
         hreg     : tregister;
       begin
-        if abs(spilltemp.offset)>63 then
+        if abs(spilltemp.offset)>127 then
           begin
-            helplist:=TAsmList.create;
-
-            helplist.concat(taicpu.op_reg_const(A_LDI,NR_R26,lo(word(spilltemp.offset))));
-            helplist.concat(taicpu.op_reg_const(A_LDI,NR_R27,hi(word(spilltemp.offset))));
-            helplist.concat(taicpu.op_reg_reg(A_ADD,NR_R26,spilltemp.base));
-            helplist.concat(taicpu.op_reg_reg(A_ADC,NR_R27,GetNextReg(spilltemp.base)));
-
-            reference_reset_base(tmpref,NR_R26,0,1,[]);
-            helplist.concat(spilling_create_store(tempreg,tmpref));
-            list.insertlistafter(pos,helplist);
-            helplist.free;
+            Internalerror(2017032702);
+//
+//            helplist:=TAsmList.create;
+//
+//            helplist.concat(taicpu.op_reg_const(A_LDI,NR_R26,lo(word(spilltemp.offset))));
+//            helplist.concat(taicpu.op_reg_const(A_LDI,NR_R27,hi(word(spilltemp.offset))));
+//            helplist.concat(taicpu.op_reg_reg(A_ADD,NR_R26,spilltemp.base));
+//            helplist.concat(taicpu.op_reg_reg(A_ADC,NR_R27,GetNextReg(spilltemp.base)));
+//
+//            reference_reset_base(tmpref,NR_R26,0,1,[]);
+//            helplist.concat(spilling_create_store(tempreg,tmpref));
+//            list.insertlistafter(pos,helplist);
+//            helplist.free;
           end
         else
           inherited;

compiler/z80/rz80con.inc

@@ -1,35 +1,27 @@
 { don't edit, this file is generated from z80reg.dat }
 NR_NO = tregister($00000000);
-NR_R0 = tregister($01000000);
-NR_R1 = tregister($01000001);
-NR_R2 = tregister($01000002);
-NR_R3 = tregister($01000003);
-NR_R4 = tregister($01000004);
-NR_R5 = tregister($01000005);
-NR_R6 = tregister($01000006);
-NR_R7 = tregister($01000007);
-NR_R8 = tregister($01000008);
-NR_R9 = tregister($01000009);
-NR_R10 = tregister($0100000a);
-NR_R11 = tregister($0100000b);
-NR_R12 = tregister($0100000c);
-NR_R13 = tregister($0100000d);
-NR_R14 = tregister($0100000e);
-NR_R15 = tregister($0100000f);
-NR_R16 = tregister($01000010);
-NR_R17 = tregister($01000011);
-NR_R18 = tregister($01000012);
-NR_R19 = tregister($01000013);
-NR_R20 = tregister($01000014);
-NR_R21 = tregister($01000015);
-NR_R22 = tregister($01000016);
-NR_R23 = tregister($01000017);
-NR_R24 = tregister($01000018);
-NR_R25 = tregister($01000019);
-NR_R26 = tregister($0100001a);
-NR_R27 = tregister($0100001b);
-NR_R28 = tregister($0100001c);
-NR_R29 = tregister($0100001d);
-NR_R30 = tregister($0100001e);
-NR_R31 = tregister($0100001f);
-NR_SREG = tregister($05000000);
+NR_A = tregister($01010000);
+NR_C = tregister($01010001);
+NR_B = tregister($01020001);
+NR_BC = tregister($01030001);
+NR_E = tregister($01010002);
+NR_D = tregister($01020002);
+NR_DE = tregister($01030002);
+NR_L = tregister($01010003);
+NR_H = tregister($01020003);
+NR_HL = tregister($01030003);
+NR_IX = tregister($01030003);
+NR_IY = tregister($01030005);
+NR_A_ = tregister($01010006);
+NR_C_ = tregister($01010007);
+NR_B_ = tregister($01020008);
+NR_E_ = tregister($01010009);
+NR_D_ = tregister($0102000a);
+NR_L_ = tregister($0101000b);
+NR_H_ = tregister($0102000c);
+NR_SP = tregister($05000000);
+NR_PC = tregister($05000001);
+NR_R = tregister($050000002);
+NR_F = tregister($05000003);
+NR_F_ = tregister($05000004);
+NR_I = tregister($05000005);

compiler/z80/rz80dwa.inc

@@ -1,5 +1,4 @@
 { don't edit, this file is generated from z80reg.dat }
--1,
 0,
 1,
 2,
@@ -25,11 +24,4 @@
 22,
 23,
 24,
-25,
-26,
-27,
-28,
-29,
-30,
-31,
-0
+25

compiler/z80/rz80nor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from z80reg.dat }
-34
+26

compiler/z80/rz80num.inc

@@ -1,35 +1,27 @@
 { don't edit, this file is generated from z80reg.dat }
 tregister($00000000),
-tregister($01000000),
-tregister($01000001),
-tregister($01000002),
-tregister($01000003),
-tregister($01000004),
-tregister($01000005),
-tregister($01000006),
-tregister($01000007),
-tregister($01000008),
-tregister($01000009),
-tregister($0100000a),
-tregister($0100000b),
-tregister($0100000c),
-tregister($0100000d),
-tregister($0100000e),
-tregister($0100000f),
-tregister($01000010),
-tregister($01000011),
-tregister($01000012),
-tregister($01000013),
-tregister($01000014),
-tregister($01000015),
-tregister($01000016),
-tregister($01000017),
-tregister($01000018),
-tregister($01000019),
-tregister($0100001a),
-tregister($0100001b),
-tregister($0100001c),
-tregister($0100001d),
-tregister($0100001e),
-tregister($0100001f),
-tregister($05000000)
+tregister($01010000),
+tregister($01010001),
+tregister($01020001),
+tregister($01030001),
+tregister($01010002),
+tregister($01020002),
+tregister($01030002),
+tregister($01010003),
+tregister($01020003),
+tregister($01030003),
+tregister($01030003),
+tregister($01030005),
+tregister($01010006),
+tregister($01010007),
+tregister($01020008),
+tregister($01010009),
+tregister($0102000a),
+tregister($0101000b),
+tregister($0102000c),
+tregister($05000000),
+tregister($05000001),
+tregister($050000002),
+tregister($05000003),
+tregister($05000004),
+tregister($05000005)

compiler/z80/rz80rni.inc

@@ -2,34 +2,26 @@
 0,
 1,
 2,
-3,
-4,
 5,
-6,
-7,
 8,
-9,
-10,
-11,
-12,
 13,
 14,
-15,
 16,
-17,
 18,
+3,
+6,
+9,
+15,
+17,
 19,
+4,
+7,
+10,
+11,
+12,
 20,
-21,
 22,
+21,
 23,
 24,
-25,
-26,
-27,
-28,
-29,
-30,
-31,
-32,
-33
+25

compiler/z80/rz80sri.inc

@@ -1,35 +1,27 @@
 { don't edit, this file is generated from z80reg.dat }
 0,
 1,
-2,
-11,
-12,
 13,
-14,
-15,
-16,
-17,
-18,
-19,
-20,
 3,
-21,
-22,
-23,
-24,
-25,
-26,
-27,
-28,
-29,
-30,
+15,
 4,
-31,
-32,
-5,
+2,
+14,
 6,
+17,
 7,
-8,
+5,
+16,
+23,
+24,
 9,
+19,
 10,
-33
+25,
+11,
+12,
+8,
+18,
+21,
+22,
+20

compiler/z80/rz80sta.inc

@@ -1,5 +1,4 @@
 { don't edit, this file is generated from z80reg.dat }
--1,
 0,
 1,
 2,
@@ -25,11 +24,4 @@
 22,
 23,
 24,
-25,
-26,
-27,
-28,
-29,
-30,
-31,
-0
+25

compiler/z80/rz80std.inc

@@ -1,35 +1,27 @@
 { don't edit, this file is generated from z80reg.dat }
 'INVALID',
-'r0',
-'r1',
-'r2',
-'r3',
-'r4',
-'r5',
-'r6',
-'r7',
-'r8',
-'r9',
-'r10',
-'r11',
-'r12',
-'r13',
-'r14',
-'r15',
-'r16',
-'r17',
-'r18',
-'r19',
-'r20',
-'r21',
-'r22',
-'r23',
-'r24',
-'r25',
-'r26',
-'r27',
-'r28',
-'r29',
-'r30',
-'r31',
-'sreg'
+'a',
+'c',
+'b',
+'bc',
+'e',
+'d',
+'de',
+'l',
+'h',
+'hl',
+'ix',
+'iy',
+'a''',
+'c''',
+'b''',
+'e''',
+'d''',
+'l''',
+'h''',
+'sp',
+'pc',
+'r',
+'f',
+'f''',
+'i'

compiler/z80/rz80sup.inc

@@ -1,35 +1,27 @@
 { don't edit, this file is generated from z80reg.dat }
-RS_NO = $00;
-RS_R0 = $00;
-RS_R1 = $01;
-RS_R2 = $02;
-RS_R3 = $03;
-RS_R4 = $04;
-RS_R5 = $05;
-RS_R6 = $06;
-RS_R7 = $07;
-RS_R8 = $08;
-RS_R9 = $09;
-RS_R10 = $0a;
-RS_R11 = $0b;
-RS_R12 = $0c;
-RS_R13 = $0d;
-RS_R14 = $0e;
-RS_R15 = $0f;
-RS_R16 = $10;
-RS_R17 = $11;
-RS_R18 = $12;
-RS_R19 = $13;
-RS_R20 = $14;
-RS_R21 = $15;
-RS_R22 = $16;
-RS_R23 = $17;
-RS_R24 = $18;
-RS_R25 = $19;
-RS_R26 = $1a;
-RS_R27 = $1b;
-RS_R28 = $1c;
-RS_R29 = $1d;
-RS_R30 = $1e;
-RS_R31 = $1f;
-RS_SREG = $00;
+RS_NO = 0;
+RS_A = 0;
+RS_C = 1;
+RS_B = 1;
+RS_BC = 1;
+RS_E = 2;
+RS_D = 2;
+RS_DE = 2;
+RS_L = 3;
+RS_H = 3;
+RS_HL = 3;
+RS_IX = 3;
+RS_IY = 5;
+RS_A_ = 6;
+RS_C_ = 7;
+RS_B_ = 8;
+RS_E_ = 9;
+RS_D_ = 10;
+RS_L_ = 11;
+RS_H_ = 12;
+RS_SP = 0;
+RS_PC = 1;
+RS_R = 2;
+RS_F = 3;
+RS_F_ = 4;
+RS_I = 5;

compiler/z80/z80reg.dat

@@ -1,44 +1,34 @@
 ;
-; AVR registers
+; Z80 registers
 ;
 ; layout
-; <name>,<type>,<value>,<stdname>,<stab idx>,<dwarf idx>
+; <name>,<value>,<stdname>,<stabidx>,<dwarfidx>
 ;
-NO,$00,$00,INVALID,-1,-1
-
-R0,$01,$00,r0,0,0
-R1,$01,$01,r1,1,1
-R2,$01,$02,r2,2,2
-R3,$01,$03,r3,3,3
-R4,$01,$04,r4,4,4
-R5,$01,$05,r5,5,5
-R6,$01,$06,r6,6,6
-R7,$01,$07,r7,7,7
-R8,$01,$08,r8,8,8
-R9,$01,$09,r9,9,9
-R10,$01,$0a,r10,10,10
-R11,$01,$0b,r11,11,11
-R12,$01,$0c,r12,12,12
-R13,$01,$0d,r13,13,13
-R14,$01,$0e,r14,14,14
-R15,$01,$0f,r15,15,15
-R16,$01,$10,r16,16,16
-R17,$01,$11,r17,17,17
-R18,$01,$12,r18,18,18
-R19,$01,$13,r19,19,19
-R20,$01,$14,r20,20,20
-R21,$01,$15,r21,21,21
-R22,$01,$16,r22,22,22
-R23,$01,$17,r23,23,23
-R24,$01,$18,r24,24,24
-R25,$01,$19,r25,25,25
-R26,$01,$1a,r26,26,26
-R27,$01,$1b,r27,27,27
-R28,$01,$1c,r28,28,28
-R29,$01,$1d,r29,29,29
-R30,$01,$1e,r30,30,30
-R31,$01,$1f,r31,31,31
-
-SREG,$05,$00,sreg,0,0
+NO,$00000000,INVALID,0,0
 
+A,$01010000,a,1,1
+C,$01010001,c,2,2
+B,$01020001,b,3,3
+BC,$01030001,bc,4,4
+E,$01010002,e,5,5
+D,$01020002,d,6,6
+DE,$01030002,de,7,7
+L,$01010003,l,8,8
+H,$01020003,h,9,9
+HL,$01030003,hl,10,10
+IX,$01030003,ix,11,11
+IY,$01030005,iy,12,12
+A_,$01010006,a'',13,13
+C_,$01010007,c'',14,14
+B_,$01020008,b'',15,15
+E_,$01010009,e'',16,16
+D_,$0102000a,d'',17,17
+L_,$0101000b,l'',18,18
+H_,$0102000c,h'',19,19
 
+SP,$05000000,sp,20,20
+PC,$05000001,pc,21,21
+R,$050000002,r,22,22
+F,$05000003,f,23,23
+F_,$05000004,f'',24,24
+I,$05000005,i,25,25