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@@ -111,6 +111,11 @@ implementation
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function trgx86.do_spill_replace(list:TAsmList;instr:taicpu;orgreg:tsuperregister;const spilltemp:treference):boolean;
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+
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+ {Decide wether a "replace" spill is possible, i.e. wether we can replace a register
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+ in an instruction by a memory reference. For example, in "mov ireg26d,0", the imaginary
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+ register ireg26d can be replaced by a memory reference.}
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+
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var
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replaceoper : longint;
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begin
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@@ -146,69 +151,87 @@ implementation
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(get_alias(getsupreg(oper[1]^.reg))=orgreg) then
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replaceoper:=1
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else
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- internalerror(200410106);
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- case replaceoper of
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- 0 :
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- begin
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- { Some instructions don't allow memory references
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- for source }
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- case instr.opcode of
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- A_BT,
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- A_BTS,
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- A_BTC,
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- A_BTR :
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- replaceoper:=-1;
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- end;
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- end;
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- 1 :
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- begin
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- { Some instructions don't allow memory references
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- for destination }
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- case instr.opcode of
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- A_MOVZX,
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- A_MOVSX,
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- A_MULSS,
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- A_MULSD,
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- A_SUBSS,
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- A_SUBSD,
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- A_ADDSD,
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- A_ADDSS,
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- A_DIVSD,
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- A_DIVSS,
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- A_SHLD,
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- A_SHRD,
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- A_CVTDQ2PD,
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- A_CVTDQ2PS,
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- A_CVTPD2DQ,
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- A_CVTPD2PI,
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- A_CVTPD2PS,
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- A_CVTPI2PD,
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- A_CVTPS2DQ,
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- A_CVTPS2PD,
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- A_CVTSD2SI,
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- A_CVTSD2SS,
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- A_CVTSI2SD,
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- A_CVTSS2SD,
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- A_CVTTPD2PI,
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- A_CVTTPD2DQ,
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- A_CVTTPS2DQ,
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- A_CVTTSD2SI,
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- A_CVTPI2PS,
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- A_CVTPS2PI,
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- A_CVTSI2SS,
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- A_CVTSS2SI,
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- A_CVTTPS2PI,
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- A_CVTTSS2SI,
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- A_IMUL,
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- A_XORPD,
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- A_XORPS,
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- A_ORPD,
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- A_ORPS,
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- A_ANDPD,
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- A_ANDPS:
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- replaceoper:=-1;
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- end;
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- end;
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+ internalerror(200704281);
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+ end;
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+ if (oper[0]^.typ=top_reg) and
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+ (oper[1]^.typ=top_const) then
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+ begin
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+ if (getregtype(oper[0]^.reg)=regtype) and
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+ (get_alias(getsupreg(oper[0]^.reg))=orgreg) then
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+ replaceoper:=0
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+ else
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+ internalerror(200704282);
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+ end;
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+ if (oper[0]^.typ=top_const) and
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+ (oper[1]^.typ=top_reg) then
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+ begin
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+ if (getregtype(oper[1]^.reg)=regtype) and
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+ (get_alias(getsupreg(oper[1]^.reg))=orgreg) then
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+ replaceoper:=1
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+ else
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+ internalerror(200704283);
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+ end;
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+ case replaceoper of
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+ 0 :
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+ begin
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+ { Some instructions don't allow memory references
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+ for source }
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+ case instr.opcode of
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+ A_BT,
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+ A_BTS,
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+ A_BTC,
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+ A_BTR :
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+ replaceoper:=-1;
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+ end;
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+ end;
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+ 1 :
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+ begin
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+ { Some instructions don't allow memory references
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+ for destination }
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+ case instr.opcode of
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+ A_MOVZX,
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+ A_MOVSX,
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+ A_MULSS,
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+ A_MULSD,
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+ A_SUBSS,
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+ A_SUBSD,
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+ A_ADDSD,
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+ A_ADDSS,
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+ A_DIVSD,
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+ A_DIVSS,
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+ A_SHLD,
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+ A_SHRD,
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+ A_CVTDQ2PD,
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+ A_CVTDQ2PS,
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+ A_CVTPD2DQ,
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+ A_CVTPD2PI,
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+ A_CVTPD2PS,
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+ A_CVTPI2PD,
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+ A_CVTPS2DQ,
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+ A_CVTPS2PD,
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+ A_CVTSD2SI,
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+ A_CVTSD2SS,
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+ A_CVTSI2SD,
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+ A_CVTSS2SD,
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+ A_CVTTPD2PI,
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+ A_CVTTPD2DQ,
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+ A_CVTTPS2DQ,
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+ A_CVTTSD2SI,
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+ A_CVTPI2PS,
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+ A_CVTPS2PI,
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+ A_CVTSI2SS,
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+ A_CVTSS2SI,
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+ A_CVTTPS2PI,
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+ A_CVTTSS2SI,
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+ A_IMUL,
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+ A_XORPD,
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+ A_XORPS,
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+ A_ORPD,
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+ A_ORPS,
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+ A_ANDPD,
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+ A_ANDPS:
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+ replaceoper:=-1;
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+ end;
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end;
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end;
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end;
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